Add watchdog support to iwg20m and iwg22m

Hello Ben,

this series backports watchdog support for iwg20m and iwg22m.

There is a dependency with series:
https://lists.cip-project.org/pipermail/cip-dev/2018-July/001415.html

This work is based on top of linux-4.4.y-cip, commit 4d769b2b8749e89dfc7ea179a44f652dcfbedb37 ("PM / OPP: Move error message to debug level").

Thanks,
Fab

Fabrizio Castro (15):
ARM: shmobile: Remove shmobile_boot_arg from
shmobile_smp_apmu_setup_boot
ARM: shmobile: Add watchdog support
clk: shmobile: rcar-gen2: Init R-Car reset IP
ARM: dts: r8a7743: Register rwdt and intc-sys clocks
ARM: dts: r8a7745: Register rwdt and intc-sys clocks
watchdog: renesas_wdt: Add suspend/resume support
watchdog: renesas_wdt: Add restart handler
ARM: shmobile: rcar-gen2: Add watchdog support
ARM: dts: r8a7743: Adjust SMP routine size
ARM: dts: r8a7745: Adjust SMP routine size
ARM: dts: r8a7743: Add watchdog support to SoC dtsi
ARM: dts: r8a7745: Add watchdog support to SoC dtsi
ARM: dts: iwg20m: Add watchdog support to SoM dtsi
ARM: dts: iwg22m: Add watchdog support to SoM dtsi
ARM: shmobile: defconfig: Enable RENESAS_WDT_GEN

Geert Uytterhoeven (12):
ARM: shmobile: Remove shmobile_boot_arg
ARM: shmobile: r8a7779: Remove remainings of removed SCU boot setup
code
soc: renesas: Add R-Car RST driver
reset: Add renesas,rst DT bindings
clk: renesas: mstp: Make INTC-SYS a critical clock
ARM: shmobile: rcar-gen2: Add more register documentation
ARM: shmobile: rcar-gen2: Use ICRAM1 for jump stub on all SoCs
ARM: shmobile: rcar-gen2: Obtain jump stub region from DT
ARM: dts: r8a7743: Add Inter Connect RAM
ARM: dts: r8a7743: Reserve SRAM for the SMP jump stub
ARM: dts: r8a7745: Add Inter Connect RAM
ARM: dts: r8a7745: Reserve SRAM for the SMP jump stub

Lee Jones (2):
clk: Allow clocks to be marked as CRITICAL
clk: WARN_ON about to disable a critical clock

Maxime Ripard (1):
clk: fix critical clock locking

Sergei Shtylyov (2):
ARM: dts: r8a7743: initial SoC device tree
ARM: dts: r8a7745: initial SoC device tree

Veeraiyan Chidambaram (1):
watchdog: renesas-wdt: Add support for WDIOF_CARDRESET

Wolfram Sang (9):
watchdog: renesas-wdt: add driver
watchdog: renesas_wdt: avoid (theoretical) type overflow
watchdog: renesas_wdt: check rate also for upper limit
watchdog: renesas_wdt: don't round closest with get_timeleft
watchdog: renesas_wdt: apply better precision
watchdog: renesas_wdt: add another divider option
watchdog: renesas_wdt: consistently use RuntimePM for clock management
watchdog: renesas_wdt: make 'clk' a variable local to probe()
watchdog: renesas_wdt: update copyright dates

 .../devicetree/bindings/reset/renesas,rst.txt      |  24 ++
 .../devicetree/bindings/watchdog/renesas-wdt.txt   |  33 +++
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi              |   5 +
 arch/arm/boot/dts/r8a7743.dtsi                     |  46 +++-
 arch/arm/boot/dts/r8a7745-iwg22m.dtsi              |   5 +
 arch/arm/boot/dts/r8a7745.dtsi                     |  44 +++-
 arch/arm/configs/shmobile_defconfig                |   1 +
 arch/arm/mach-shmobile/common.h                    |   5 +-
 arch/arm/mach-shmobile/headsmp.S                   |  63 ++++-
 arch/arm/mach-shmobile/platsmp-apmu.c              |   3 +-
 arch/arm/mach-shmobile/platsmp-scu.c               |   1 -
 arch/arm/mach-shmobile/pm-rcar-gen2.c              |  97 +++++--
 arch/arm/mach-shmobile/smp-r8a7779.c               |   2 -
 drivers/clk/clk.c                                  |  16 ++
 drivers/clk/shmobile/clk-mstp.c                    |   5 +
 drivers/clk/shmobile/clk-rcar-gen2.c               |   3 +
 drivers/soc/Makefile                               |   1 +
 drivers/soc/renesas/Makefile                       |   1 +
 drivers/soc/renesas/rcar-rst.c                     |  81 ++++++
 drivers/watchdog/Kconfig                           |   8 +
 drivers/watchdog/Makefile                          |   1 +
 drivers/watchdog/renesas_wdt.c                     | 285 +++++++++++++++++++++
 include/linux/clk-provider.h                       |   1 +
 include/linux/soc/renesas/rcar-rst.h               |   6 +
 24 files changed, 694 insertions(+), 43 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/renesas,rst.txt
 create mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
 create mode 100644 drivers/soc/renesas/Makefile
 create mode 100644 drivers/soc/renesas/rcar-rst.c
 create mode 100644 drivers/watchdog/renesas_wdt.c
 create mode 100644 include/linux/soc/renesas/rcar-rst.h

2.7.4

From: Geert Uytterhoeven <[email protected]>

CPU boot configuration writes to shmobile_boot_arg, which is located in the .text section, and thus should not be written to.

As of commit 1d33a354bbb618ba ("ARM: shmobile: Per-CPU SMP boot / sleep code for SCU SoCs"), and ignoring accidental remainings, shmobile_boot_arg is always set to MPIDR_HWID_BITMASK by C code. Hence we can just hardcode this in the assembler code, and remove the variable, and thus also remove the need to write to this variable.

---
 arch/arm/mach-shmobile/common.h       | 1 -
 arch/arm/mach-shmobile/headsmp.S      | 8 ++------
 arch/arm/mach-shmobile/platsmp-apmu.c | 1 -
 arch/arm/mach-shmobile/platsmp-scu.c  | 1 -
 4 files changed, 2 insertions(+), 9 deletions(-)

index 7b20b1b..f1ffff7 100644
@@ -5,7 +5,6 @@ extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
-extern unsigned long shmobile_boot_arg;
 extern unsigned long shmobile_boot_size;
 extern void shmobile_smp_boot(void);
 extern void shmobile_smp_sleep(void);

index 94d86ed..32e0bf6 100644
@@ -24,7 +24,6 @@
 	.arm
 	.align  12
 ENTRY(shmobile_boot_vector)
-	ldr     r0, 2f
 	ldr     r1, 1f
 	bx	r1
 

@@ -34,9 +33,6 @@ ENDPROC(shmobile_boot_vector)
 	.globl	shmobile_boot_fn
 shmobile_boot_fn:
 1:	.space	4
-	.globl	shmobile_boot_arg
-shmobile_boot_arg:
-2:	.space	4
 	.globl	shmobile_boot_size
 shmobile_boot_size:
 	.long	. - shmobile_boot_vector

@@ -46,9 +42,9 @@ shmobile_boot_size:
  */
 
 ENTRY(shmobile_smp_boot)
-						@ r0 = MPIDR_HWID_BITMASK
 	mrc	p15, 0, r1, c0, c0, 5		@ r1 = MPIDR
-	and	r0, r1, r0			@ r0 = cpu_logical_map() value
+	and	r0, r1, #0xffffff		@ MPIDR_HWID_BITMASK
+						@ r0 = cpu_logical_map() value
 	mov	r1, #0				@ r1 = CPU index
 	adr	r2, 1f
 	ldmia	r2, {r5, r6, r7}

index ffae187..067b252 100644
@@ -195,7 +195,6 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 {
 	/* install boot code shared by all CPUs */
 	shmobile_smp_apmu_setup_boot();
-	shmobile_boot_arg = MPIDR_HWID_BITMASK;
 
 	/* perform per-cpu setup */
 	apmu_parse_cfg(apmu_init_cpu, apmu_config, num);

index 6466311..1f2e2e8 100644
@@ -41,7 +41,6 @@ void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus)
 {
 	/* install boot code shared by all CPUs */
 	shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
-	shmobile_boot_arg = MPIDR_HWID_BITMASK;
 
 	/* enable SCU and cache coherency on booting CPU */
 	scu_enable(shmobile_scu_base);

2.7.4

This commit removes shmobile_boot_arg from shmobile_smp_apmu_setup_boot as not used anymore.

---
 arch/arm/mach-shmobile/platsmp-apmu.c | 1 -
 1 file changed, 1 deletion(-)

index 067b252..66fe008 100644
@@ -186,7 +186,6 @@ static void __init shmobile_smp_apmu_setup_boot(void)
 {
 	/* install boot code shared by all CPUs */
 	shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
-	shmobile_boot_arg = MPIDR_HWID_BITMASK;
 }
 
 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,

2.7.4

From: Geert Uytterhoeven <[email protected]>

Commit 0ca2894b5a900709 ("ARM: shmobile: Use shared SCU SMP boot code on r8a7779") obsoleted the r8a7779-specific SCU boot code, but forgot to remove the setup of shmobile_boot_fn and shmobile_boot_arg, which is overwritten by shmobile_smp_scu_prepare_cpus().

Note that shmobile_scu_base wasn't initialized at that point yet anyway.

---
 arch/arm/mach-shmobile/smp-r8a7779.c | 2 --
 1 file changed, 2 deletions(-)

index 353562b8..5c2d80f 100644
@@ -92,8 +92,6 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
 	/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
 	__raw_writel(__pa(shmobile_boot_vector), AVECR);
-	shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
-	shmobile_boot_arg = (unsigned long)shmobile_scu_base;
 
 	/* setup r8a7779 specific SCU bits */
 	shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);

2.7.4

On R-Car Gen2 and RZ/G1 platforms, we use the SBAR registers to make non boot CPUs run a routine designed to bring up SMP and deal with hot plug. The value contained in the SBAR registers is not initialized by a WDT triggered reset, which means that after a WDT triggered reset we jump to the SMP bring up routine, preventing the system from executing the bootrom code.

The purpose of this patch is to jump to the bootrom code in case of a WDT triggered reset, and keep the SMP functionality untouched. In order to tell if the code had been called due to the WDT overflowing we are testing WOVF from register RWTCSRA.

The new function shmobile_boot_vector_gen2 isn't replacing shmobile_boot_vector for backward compatibility reasons. The kernel will install the best option (either shmobile_boot_vector or shmobile_boot_vector_gen2) to ICRAM1 after parsing the device tree, according to the amount of memory available.

Since shmobile_boot_vector has become bigger, "reg" property of nodes compatible with "renesas,smp-sram" now need to be set to a value greater or equal to "<0 0x60>".

---
 arch/arm/mach-shmobile/common.h  |  4 +++
 arch/arm/mach-shmobile/headsmp.S | 55 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

index f1ffff7..5c7f24e 100644
@@ -6,6 +6,10 @@ extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
 extern unsigned long shmobile_boot_size;
+extern void shmobile_boot_vector_gen2(void);
+extern unsigned long shmobile_boot_fn_gen2;
+extern unsigned long shmobile_boot_cpu_gen2;
+extern unsigned long shmobile_boot_size_gen2;
 extern void shmobile_smp_boot(void);
 extern void shmobile_smp_sleep(void);
 extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,

2.7.4

From: Geert Uytterhoeven <[email protected]>

Add a driver for the Renesas R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST module.

For now this driver just provides an API to obtain the state of the mode pins, as latched at reset time. As this is typically called from the probe function of a clock driver, which can run much earlier than any initcall, calling rcar_rst_read_mode_pins() just forces an early initialization of the driver.

Despite the current simple and almost identical handling for all supported SoCs, the driver matches against SoC-specific compatible values, as the features provided by the hardware module differ a lot across the various SoC families and members.

(Added renesas directory to driver/soc/Makefile. Modified drivers/soc/renesas/Makefile to only compile rcar-rst.c for R-Car Gen2. Removed R-Car Gen3 and R-Car Gen1 from rcar_rst_matches and stripped read mode pins logic from the driver. Got rid of rcar_rst_read_mode_pins, advertising rcar_rst_init instead)

---
 drivers/soc/Makefile                 |  1 +
 drivers/soc/renesas/Makefile         |  1 +
 drivers/soc/renesas/rcar-rst.c       | 81 ++++++++++++++++++++++++++++++++++++
 include/linux/soc/renesas/rcar-rst.h |  6 +++
 4 files changed, 89 insertions(+)
 create mode 100644 drivers/soc/renesas/Makefile
 create mode 100644 drivers/soc/renesas/rcar-rst.c
 create mode 100644 include/linux/soc/renesas/rcar-rst.h

index f2ba2e9..c87aada 100644
@@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_BRCMSTB)	+= brcmstb/
 obj-$(CONFIG_MACH_DOVE)		+= dove/
 obj-$(CONFIG_ARCH_MEDIATEK)	+= mediatek/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
+obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_ARCH_SUNXI)	+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/

new file mode 100644
index 0000000..8751756
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_RCAR_GEN2)	+= rcar-rst.o

new file mode 100644
index 0000000..6b1f492
@@ -0,0 +1,6 @@
+#ifndef __LINUX_SOC_RENESAS_RCAR_RST_H__
+#define __LINUX_SOC_RENESAS_RCAR_RST_H__
+
+void rcar_rst_init(void);
+
+#endif /* __LINUX_SOC_RENESAS_RCAR_RST_H__ */

2.7.4

[...]

Ben Hutchings, Software Developer                ?        Codethink Ltd
https://www.codethink.co.uk/                 Dale House, 35 Dale Street
                                     Manchester, M1 2HF, United Kingdom

Hello Ben,

Thank you for your feedback.

Good catch. Will delete it.

Will mention that in the commit message of V2.

Thanks,
Fab

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

From: Geert Uytterhoeven <[email protected]>

Add a driver for the Renesas R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST module.

For now this driver just provides an API to obtain the state of the mode pins, as latched at reset time. As this is typically called from the probe function of a clock driver, which can run much earlier than any initcall, calling rcar_rst_read_mode_pins() just forces an early initialization of the driver.

Despite the current simple and almost identical handling for all supported SoCs, the driver matches against SoC-specific compatible values, as the features provided by the hardware module differ a lot across the various SoC families and members.

and squashed commit 69e0d1b8db8f8cc319f966ec3eb2fffce28c4f28 into it) (Added renesas directory to driver/soc/Makefile. Modified drivers/soc/renesas/Makefile to only compile rcar-rst.c for R-Car Gen2. Removed R-Car Gen3 and R-Car Gen1 from rcar_rst_matches and stripped read mode pins logic from the driver. Got rid of rcar_rst_read_mode_pins, advertising rcar_rst_init instead)

---
v1->v2:
* deleted rcar_rst_gen1
* added reference to the upstream commit for configure operation to the changelog

 drivers/soc/Makefile                 |  1 +
 drivers/soc/renesas/Makefile         |  1 +
 drivers/soc/renesas/rcar-rst.c       | 77 ++++++++++++++++++++++++++++++++++++
 include/linux/soc/renesas/rcar-rst.h |  6 +++
 4 files changed, 85 insertions(+)
 create mode 100644 drivers/soc/renesas/Makefile
 create mode 100644 drivers/soc/renesas/rcar-rst.c
 create mode 100644 include/linux/soc/renesas/rcar-rst.h

index f2ba2e9..c87aada 100644
@@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_BRCMSTB)	+= brcmstb/
 obj-$(CONFIG_MACH_DOVE)		+= dove/
 obj-$(CONFIG_ARCH_MEDIATEK)	+= mediatek/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
+obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_ARCH_SUNXI)	+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/

new file mode 100644
index 0000000..8751756
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_RCAR_GEN2)	+= rcar-rst.o

new file mode 100644
index 0000000..6b1f492
@@ -0,0 +1,6 @@
+#ifndef __LINUX_SOC_RENESAS_RCAR_RST_H__
+#define __LINUX_SOC_RENESAS_RCAR_RST_H__
+
+void rcar_rst_init(void);
+
+#endif /* __LINUX_SOC_RENESAS_RCAR_RST_H__ */

2.7.4

From: Geert Uytterhoeven <[email protected]>

Add DT bindings for the Renesas R-Car Reset Controller (R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST).

As the features provided by the hardware module differ a lot across the various SoC families and members, only SoC-specific compatible values are defined.

For now we use the RST only for providing access to the state of the mode pins, which is needed by the clock driver.

(dropped R-Car Gen1 and Gen3 support, replaced R-Car3 example with RZ/G1M, dropped mode pins functionality description)

---
 .../devicetree/bindings/reset/renesas,rst.txt      | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/renesas,rst.txt

new file mode 100644
index 0000000..fff2e8e
@@ -0,0 +1,24 @@
+DT bindings for the Renesas R-Car and RZ/G Reset Controllers
+
+The R-Car and RZ/G Reset Controllers provide reset control.
+
+Required properties:
+  - compatible: Should be
+		  - "renesas,<soctype>-rst" for R-Car Gen2 and RZ/G
+		Examples with soctypes are:
+		  - "renesas,r8a7743-rst" (RZ/G1M)
+		  - "renesas,r8a7745-rst" (RZ/G1E)
+		  - "renesas,r8a7790-rst" (R-Car H2)
+		  - "renesas,r8a7791-rst" (R-Car M2-W)
+		  - "renesas,r8a7792-rst" (R-Car V2H
+		  - "renesas,r8a7793-rst" (R-Car M2-N)
+		  - "renesas,r8a7794-rst" (R-Car E2)
+  - reg: Address start and address range for the device.
+
+
+Example:
+
+	rst: reset-controller at e6160000 {
+		compatible = "renesas,r8a7743-rst";
+		reg = <0 0xe6160000 0 0x100>;
+	};

2.7.4

Initialize R-Car reset IP by calling rcar_rst_init.

---
 drivers/clk/shmobile/clk-rcar-gen2.c | 3 +++
 1 file changed, 3 insertions(+)

index 636070b..6ab0199 100644
@@ -19,6 +19,7 @@
 #include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/soc/renesas/rcar-rst.h>
 
 struct rcar_gen2_cpg {
 	struct clk_onecell_data data;

@@ -442,4 +443,6 @@ void __init rcar_gen2_clocks_init(u32 mode)
 	cpg_mode = mode;
 
 	of_clk_init(NULL);
+
+	rcar_rst_init();
 }

2.7.4

From: Lee Jones <[email protected]>

Critical clocks are those which must not be gated, else undefined or catastrophic failure would occur. Here we have chosen to ensure the prepare/enable counts are correctly incremented, so as not to confuse users with enabled clocks with no visible users.

---
 drivers/clk/clk.c            | 5 +++++
 include/linux/clk-provider.h | 1 +
 2 files changed, 6 insertions(+)

index 53c068f..c2718c8 100644
@@ -2469,6 +2469,11 @@ static int __clk_init(struct device *dev, struct clk *clk_user)
 	if (core->ops->init)
 		core->ops->init(core->hw);
 
+	if (core->flags & CLK_IS_CRITICAL) {
+		clk_core_prepare(core);
+		clk_core_enable(core);
+	}
+
 	kref_init(&core->ref);
 out:
 	clk_prepare_unlock();

index 7cd0171..b79d854 100644
@@ -31,6 +31,7 @@
 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
 #define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
+#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
 
 struct clk;
 struct clk_hw;

2.7.4

From: Lee Jones <[email protected]>

---
 drivers/clk/clk.c | 6 ++++++
 1 file changed, 6 insertions(+)

index c2718c8..a5b6a20 100644
@@ -575,6 +575,9 @@ static void clk_core_unprepare(struct clk_core *core)
 	if (WARN_ON(core->prepare_count == 0))
 		return;
 
+	if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
+		return;
+
 	if (--core->prepare_count > 0)
 		return;
 

@@ -680,6 +683,9 @@ static void clk_core_disable(struct clk_core *core)
 	if (WARN_ON(core->enable_count == 0))
 		return;
 
+	if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
+		return;
+
 	if (--core->enable_count > 0)
 		return;
 

2.7.4

From: Maxime Ripard <[email protected]>

The critical clock handling in __clk_core_init isn't taking the enable lock before calling clk_core_enable, which in turns triggers the warning in the lockdep_assert_held call in that function when lockep is enabled.

Add the calls to clk_enable_lock/unlock to make sure it doesn't happen.

---
 drivers/clk/clk.c | 5 +++++
 1 file changed, 5 insertions(+)

index a5b6a20..ef6b7891 100644
@@ -2476,8 +2476,13 @@ static int __clk_init(struct device *dev, struct clk *clk_user)
 		core->ops->init(core->hw);
 
 	if (core->flags & CLK_IS_CRITICAL) {
+		unsigned long flags;
+
 		clk_core_prepare(core);
+
+		flags = clk_enable_lock();
 		clk_core_enable(core);
+		clk_enable_unlock(flags);
 	}
 
 	kref_init(&core->ref);

2.7.4

From: Geert Uytterhoeven <[email protected]>

INTC-SYS is the module clock for the GIC. Accessing the GIC while it is disabled causes:

    Unhandled fault: asynchronous external abort (0x1211) at 0x00000000

Currently, the GIC-400 driver cannot enable its module clock for several reasons:
- It does not use a platform device, so Runtime PM is not an option,
- gic_of_init() runs before any clocks are registered, so it cannot enable the clock explicitly,
- gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE() doesn't support deferred probing.

Hence we have to keep on relying on the boot loader for enabling the module clock.

To prevent the module clock from being disabled when the CCF core thinks it is unused, and thus causing a system lock-up, add a check to the MSTP clock driver and enable CLK_IS_CRITICAL. This will make sure the module clock is never disabled.

This is a hard dependency for describing the INTC-SYS clock in DT on R-Mobile APE6 and R-Car Gen2.

(Added rwdt as critical clock)

---
 drivers/clk/shmobile/clk-mstp.c | 5 +++++
 1 file changed, 5 insertions(+)

index 3b09716..6c7c7ed 100644
@@ -144,6 +144,11 @@ cpg_mstp_clock_register(const char *name, const char *parent_name,
 	init.name = name;
 	init.ops = &cpg_mstp_clock_ops;
 	init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+	/* INTC-SYS is the module clock of the GIC, and must not be disabled */
+	if (!strcmp(name, "intc-sys") || !strcmp(name, "rwdt")) {
+		pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
+		init.flags |= CLK_IS_CRITICAL;
+	}
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 

2.7.4

This patch registers "rwdt" and "intc-sys" clocks by adding the necessary definitions to the mstp4_clks node. Please note that both "rwdt" and "intc-sys" are critical clocks.

---
 arch/arm/boot/dts/r8a7743.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

index d94fbce..551ce1c 100644
@@ -1289,10 +1289,13 @@
 				compatible = "renesas,r8a7743-mstp-clocks",
 					     "renesas,cpg-mstp-clocks";
 				reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-				clocks = <&cp_clk>;
+				clocks = <&rclk_clk>, <&cp_clk>, <&zs_clk>;
 				#clock-cells = <1>;
-				clock-indices = <R8A7743_CLK_IRQC>;
-				clock-output-names = "irqc";
+				clock-indices = <
+					R8A7743_CLK_RWDT R8A7743_CLK_IRQC
+					R8A7743_CLK_INTC_SYS
+				>;
+				clock-output-names = "rwdt", "irqc", "intc-sys";
 			};
 			mstp5_clks: mstp5_clks at e6150144 {
 				compatible = "renesas,r8a7743-mstp-clocks",

2.7.4

This patch registers "rwdt" and "intc-sys" clocks by adding the necessary definitions to the mstp4_clks node. Please note that both "rwdt" and "intc-sys" are critical clocks.

---
 arch/arm/boot/dts/r8a7745.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

index 46fb046..33236c0 100644
@@ -1365,12 +1365,13 @@
 				compatible = "renesas,r8a7745-mstp-clocks",
 					     "renesas,cpg-mstp-clocks";
 				reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-				clocks = <&cp_clk>;
+				clocks = <&rclk_clk>, <&cp_clk>, <&zs_clk>;
 				#clock-cells = <1>;
 				clock-indices = <
-					R8A7745_CLK_IRQC
+					R8A7745_CLK_RWDT R8A7745_CLK_IRQC
+					R8A7745_CLK_INTC_SYS
 				>;
-				clock-output-names = "irqc";
+				clock-output-names = "rwdt", "irqc", "intc-sys";
 			};
 			mstp5_clks: mstp5_clks at e6150144 {
 				compatible = "renesas,r8a7745-mstp-clocks",

2.7.4

From: Wolfram Sang <[email protected]>

Add support for watchdogs (RWDT and SWDT) found on RCar Gen3 based SoCs from Renesas.

(reworked dt-bindings to refer to R-Car Gen2 and RZ/G1 only. replaced ARCH_RENESAS with ARCH_SHMOBILE in Kconfig. changes to the driver:
* replaced "renesas,rcar-gen3-wdt" with "renesas,rcar-gen2-wdt"
* added rwdt_set_timeout
* modified rwdt_ping and rwdt_start to leverage rwdt_set_timeout)

---
 .../devicetree/bindings/watchdog/renesas-wdt.txt   |  33 ++++
 drivers/watchdog/Kconfig                           |   8 +
 drivers/watchdog/Makefile                          |   1 +
 drivers/watchdog/renesas_wdt.c                     | 215 +++++++++++++++++++++
 4 files changed, 257 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
 create mode 100644 drivers/watchdog/renesas_wdt.c

new file mode 100644
index 0000000..25b108e
@@ -0,0 +1,33 @@
+Renesas Watchdog Timer (WDT) Controller
+
+Required properties:
+ - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
+		fallback compatible string when compatible with the generic
+		version.
+	       Examples with soctypes are:
+		 - "renesas,r8a7743-wdt" (RZ/G1M)
+		 - "renesas,r8a7745-wdt" (RZ/G1E)
+		The generic compatible string must be:
+		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G
+
+  When compatible with the generic version, nodes must list the SoC-specific
+  version corresponding to the platform first, followed by the generic
+  version.
+
+- reg : Should contain WDT registers location and length
+- clocks : the clock feeding the watchdog timer.
+
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+- power-domains : the power domain the WDT belongs to
+
+Examples:
+
+	rwdt: watchdog at e6020000 {
+		compatible = "renesas,r8a7743-wdt",
+			     "renesas,rcar-gen2-wdt";
+		reg = <0 0xe6020000 0 0x0c>;
+		clocks = <&mstp4_clks R8A7743_CLK_RWDT>;
+		power-domains = <&cpg_clocks>;
+		timeout-sec = <60>;
+	};

index 88743cd..b449065 100644
@@ -589,6 +589,14 @@ config LPC18XX_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called lpc18xx_wdt.
 
+config RENESAS_WDT
+	tristate "Renesas WDT Watchdog"
+	depends on ARCH_SHMOBILE || COMPILE_TEST
+	select WATCHDOG_CORE
+	help
+	  This driver adds watchdog support for the integrated watchdogs in the
+	  Renesas R-Car and other SH-Mobile SoCs (usually named RWDT or SWDT).
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT

index 53d4827..e1c5d85 100644
@@ -69,6 +69,7 @@ obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
 obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
 obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
 obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
+obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o

2.7.4

Well, gen2 support was added upstream by commit 3fe95e6c68e6258410e85488af9e1b1ff545b831, so that should be mentioned here too. It also blacklisted some early gen2 chips; shouldn't that code be included in this backport?

[...]

You explain what you changed, but it's more helpful to explain why. If I'm reading correctly, the set_timeout operation for watchdog drivers is now optional, but was required in 4.4. Could you put that in the commit message?

Ben.

Ben Hutchings, Software Developer                ?        Codethink Ltd
https://www.codethink.co.uk/                 Dale House, 35 Dale Street
                                     Manchester, M1 2HF, United Kingdom

Hello Ben,

Thank you for your feedback.

Will do

There is more work to do to backport that neatly, and also the goal is to support r8a774[35] (which is covered by this commit). On top of that, the blacklisted chips are not found in real products, only in early prototypes of development boards. The plan is to look into this iff interests arises.

I will put the reason in the commit message of V2.

Thanks,
Fab

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[...]

[...]

OK, that makes sense.

Ben.

Ben Hutchings, Software Developer                ?        Codethink Ltd
https://www.codethink.co.uk/                 Dale House, 35 Dale Street
                                     Manchester, M1 2HF, United Kingdom

From: Wolfram Sang <[email protected]>

Add support for watchdogs (RWDT and SWDT) found on RCar Gen3 based SoCs from Renesas.

and squashed commit 3fe95e6c68e6258410e85488af9e1b1ff545b831 into it) (reworked dt-bindings to refer to R-Car Gen2 and RZ/G1 only. replaced ARCH_RENESAS with ARCH_SHMOBILE in Kconfig. changes to the driver:
* removed "renesas,rcar-gen3-wdt"
* removed blacklisting logic
* implemented set_timeout (via rwdt_set_timeout) as required by the 4.4 kernel
* modified rwdt_ping and rwdt_start to leverage rwdt_set_timeout)

---
v1->v2:
* added reference to the upstream commit for gen2 support to the changelog
* added some explanation for set_timeout to the changelog

 .../devicetree/bindings/watchdog/renesas-wdt.txt   |  33 ++++
 drivers/watchdog/Kconfig                           |   8 +
 drivers/watchdog/Makefile                          |   1 +
 drivers/watchdog/renesas_wdt.c                     | 215 +++++++++++++++++++++
 4 files changed, 257 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
 create mode 100644 drivers/watchdog/renesas_wdt.c

new file mode 100644
index 0000000..25b108e
@@ -0,0 +1,33 @@
+Renesas Watchdog Timer (WDT) Controller
+
+Required properties:
+ - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
+		fallback compatible string when compatible with the generic
+		version.
+	       Examples with soctypes are:
+		 - "renesas,r8a7743-wdt" (RZ/G1M)
+		 - "renesas,r8a7745-wdt" (RZ/G1E)
+		The generic compatible string must be:
+		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G
+
+  When compatible with the generic version, nodes must list the SoC-specific
+  version corresponding to the platform first, followed by the generic
+  version.
+
+- reg : Should contain WDT registers location and length
+- clocks : the clock feeding the watchdog timer.
+
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+- power-domains : the power domain the WDT belongs to
+
+Examples:
+
+	rwdt: watchdog at e6020000 {
+		compatible = "renesas,r8a7743-wdt",
+			     "renesas,rcar-gen2-wdt";
+		reg = <0 0xe6020000 0 0x0c>;
+		clocks = <&mstp4_clks R8A7743_CLK_RWDT>;
+		power-domains = <&cpg_clocks>;
+		timeout-sec = <60>;
+	};

index 88743cd..b449065 100644
@@ -589,6 +589,14 @@ config LPC18XX_WATCHDOG
 	  To compile this driver as a module, choose M here: the
 	  module will be called lpc18xx_wdt.
 
+config RENESAS_WDT
+	tristate "Renesas WDT Watchdog"
+	depends on ARCH_SHMOBILE || COMPILE_TEST
+	select WATCHDOG_CORE
+	help
+	  This driver adds watchdog support for the integrated watchdogs in the
+	  Renesas R-Car and other SH-Mobile SoCs (usually named RWDT or SWDT).
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT

index 53d4827..e1c5d85 100644
@@ -69,6 +69,7 @@ obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
 obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
 obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
 obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
+obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o

2.7.4

From: Wolfram Sang <[email protected]>

Because the smallest clock divider we can select is 1, 'clks_per_sec' must be the same type as 'rate'.

---
 drivers/watchdog/renesas_wdt.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

index ab3e9b0..27c090e 100644
@@ -37,7 +37,7 @@ struct rwdt_priv {
 	void __iomem *base;
 	struct watchdog_device wdev;
 	struct clk *clk;
-	unsigned int clks_per_sec;
+	unsigned long clks_per_sec;
 	u8 cks;
 };
 

@@ -119,8 +119,7 @@ static int rwdt_probe(struct platform_device *pdev)
 {
 	struct rwdt_priv *priv;
 	struct resource *res;
-	unsigned long rate;
-	unsigned int clks_per_sec;
+	unsigned long rate, clks_per_sec;
 	int ret, i;
 
 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);

2.7.4

From: Wolfram Sang <[email protected]>

When checking the clock rate, ensure also that counting all 16 bits takes at least one second to match the granularity of the framework.

---
 drivers/watchdog/renesas_wdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 27c090e..9d68eb0 100644
@@ -141,14 +141,14 @@ static int rwdt_probe(struct platform_device *pdev)
 
 	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
 		clks_per_sec = DIV_ROUND_UP(rate, clk_divs[i]);
-		if (clks_per_sec) {
+		if (clks_per_sec && clks_per_sec < 65536) {
 			priv->clks_per_sec = clks_per_sec;
 			priv->cks = i;
 			break;
 		}
 	}
 
-	if (!clks_per_sec) {
+	if (i < 0) {
 		dev_err(&pdev->dev, "Can't find suitable clock divider\n");
 		return -ERANGE;
 	}

2.7.4

From: Wolfram Sang <[email protected]>

We should never return more time left than there actually is. So, switch to a plain divider instead of DIV_ROUND_CLOSEST.

---
 drivers/watchdog/renesas_wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 9d68eb0..64f68d1 100644
@@ -98,7 +98,7 @@ static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 	u16 val = readw_relaxed(priv->base + RWTCNT);
 
-	return DIV_ROUND_CLOSEST(65536 - val, priv->clks_per_sec);
+	return (65536 - val) / priv->clks_per_sec;
 }
 
 static const struct watchdog_info rwdt_ident = {

2.7.4

From: Wolfram Sang <[email protected]>

The error margin of the clks_per_second variable was too large and caused offsets when used with clock frequencies which left a remainder after applying the dividers. Now we always calculate directly using the clock rate and the divider using some helper macros. That also means that DIV_ROUND_UP moves from probe to the multiplication macro. In probe, we don't need to ensure anymore that 'clks_per_sec' would go too fast but rather ensure that the lower limit is really at least 1 to certainly get a full cycle.

---
 drivers/watchdog/renesas_wdt.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

index 64f68d1..454a2fc 100644
@@ -26,6 +26,17 @@
 
 #define RWDT_DEFAULT_TIMEOUT 60U
 
+/*
+ * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
+ * divider (10 bits). d is only a factor to fully utilize the WDT counter and
+ * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
+ */
+#define MUL_BY_CLKS_PER_SEC(p, d) \
+	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
+
+/* d is 16 bit, clk_divs 10 bit -> no 32 bit overflow */
+#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
+
 static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024 };
 
 static bool nowayout = WATCHDOG_NOWAYOUT;

@@ -37,7 +48,7 @@ struct rwdt_priv {
 	void __iomem *base;
 	struct watchdog_device wdev;
 	struct clk *clk;
-	unsigned long clks_per_sec;
+	unsigned long clk_rate;
 	u8 cks;
 };
 

@@ -56,7 +67,7 @@ static int rwdt_set_timeout(struct watchdog_device *wdev, unsigned int seconds)
 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 
 	wdev->timeout = seconds;
-	rwdt_write(priv, 65536 - wdev->timeout * priv->clks_per_sec, RWTCNT);
+	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
 
 	return 0;
 }

@@ -98,7 +109,7 @@ static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 	u16 val = readw_relaxed(priv->base + RWTCNT);
 
-	return (65536 - val) / priv->clks_per_sec;
+	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
 }
 
 static const struct watchdog_info rwdt_ident = {

@@ -119,7 +130,7 @@ static int rwdt_probe(struct platform_device *pdev)
 {
 	struct rwdt_priv *priv;
 	struct resource *res;
-	unsigned long rate, clks_per_sec;
+	unsigned long clks_per_sec;
 	int ret, i;
 
 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);

@@ -135,14 +146,13 @@ static int rwdt_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->clk))
 		return PTR_ERR(priv->clk);
 
-	rate = clk_get_rate(priv->clk);
-	if (!rate)
+	priv->clk_rate = clk_get_rate(priv->clk);
+	if (!priv->clk_rate)
 		return -ENOENT;
 
 	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
-		clks_per_sec = DIV_ROUND_UP(rate, clk_divs[i]);
+		clks_per_sec = priv->clk_rate / clk_divs[i];
 		if (clks_per_sec && clks_per_sec < 65536) {
-			priv->clks_per_sec = clks_per_sec;
 			priv->cks = i;
 			break;
 		}

@@ -160,7 +170,7 @@ static int rwdt_probe(struct platform_device *pdev)
 	priv->wdev.ops = &rwdt_ops,
 	priv->wdev.parent = &pdev->dev;
 	priv->wdev.min_timeout = 1;
-	priv->wdev.max_timeout = 65536 / clks_per_sec;
+	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
 	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
 
 	platform_set_drvdata(pdev, priv);

2.7.4

From: Wolfram Sang <[email protected]>

If we set RWTCSRB to 0, we can gain 4096 as another divider value. This is supported by all R-Car Gen2 and Gen3 devices which we aim to support.

---
 drivers/watchdog/renesas_wdt.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

index 454a2fc..1891a0e 100644
@@ -23,21 +23,22 @@
 #define RWTCSRA_WOVF	BIT(4)
 #define RWTCSRA_WRFLG	BIT(5)
 #define RWTCSRA_TME	BIT(7)
+#define RWTCSRB		8
 
 #define RWDT_DEFAULT_TIMEOUT 60U
 
 /*
  * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
- * divider (10 bits). d is only a factor to fully utilize the WDT counter and
+ * divider (12 bits). d is only a factor to fully utilize the WDT counter and
  * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
  */
 #define MUL_BY_CLKS_PER_SEC(p, d) \
 	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
 
-/* d is 16 bit, clk_divs 10 bit -> no 32 bit overflow */
+/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
 
-static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024 };
+static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
 
 static bool nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, bool, 0);

@@ -83,6 +84,7 @@ static int rwdt_start(struct watchdog_device *wdev)
 
 	clk_prepare_enable(priv->clk);
 
+	rwdt_write(priv, 0, RWTCSRB);
 	rwdt_write(priv, priv->cks, RWTCSRA);
 	rwdt_set_timeout(wdev, wdev->timeout);
 

2.7.4

From: Wolfram Sang <[email protected]>

On Renesas R-Car archs, RuntimePM does all the clock handling. So, use it consistently to enable/disable the clocks. Also make sure that clocks are really enabled around clk_get_rate(). clk_summary looks proper now:

clock enable_cnt prepare_cnt rate ...
Before this commit:

At boot: rwdt 1 1 32768 0 0
WDT running: rwdt 2 2 32768 0 0

After this commit:

At boot: rwdt 0 1 32768 0 0
WDT running rwdt 1 1 32768 0 0

---
 drivers/watchdog/renesas_wdt.c | 33 +++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

index 1891a0e..834cff0 100644
@@ -82,7 +82,7 @@ static int rwdt_start(struct watchdog_device *wdev)
 {
 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 
-	clk_prepare_enable(priv->clk);
+	pm_runtime_get_sync(wdev->parent);
 
 	rwdt_write(priv, 0, RWTCSRB);
 	rwdt_write(priv, priv->cks, RWTCSRA);

@@ -101,7 +101,7 @@ static int rwdt_stop(struct watchdog_device *wdev)
 	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 
 	rwdt_write(priv, priv->cks, RWTCSRA);
-	clk_disable_unprepare(priv->clk);
+	pm_runtime_put(wdev->parent);
 
 	return 0;
 }

@@ -148,9 +148,16 @@ static int rwdt_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->clk))
 		return PTR_ERR(priv->clk);
 
+	pm_runtime_enable(&pdev->dev);
+
+	pm_runtime_get_sync(&pdev->dev);
 	priv->clk_rate = clk_get_rate(priv->clk);
-	if (!priv->clk_rate)
-		return -ENOENT;
+	pm_runtime_put(&pdev->dev);
+
+	if (!priv->clk_rate) {
+		ret = -ENOENT;
+		goto out_pm_disable;
+	}
 
 	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
 		clks_per_sec = priv->clk_rate / clk_divs[i];

@@ -162,12 +169,10 @@ static int rwdt_probe(struct platform_device *pdev)
 
 	if (i < 0) {
 		dev_err(&pdev->dev, "Can't find suitable clock divider\n");
-		return -ERANGE;
+		ret = -ERANGE;
+		goto out_pm_disable;
 	}
 
-	pm_runtime_enable(&pdev->dev);
-	pm_runtime_get_sync(&pdev->dev);
-
 	priv->wdev.info = &rwdt_ident,
 	priv->wdev.ops = &rwdt_ops,
 	priv->wdev.parent = &pdev->dev;

@@ -185,13 +190,14 @@ static int rwdt_probe(struct platform_device *pdev)
 		dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
 
 	ret = watchdog_register_device(&priv->wdev);
-	if (ret < 0) {
-		pm_runtime_put(&pdev->dev);
-		pm_runtime_disable(&pdev->dev);
-		return ret;
-	}
+	if (ret < 0)
+		goto out_pm_disable;
 
 	return 0;
+
+ out_pm_disable:
+	pm_runtime_disable(&pdev->dev);
+	return ret;
 }
 
 static int rwdt_remove(struct platform_device *pdev)

@@ -199,7 +205,6 @@ static int rwdt_remove(struct platform_device *pdev)
 	struct rwdt_priv *priv = platform_get_drvdata(pdev);
 
 	watchdog_unregister_device(&priv->wdev);
-	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 
 	return 0;

2.7.4

From: Wolfram Sang <[email protected]>

It is not needed outside probe() anymore.

---
 drivers/watchdog/renesas_wdt.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

index 834cff0..0e4a82e 100644
@@ -48,7 +48,6 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
 struct rwdt_priv {
 	void __iomem *base;
 	struct watchdog_device wdev;
-	struct clk *clk;
 	unsigned long clk_rate;
 	u8 cks;
 };

@@ -132,6 +131,7 @@ static int rwdt_probe(struct platform_device *pdev)
 {
 	struct rwdt_priv *priv;
 	struct resource *res;
+	struct clk *clk;
 	unsigned long clks_per_sec;
 	int ret, i;
 

@@ -144,14 +144,14 @@ static int rwdt_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->base))
 		return PTR_ERR(priv->base);
 
-	priv->clk = devm_clk_get(&pdev->dev, NULL);
-	if (IS_ERR(priv->clk))
-		return PTR_ERR(priv->clk);
+	clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
 
 	pm_runtime_enable(&pdev->dev);
 
 	pm_runtime_get_sync(&pdev->dev);
-	priv->clk_rate = clk_get_rate(priv->clk);
+	priv->clk_rate = clk_get_rate(clk);
 	pm_runtime_put(&pdev->dev);
 
 	if (!priv->clk_rate) {

2.7.4

From: Wolfram Sang <[email protected]>

---
 drivers/watchdog/renesas_wdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 0e4a82e..be1e39b 100644
@@ -1,8 +1,8 @@
 /*
  * Watchdog driver for Renesas WDT watchdog
  *
- * Copyright (C) 2015-16 Wolfram Sang, Sang Engineering <[email protected]>
- * Copyright (C) 2015-16 Renesas Electronics Corporation
+ * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <[email protected]>
+ * Copyright (C) 2015-17 Renesas Electronics Corporation
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as published by

2.7.4

On R-Car Gen2 and RZ/G1 the watchdog IP clock needs to be always ON, on R-Car Gen3 we power the IP down during suspend.

This commit adds suspend/resume support, so that the watchdog counting "pauses" during suspend on all of the SoCs compatible with this driver and on those we are now adding support for (R-Car Gen2 and RZ/G1).

---
 drivers/watchdog/renesas_wdt.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

index be1e39b..87f3e57 100644
@@ -49,6 +49,7 @@ struct rwdt_priv {
 	void __iomem *base;
 	struct watchdog_device wdev;
 	unsigned long clk_rate;
+	u16 time_left;
 	u8 cks;
 };
 

@@ -210,6 +211,30 @@ static int rwdt_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static int __maybe_unused rwdt_suspend(struct device *dev)
+{
+	struct rwdt_priv *priv = dev_get_drvdata(dev);
+
+	if (watchdog_active(&priv->wdev)) {
+		priv->time_left = readw(priv->base + RWTCNT);
+		rwdt_stop(&priv->wdev);
+	}
+	return 0;
+}
+
+static int __maybe_unused rwdt_resume(struct device *dev)
+{
+	struct rwdt_priv *priv = dev_get_drvdata(dev);
+
+	if (watchdog_active(&priv->wdev)) {
+		rwdt_start(&priv->wdev);
+		rwdt_write(priv, priv->time_left, RWTCNT);
+	}
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
+
 static const struct of_device_id rwdt_ids[] = {
 	{ .compatible = "renesas,rcar-gen2-wdt", },
 	{ /* sentinel */ }

@@ -220,6 +245,7 @@ static struct platform_driver rwdt_driver = {
 	.driver = {
 		.name = "renesas_wdt",
 		.of_match_table = rwdt_ids,
+		.pm = &rwdt_pm_ops,
 	},
 	.probe = rwdt_probe,
 	.remove = rwdt_remove,

2.7.4

On iWave's boards iwg20d and iwg22d the only way to reboot the system is by means of the watchdog.
This patch adds a restart handler to rwdt_ops, and also makes sure we keep its priority to the lowest level, in order to not override other more effective handlers.

(changed restart handler implementation as .restart is not available from struct watchdog_ops)

---
 drivers/watchdog/renesas_wdt.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

index 87f3e57..88b9c7d 100644
@@ -17,6 +17,8 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/watchdog.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
 
 #define RWTCNT		0
 #define RWTCSRA		4

@@ -51,6 +53,7 @@ struct rwdt_priv {
 	unsigned long clk_rate;
 	u16 time_left;
 	u8 cks;
+	struct notifier_block restart_handler;
 };
 
 static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)

@@ -114,6 +117,18 @@ static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
 	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
 }
 
+static int rwdt_restart(struct notifier_block *this, unsigned long mode,
+			void *cmd)
+{
+	struct rwdt_priv *priv = container_of(this, struct rwdt_priv,
+					      restart_handler);
+
+	rwdt_start(&priv->wdev);
+	rwdt_write(priv, 0xffff, RWTCNT);
+
+	return NOTIFY_DONE;
+}
+
 static const struct watchdog_info rwdt_ident = {
 	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
 	.identity = "Renesas WDT Watchdog",

@@ -194,6 +209,15 @@ static int rwdt_probe(struct platform_device *pdev)
 	if (ret < 0)
 		goto out_pm_disable;
 
+	priv->restart_handler.notifier_call = rwdt_restart;
+	priv->restart_handler.priority = 0;
+	ret = register_restart_handler(&priv->restart_handler);
+	if (ret) {
+		dev_err(&pdev->dev, "can't register restart handler (err=%d)\n",
+			ret);
+		priv->restart_handler.notifier_call = NULL;
+	}
+
 	return 0;
 
  out_pm_disable:

@@ -205,6 +229,8 @@ static int rwdt_remove(struct platform_device *pdev)
 {
 	struct rwdt_priv *priv = platform_get_drvdata(pdev);
 
+	if (priv->restart_handler.notifier_call);
+		unregister_restart_handler(&priv->restart_handler);
 	watchdog_unregister_device(&priv->wdev);
 	pm_runtime_disable(&pdev->dev);
 

2.7.4

[...]

Ben Hutchings, Software Developer                ?        Codethink Ltd
https://www.codethink.co.uk/                 Dale House, 35 Dale Street
                                     Manchester, M1 2HF, United Kingdom

Hello Ben,

Thank you for your feedback.

Good catch!

Yes I am unfortunately

Thank you!

Fab

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

From: Veeraiyan Chidambaram <[email protected]>

This patch adds the WDIOF_CARDRESET support for the Renesas platform watchdog, to know if the board reboot is due to a watchdog reset.

This is done via the WOVF bit (bit 4) of the RWTCSRA register, which indicates if RWTCNT overflowed, triggering the reset in last boot.

[takeshi.kihara.df: changed to read the RWTCSRA register while clock is
enabled]

---
 drivers/watchdog/renesas_wdt.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

index 88b9c7d..e334a83 100644
@@ -130,7 +130,8 @@ static int rwdt_restart(struct notifier_block *this, unsigned long mode,
 }
 
 static const struct watchdog_info rwdt_ident = {
-	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
+	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
+		WDIOF_CARDRESET,
 	.identity = "Renesas WDT Watchdog",
 };
 

@@ -165,9 +166,10 @@ static int rwdt_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 
 	pm_runtime_enable(&pdev->dev);
-
 	pm_runtime_get_sync(&pdev->dev);
 	priv->clk_rate = clk_get_rate(clk);
+	priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
+				RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
 	pm_runtime_put(&pdev->dev);
 
 	if (!priv->clk_rate) {

2.7.4

From: Geert Uytterhoeven <[email protected]>

---
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +++++++++++++++++++++++++----------
 1 file changed, 29 insertions(+), 11 deletions(-)

index f1bee67..cb7e764 100644
@@ -20,15 +20,31 @@
 
 /* RST */
 #define RST		0xe6160000
-#define CA15BAR		0x0020
-#define CA7BAR		0x0030
-#define CA15RESCNT	0x0040
-#define CA7RESCNT	0x0044
+
+#define CA15BAR		0x0020		/* CA15 Boot Address Register */
+#define CA7BAR		0x0030		/* CA7 Boot Address Register */
+#define CA15RESCNT	0x0040		/* CA15 Reset Control Register */
+#define CA7RESCNT	0x0044		/* CA7 Reset Control Register */
+
+/* SYS Boot Address Register */
+#define SBAR_BAREN	BIT(4)		/* SBAR is valid */
+
+/* Reset Control Registers */
+#define CA15RESCNT_CODE	0xa5a50000
+#define CA15RESCNT_CPUS	0xf		/* CPU0-3 */
+#define CA7RESCNT_CODE	0x5a5a0000
+#define CA7RESCNT_CPUS	0xf		/* CPU0-3 */
+
 
 /* On-chip RAM */
 #define MERAM		0xe8080000
 #define RAM		0xe6300000
 
+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+	return (addr >> 8) & 0xfffffc00;
+}
+
 /* SYSC */
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10

@@ -97,22 +113,24 @@ void __init rcar_gen2_pm_init(void)
 
 	/* setup reset vectors */
 	p = ioremap_nocache(RST, 0x63);
-	bar = (boot_vector_addr >> 8) & 0xfffffc00;
+	bar = phys_to_sbar(boot_vector_addr);
 	if (has_a15) {
 		writel_relaxed(bar, p + CA15BAR);
-		writel_relaxed(bar | 0x10, p + CA15BAR);
+		writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
 
 		/* de-assert reset for CA15 CPUs */
-		writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
-				0xa5a50000, p + CA15RESCNT);
+		writel_relaxed((readl_relaxed(p + CA15RESCNT) &
+				~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
+			       p + CA15RESCNT);
 	}
 	if (has_a7) {
 		writel_relaxed(bar, p + CA7BAR);
-		writel_relaxed(bar | 0x10, p + CA7BAR);
+		writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
 
 		/* de-assert reset for CA7 CPUs */
-		writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
-				0x5a5a0000, p + CA7RESCNT);
+		writel_relaxed((readl_relaxed(p + CA7RESCNT) &
+				~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
+			       p + CA7RESCNT);
 	}
 	iounmap(p);
 

2.7.4

From: Geert Uytterhoeven <[email protected]>

Currently the different SoCs in the R-Car Gen2 family use different types of on-chip RAM for the jump stub:
- R-Car H2 uses Media RAM,
- R-Car M2-W uses another type of optional On-chip RAM, as it doesn't have Media RAM,
- R-Car M2-N uses Inter Connect RAM in Magnus Damm's "ARM: shmobile:
r8a7793 boot address update".

As all R-Car Gen2 SoCs have 4 KiB of Inter Connect RAM, consolidate the code by always using that.

(do not init boot_vector_addr for r8a7743 and r8a7745)

---
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

index cb7e764..6556134 100644
@@ -37,8 +37,7 @@
 
 
 /* On-chip RAM */
-#define MERAM		0xe8080000
-#define RAM		0xe6300000
+#define ICRAM1		0xe63c0000	/* Inter Connect RAM1 (4 KiB) */
 
 static inline u32 phys_to_sbar(phys_addr_t addr)
 {

@@ -74,7 +73,7 @@ void __init rcar_gen2_pm_init(void)
 	struct device_node *np, *cpus;
 	bool has_a7 = false;
 	bool has_a15 = false;
-	phys_addr_t boot_vector_addr = 0;
+	phys_addr_t boot_vector_addr = ICRAM1;
 	u32 syscier = 0;
 
 	if (once++)

@@ -91,20 +90,14 @@ void __init rcar_gen2_pm_init(void)
 			has_a7 = true;
 	}
 
-	if (of_machine_is_compatible("renesas,r8a7790")) {
-		boot_vector_addr = MERAM;
+	if (of_machine_is_compatible("renesas,r8a7790"))
 		syscier = 0x013111ef;
-
-	} else if (of_machine_is_compatible("renesas,r8a7791")) {
-		boot_vector_addr = RAM;
+	else if (of_machine_is_compatible("renesas,r8a7791"))
 		syscier = 0x00111003;
-	} else if (of_machine_is_compatible("renesas,r8a7743")) {
-		boot_vector_addr = RAM;
+	else if (of_machine_is_compatible("renesas,r8a7743"))
 		syscier = 0x00101003;
-	} else if (of_machine_is_compatible("renesas,r8a7745")) {
-		boot_vector_addr = RAM;
+	else if (of_machine_is_compatible("renesas,r8a7745"))
 		syscier = 0x00300060;
-	}
 
 	/* RAM for jump stub, because BAR requires 256KB aligned address */
 	p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);

2.7.4

From: Geert Uytterhoeven <[email protected]>

Add support for obtaining from DT the SRAM region to store the jump stub for CPU core bringup, according to the renesas,smp-sram DT bindings.

If no region is specified in DT, the code falls back to hardcoded ICRAM1 as before, to maintain backwards compatibility.

---
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

index 6556134..7a34ec9 100644
@@ -11,7 +11,9 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/smp.h>
 #include <asm/io.h>
 #include "common.h"

@@ -73,8 +75,9 @@ void __init rcar_gen2_pm_init(void)
 	struct device_node *np, *cpus;
 	bool has_a7 = false;
 	bool has_a15 = false;
-	phys_addr_t boot_vector_addr = ICRAM1;
+	struct resource res;
 	u32 syscier = 0;
+	int error;
 
 	if (once++)
 		return;

@@ -99,14 +102,38 @@ void __init rcar_gen2_pm_init(void)
 	else if (of_machine_is_compatible("renesas,r8a7745"))
 		syscier = 0x00300060;
 
+	np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
+	if (!np) {
+		/* No smp-sram in DT, fall back to hardcoded address */
+		res = (struct resource)DEFINE_RES_MEM(ICRAM1,
+						      shmobile_boot_size);
+		goto map;
+	}
+
+	error = of_address_to_resource(np, 0, &res);
+	if (error) {
+		pr_err("Failed to get smp-sram address: %d\n", error);
+		return;
+	}
+
+map:
 	/* RAM for jump stub, because BAR requires 256KB aligned address */
-	p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);
+	if (res.start & (256 * 1024 - 1) ||
+	    resource_size(&res) < shmobile_boot_size) {
+		pr_err("Invalid smp-sram region\n");
+		return;
+	}
+
+	p = ioremap(res.start, resource_size(&res));
+	if (!p)
+		return;
+
 	memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
 	iounmap(p);
 
 	/* setup reset vectors */
 	p = ioremap_nocache(RST, 0x63);
-	bar = phys_to_sbar(boot_vector_addr);
+	bar = phys_to_sbar(res.start);
 	if (has_a15) {
 		writel_relaxed(bar, p + CA15BAR);
 		writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);

2.7.4

This patch adds watchdog support by installing shmobile_boot_vector_gen2 to ICRAM1 when enough memory is available, in which case we also keep a copy of MPIDR to complete the reset vector logic.

---
 arch/arm/mach-shmobile/platsmp-apmu.c |  1 +
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 15 ++++++++++++---
 2 files changed, 13 insertions(+), 3 deletions(-)

index 66fe008..4153d5a 100644
@@ -186,6 +186,7 @@ static void __init shmobile_smp_apmu_setup_boot(void)
 {
 	/* install boot code shared by all CPUs */
 	shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+	shmobile_boot_fn_gen2 = shmobile_boot_fn;
 }
 
 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,

index 7a34ec9..0054561 100644
@@ -16,6 +16,7 @@
 #include <linux/of_address.h>
 #include <linux/smp.h>
 #include <asm/io.h>
+#include <asm/cputype.h>
 #include "common.h"
 #include "pm-rcar.h"
 #include "rcar-gen2.h"

@@ -37,7 +38,6 @@
 #define CA7RESCNT_CODE	0x5a5a0000
 #define CA7RESCNT_CPUS	0xf		/* CPU0-3 */
 
-
 /* On-chip RAM */
 #define ICRAM1		0xe63c0000	/* Inter Connect RAM1 (4 KiB) */
 

@@ -127,8 +127,17 @@ map:
 	p = ioremap(res.start, resource_size(&res));
 	if (!p)
 		return;
-
-	memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+	/*
+	 * install the reset vector, use the largest version if we have enough
+	 * memory available
+	 */
+	if (resource_size(&res) >= shmobile_boot_size_gen2) {
+		shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
+		memcpy_toio(p, shmobile_boot_vector_gen2,
+			    shmobile_boot_size_gen2);
+	} else {
+		memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+	}
 	iounmap(p);
 
 	/* setup reset vectors */

2.7.4

From: Geert Uytterhoeven <[email protected]>

RZ/G1M has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB).

(sorted icram nodes)

---
 arch/arm/boot/dts/r8a7743.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

index 551ce1c..c138027 100644
@@ -268,6 +268,21 @@
 			};
 		};
 
+		icram0:	sram at e63a0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63a0000 0 0x12000>;
+		};
+
+		icram1:	sram at e63c0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63c0000 0 0x1000>;
+		};
+
+		icram2:	sram at e6300000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe6300000 0 0x40000>;
+		};
+
 		timer {
 			compatible = "arm,armv7-timer";
 			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

2.7.4

From: Geert Uytterhoeven <[email protected]>

Reserve SRAM for the jump stub for CPU core bringup.

---
 arch/arm/boot/dts/r8a7743.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

index c138027..675c7b3 100644
@@ -276,6 +276,14 @@
 		icram1:	sram at e63c0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63c0000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63c0000 0x1000>;
+
+			smp-sram at 0 {
+				compatible = "renesas,smp-sram";
+				reg = <0 0x10>;
+			};
 		};
 
 		icram2:	sram at e6300000 {

2.7.4

This patch adjusts the definition of the SMP routine size according to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"

---
 arch/arm/boot/dts/r8a7743.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 675c7b3..bd0c8b2 100644
@@ -282,7 +282,7 @@
 
 			smp-sram at 0 {
 				compatible = "renesas,smp-sram";
-				reg = <0 0x10>;
+				reg = <0 0x100>;
 			};
 		};
 

2.7.4

From: Geert Uytterhoeven <[email protected]>

RZ/G1E has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB).

---
 arch/arm/boot/dts/r8a7745.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

index 33236c0..0afd5f0 100644
@@ -1022,6 +1022,21 @@
 			status = "disabled";
 		};
 
+		icram2:	sram at e6300000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe6300000 0 0x40000>;
+		};
+
+		icram0:	sram at e63a0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63a0000 0 0x12000>;
+		};
+
+		icram1:	sram at e63c0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63c0000 0 0x1000>;
+		};
+
 		ether: ethernet at ee700000 {
 			compatible = "renesas,ether-r8a7745";
 			reg = <0 0xee700000 0 0x400>;

2.7.4

From: Geert Uytterhoeven <[email protected]>

Reserve SRAM for the jump stub for CPU core bringup.

---
 arch/arm/boot/dts/r8a7745.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

index 0afd5f0..25ce4cd 100644
@@ -1035,6 +1035,14 @@
 		icram1:	sram at e63c0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63c0000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63c0000 0x1000>;
+
+			smp-sram at 0 {
+				compatible = "renesas,smp-sram";
+				reg = <0 0x10>;
+			};
 		};
 
 		ether: ethernet at ee700000 {

2.7.4

This patch adjusts the definition of the SMP routine size according to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"

---
 arch/arm/boot/dts/r8a7745.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 25ce4cd..2e79205 100644
@@ -1041,7 +1041,7 @@
 
 			smp-sram at 0 {
 				compatible = "renesas,smp-sram";
-				reg = <0 0x10>;
+				reg = <0 0x100>;
 			};
 		};
 

2.7.4

From: Sergei Shtylyov <[email protected]>

The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions.

Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.

(cherry-picked again only to get rst node)

---
 arch/arm/boot/dts/r8a7743.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index bd0c8b2..2931a02 100644
@@ -90,6 +90,11 @@
 			cpus = <&cpu0 &cpu1>;
 		};
 
+		rst: reset-controller at e6160000 {
+			compatible = "renesas,r8a7743-rst";
+			reg = <0 0xe6160000 0 0x100>;
+		};
+
 		gic: interrupt-controller at f1001000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;

2.7.4

From: Sergei Shtylyov <[email protected]>

The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions.

Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.

(cherry picked again only to get rst node)

---
 arch/arm/boot/dts/r8a7745.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 2e79205..f19aed2 100644
@@ -214,6 +214,11 @@
 			cpus = <&cpu0 &cpu1>;
 		};
 
+		rst: reset-controller at e6160000 {
+			compatible = "renesas,r8a7745-rst";
+			reg = <0 0xe6160000 0 0x100>;
+		};
+
 		irqc: interrupt-controller at e61c0000 {
 			compatible = "renesas,irqc-r8a7745", "renesas,irqc";
 			#interrupt-cells = <2>;

2.7.4

This patch adds watchdog support to the r8a7743 SoC dtsi.

(move node to better location to allow for better sorting. modified clocks and power-domains properties. removed resets property)

---
 arch/arm/boot/dts/r8a7743.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

index 2931a02..bb507a1 100644
@@ -95,6 +95,15 @@
 			reg = <0 0xe6160000 0 0x100>;
 		};
 
+		rwdt: watchdog at e6020000 {
+			compatible = "renesas,r8a7743-wdt",
+				     "renesas,rcar-gen2-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			clocks = <&mstp4_clks R8A7743_CLK_RWDT>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller at f1001000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;

2.7.4

This patch adds watchdog support to the r8a7745 SoC dtsi.

(modified clocks and power-domains properties. removed resets property)

---
 arch/arm/boot/dts/r8a7745.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

index f19aed2..5cafc3060 100644
@@ -219,6 +219,15 @@
 			reg = <0 0xe6160000 0 0x100>;
 		};
 
+		rwdt: watchdog at e6020000 {
+			compatible = "renesas,r8a7745-wdt",
+				     "renesas,rcar-gen2-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			clocks = <&mstp4_clks R8A7745_CLK_RWDT>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
 		irqc: interrupt-controller at e61c0000 {
 			compatible = "renesas,irqc-r8a7745", "renesas,irqc";
 			#interrupt-cells = <2>;

2.7.4

This patch enables the watchdog from within the iwg20m SoM dtsi.

---
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 1d3e950..d364685 100644
@@ -91,6 +91,11 @@
 	};
 };
 
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";

2.7.4

This patch enables the watchdog from within the iwg20m SoM dtsi.

---
 arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 8d0a392b..29b6e10 100644
@@ -91,6 +91,11 @@
 	};
 };
 
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};
+
 &sdhi1 {
 	pinctrl-0 = <&sdhi1_pins>;
 	pinctrl-names = "default";

2.7.4

R-Car Gen2 and RZ/G1 platforms come with a watchdog IP, therefore enable its driver by default.

---
 arch/arm/configs/shmobile_defconfig | 1 +
 1 file changed, 1 insertion(+)

index 3282a4f..223fbc8 100644
@@ -127,6 +127,7 @@ CONFIG_CPU_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_DA9063_WATCHDOG=y
+CONFIG_RENESAS_WDT=y
 CONFIG_MFD_AS3711=y
 CONFIG_MFD_DA9063=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y

2.7.4

Thanks. I've applied these, with the updated (v2) commit messages for?"soc: renesas: Add R-Car RST driver" and "watchdog: renesas-wdt:
add driver" and the fix I mentioned for "watchdog: renesas_wdt: Add restart handler".

Ben.

Ben Hutchings, Software Developer                ?        Codethink Ltd
https://www.codethink.co.uk/                 Dale House, 35 Dale Street
                                     Manchester, M1 2HF, United Kingdom