Add support for display port clocks and clock ops
cover Add support for display port clocks and clock ops
New display port clock ops supported for display port clocks. Also add support for the display port related branches and RCGs.
Taniya Das (2):
clk: qcom: rcg2: Add support for display port clock ops
clk: qcom : dispcc: Add support for display port clocks
drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 86 +++++++++ drivers/clk/qcom/dispcc-sdm845.c | 232 +++++++++++++++++++++++++ include/dt-bindings/clock/qcom,dispcc-sdm845.h | 11 ++ 4 files changed, 330 insertions(+)
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Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH 1/2 clk: qcom: rcg2: Add support for display port clock ops
New display port clock ops supported for display port clocks.
--- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 86 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+)
drivers/clk/qcom/clk-rcg.h +1 -0
@@ -162,6 +162,7 @@ struct clk_rcg2 {extern const struct clk_ops clk_pixel_ops;extern const struct clk_ops clk_gfx3d_ops;extern const struct clk_ops clk_rcg2_shared_ops; +extern const struct clk_ops clk_dp_ops;struct clk_rcg_dfs_data {struct clk_rcg2 *rcg;
drivers/clk/qcom/clk-rcg2.c +86 -0
95 lines not on this page · raw message
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Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v1 1/2] clk: qcom: rcg2: Add support for display port clock ops
Quoting Taniya Das (2018-10-09 06:57:46)
drivers/clk/qcom/clk-rcg2.c line 13
Quoted 9 lines
drivers/clk/qcom/clk-rcg2.c +1
-0@@ -10,6 +10,7 @@#include <linux/export.h> #include <linux/clk-provider.h> #include <linux/delay.h> +#include <linux/rational.h>
Can you also select RATIONAL in the Kconfig language? Yes the clk subsystem is already selecting it, but it's nice to be explicit in the subdrivers.
Quoted 10 lines
drivers/clk/qcom/clk-rcg2.c +3
-0#include <linux/regmap.h> #include <linux/math64.h> #include <linux/slab.h> @@ -1124,3 +1125,88 @@ int qcom_cc_register_rcg_dfs(struct regmap *regmap,return 0 ; }EXPORT_SYMBOL_GPL (qcom_cc_register_rcg_dfs); + +static int clk_rcg2_dp_set_rate (struct clk_hw *hw,unsigned long rate, +unsigned long parent_rate)
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1140
Quoted 10 lines
drivers/clk/qcom/clk-rcg2.c +10
-0+{ +struct clk_rcg2 *rcg =to_clk_rcg2 (hw); +struct freq_tbl f = {0 }; +unsigned long src_rate; +unsigned long num, den; +u32 mask =BIT (rcg->hid_width) -1 ; +u32 hid_div, cfg; +int i, num_parents =clk_hw_get_num_parents (hw); + + src_rate =clk_hw_get_rate (clk_hw_get_parent (hw));
What is this doing? We shouldn't need to check the parent clk for any rate here when we're setting the rate.
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1147
Quoted 7 lines
drivers/clk/qcom/clk-rcg2.c +7
-0+if (src_rate <=0 ) { +pr_err ("Invalid RCG parent rate\n" ); +return -EINVAL ; + } + + rational_best_approximation(src_rate, rate, + (unsigned long)(1 << 16) - 1,
Use GENMASK?
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1148
Quoted 1 line
drivers/clk/qcom/clk-rcg2.c +1
-0+ (unsigned long)(1 << 16) - 1, &den, &num);
Same?
Quoted 39 lines
drivers/clk/qcom/clk-rcg2.c +39
-0+ +if (!num || !den) { +pr_err ("Invalid MN values derived for requested rate %lu\n" , + rate); +return -EINVAL ; + } + +regmap_read (rcg->clkr.regmap, rcg->cmd_rcgr +CFG_REG , &cfg); + hid_div = cfg; + cfg &=CFG_SRC_SEL_MASK ; + cfg >>=CFG_SRC_SEL_SHIFT ; + +for (i =0 ; i < num_parents; i++) +if (cfg == rcg->parent_map[i].cfg) { + f.src = rcg->parent_map[i].src; +break ; + } + + f.pre_div = hid_div; + f.pre_div >>=CFG_SRC_DIV_SHIFT ; + f.pre_div &= mask; + +if (num == den) { + f.m =0 ; + f.n =0 ; + }else { + f.m = num; + f.n = den; + } + +return clk_rcg2_configure (rcg, &f); +} + +static int clk_rcg2_dp_set_rate_and_parent (struct clk_hw *hw, +unsigned long rate,unsigned long parent_rate,u8 index) +{ +return clk_rcg2_dp_set_rate (hw, rate, parent_rate); +} +
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1197
Quoted 10 lines
drivers/clk/qcom/clk-rcg2.c +10
-0+static int clk_rcg2_dp_determine_rate (struct clk_hw *hw, +struct clk_rate_request *req) +{ +if (!hw) +return -EINVAL ; + +if (!clk_hw_get_parent (hw)) { +pr_err ("Missing the parent for the DP RCG\n" ); +return -EINVAL ; + }
Let me Harry Potter this stuff. Expelliarmus!
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1199
Quoted 2 lines
drivers/clk/qcom/clk-rcg2.c +2
-0+ + req->best_parent_rate =clk_hw_get_rate (clk_hw_get_parent (hw));
Presumably we should ask the parent clk for the rate that is requested here by calling determine rate up and see if the parent can do it. Sure, this clk does nothing, so we don't really need any sort of op here then and we can just flag the clk as CLK_SET_RATE_PARENT and let the core do the rest.
Quoted 13 lines
drivers/clk/qcom/clk-rcg2.c +13
-0+return 0 ; +} + +const struct clk_ops clk_dp_ops = { + .is_enabled = clk_rcg2_is_enabled, + .get_parent = clk_rcg2_get_parent, + .set_parent = clk_rcg2_set_parent, + .recalc_rate = clk_rcg2_recalc_rate, + .set_rate = clk_rcg2_dp_set_rate, + .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent, + .determine_rate = clk_rcg2_dp_determine_rate, +}; +EXPORT_SYMBOL_GPL (clk_dp_ops);
Re: [PATCH v1 1/2] clk: qcom: rcg2: Add support for display port clock ops
Hello Stephen,
Quoted 15 lines · Stephen Boyd
Quoting Taniya Das (2018-10-09 06:57:46)
drivers/clk/qcom/clk-rcg2.c line 13
Quoted 9 lines
drivers/clk/qcom/clk-rcg2.c +1
-0@@ -10,6 +10,7 @@#include <linux/export.h> #include <linux/clk-provider.h> #include <linux/delay.h> +#include <linux/rational.h> Can you also select RATIONAL in the
Kconfiglanguage? Yes the clk subsystem is already selecting it, but it's nice to be explicit in the subdrivers.
Sure, would take care of adding it in KCONFIG.
Quoted 15 lines
Quoted 15 lines
drivers/clk/qcom/clk-rcg2.c +8
-0#include <linux/regmap.h> #include <linux/math64.h> #include <linux/slab.h> @@ -1124,3 +1125,88 @@ int qcom_cc_register_rcg_dfs(struct regmap *regmap,return 0 ; }EXPORT_SYMBOL_GPL (qcom_cc_register_rcg_dfs); + +static int clk_rcg2_dp_set_rate (struct clk_hw *hw,unsigned long rate, +unsigned long parent_rate) +{ +struct clk_rcg2 *rcg =to_clk_rcg2 (hw); +struct freq_tbl f = {0 }; +unsigned long src_rate; +unsigned long num, den;
Quoted 9 lines
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1140
Quoted 5 lines
drivers/clk/qcom/clk-rcg2.c +5
-0+u32 mask =BIT (rcg->hid_width) -1 ; +u32 hid_div, cfg; +int i, num_parents =clk_hw_get_num_parents (hw); + + src_rate =clk_hw_get_rate (clk_hw_get_parent (hw));What is this doing? We shouldn't need to check the parent clk for any rate here when we're setting the rate.
Hmmm, let me get back on this.
Quoted 8 lines
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1147
Quoted 7 lines
drivers/clk/qcom/clk-rcg2.c +7
-0+if (src_rate <=0 ) { +pr_err ("Invalid RCG parent rate\n" ); +return -EINVAL ; + } + + rational_best_approximation(src_rate, rate, + (unsigned long)(1 << 16) - 1,
Quoted 5 lines
Use GENMASK?
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1148
Quoted 1 line
drivers/clk/qcom/clk-rcg2.c +1
-0+ (unsigned long)(1 << 16) - 1, &den, &num);Same? >
Sure, would use GENMASK.
Quoted 61 lines
Quoted 39 lines
drivers/clk/qcom/clk-rcg2.c +39
-0+ +if (!num || !den) { +pr_err ("Invalid MN values derived for requested rate %lu\n" , + rate); +return -EINVAL ; + } + +regmap_read (rcg->clkr.regmap, rcg->cmd_rcgr +CFG_REG , &cfg); + hid_div = cfg; + cfg &=CFG_SRC_SEL_MASK ; + cfg >>=CFG_SRC_SEL_SHIFT ; + +for (i =0 ; i < num_parents; i++) +if (cfg == rcg->parent_map[i].cfg) { + f.src = rcg->parent_map[i].src; +break ; + } + + f.pre_div = hid_div; + f.pre_div >>=CFG_SRC_DIV_SHIFT ; + f.pre_div &= mask; + +if (num == den) { + f.m =0 ; + f.n =0 ; + }else { + f.m = num; + f.n = den; + } + +return clk_rcg2_configure (rcg, &f); +} + +static int clk_rcg2_dp_set_rate_and_parent (struct clk_hw *hw, +unsigned long rate,unsigned long parent_rate,u8 index) +{ +return clk_rcg2_dp_set_rate (hw, rate, parent_rate); +} +drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1197
Quoted 10 lines
drivers/clk/qcom/clk-rcg2.c +10
-0+static int clk_rcg2_dp_determine_rate (struct clk_hw *hw, +struct clk_rate_request *req) +{ +if (!hw) +return -EINVAL ; + +if (!clk_hw_get_parent (hw)) { +pr_err ("Missing the parent for the DP RCG\n" ); +return -EINVAL ; + }Let me Harry Potter this stuff. Expelliarmus!
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1199
Quoted 2 lines
drivers/clk/qcom/clk-rcg2.c +2
-0+ + req->best_parent_rate =clk_hw_get_rate (clk_hw_get_parent (hw));Presumably we should ask the parent clk for the rate that is requested here by calling determine rate up and see if the parent can do it. Sure, this clk does nothing, so we don't really need any sort of op here then and we can just flag the clk as
CLK_SET_RATE_PARENTand let the core do the rest.
Quoted 3 lines
drivers/clk/qcom/clk-rcg2.c int qcom_cc_register_rcg_dfs(struct regmap *regmap, · line 1202
Quoted 3 lines
drivers/clk/qcom/clk-rcg2.c +3
-0+return 0 ; +} +
Would remove this.
Quoted 10 lines
Quoted 10 lines
drivers/clk/qcom/clk-rcg2.c +10
-0+const struct clk_ops clk_dp_ops = { + .is_enabled = clk_rcg2_is_enabled, + .get_parent = clk_rcg2_get_parent, + .set_parent = clk_rcg2_set_parent, + .recalc_rate = clk_rcg2_recalc_rate, + .set_rate = clk_rcg2_dp_set_rate, + .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent, + .determine_rate = clk_rcg2_dp_determine_rate, +}; +EXPORT_SYMBOL_GPL (clk_dp_ops);
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
PATCH 2/2 clk: qcom : dispcc: Add support for display port clocks
In reply to Taniya DasSDM845 dispcc supports RCG and CBCRs for display port, so add support for the same.
--- drivers/clk/qcom/dispcc-sdm845.c | 232 +++++++++++++++++++++++++ include/dt-bindings/clock/qcom,dispcc-sdm845.h | 11 ++ 2 files changed, 243 insertions(+)
drivers/clk/qcom/dispcc-sdm845.c +232 -0
@@ -29,6 +29,8 @@ enum {P_DSI1_PHY_PLL_OUT_DSICLK ,P_GPLL0_OUT_MAIN ,P_GPLL0_OUT_MAIN_DIV , +P_DP_PHY_PLL_LINK_CLK , + P_DP_PHY_PLL_VCO_DIV_CLK, }; static const struct parent_map disp_cc_parent_map_0[] = {
@@ -45,6 +47,20 @@ enum { "core_bi_pll_test_se", }; +static const struct parent_map disp_cc_parent_map_1[] = { + {P_BI_TCXO ,0 }, + {P_DP_PHY_PLL_LINK_CLK ,1 }, + {P_DP_PHY_PLL_VCO_DIV_CLK ,2 }, + {P_CORE_BI_PLL_TEST_SE ,7 }, +}; + +static const char *const disp_cc_parent_names_1[] = { +"bi_tcxo" , +"dp_link_clk_divsel_ten" , +"dp_vco_divided_clk_src_mux" , +"core_bi_pll_test_se" , +}; +static const struct parent_map disp_cc_parent_map_2[] = { {P_BI_TCXO ,0 }, {P_CORE_BI_PLL_TEST_SE ,7 },
@@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { +F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr =0x219c , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk_src" , + .parent_names = disp_cc_parent_names_2, + .num_parents =2 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { +F (108000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (180000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (360000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr =0x2154 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (810000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr =0x2138 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr =0x2184 , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr =0x216c , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), { }
@@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg =0x2054 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_aux_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg =0x2048 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2048 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_crypto_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg =0x2040 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2040 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */ +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { + .halt_reg =0x2050 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2050 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_pixel1_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg =0x204c , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x204c , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_pixel_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch disp_cc_mdss_esc0_clk = { .halt_reg =0x2038 , .halt_check =BRANCH_HALT ,
@@ -589,6 +808,19 @@ enum { [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC ] = &disp_cc_mdss_byte1_div_clk_src.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC ] = + &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC ] = + &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
include/dt-bindings/clock/qcom,dispcc-sdm845.h +11 -0
@@ -35,6 +35,17 @@#define DISP_CC_PLL0 25#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DP_AUX_CLK 28 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 +#define DISP_CC_MDSS_DP_LINK_CLK 32 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 +#define DISP_CC_MDSS_DP_PIXEL_CLK 37 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38/* DISP_CC Reset */ #define DISP_CC_MDSS_RSCC_BCR 0
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Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 37 lines
drivers/clk/qcom/dispcc-sdm845.c +29
-0@@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { +F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr =0x219c , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk_src" , + .parent_names = disp_cc_parent_names_2, + .num_parents =2 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { +F (108000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (180000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (360000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
drivers/clk/qcom/dispcc-sdm845.c enum { · line 185
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE ,
Why?
drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c +9
-0+ .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.
Quoted 98 lines
drivers/clk/qcom/dispcc-sdm845.c +91
-0+ { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr =0x2138 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr =0x2184 , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr =0x216c , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), { }@@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg =0x2054 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_aux_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg =0x2048 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2048 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_crypto_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg =0x2040 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2040 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk" , + .parent_names = (const char *[]){
drivers/clk/qcom/dispcc-sdm845.c enum { · line 558
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
Not sure what this comment is for. But it's interesting nonetheless.
drivers/clk/qcom/dispcc-sdm845.c enum { · line 571
Quoted 13 lines
drivers/clk/qcom/dispcc-sdm845.c +13
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE ,
Why?
Quoted 5 lines
drivers/clk/qcom/dispcc-sdm845.c +5
-0+ .ops = &clk_branch2_ops, + }, + }, +}; +
Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Hello Stephen,
Quoted 51 lines · Stephen Boyd
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 37 lines
drivers/clk/qcom/dispcc-sdm845.c +29
-0@@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { +F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr =0x219c , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk_src" , + .parent_names = disp_cc_parent_names_2, + .num_parents =2 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { +F (108000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (180000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (360000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {drivers/clk/qcom/dispcc-sdm845.c enum { · line 185
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
Quoted 15 lines
drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c +9
-0+ .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.
Let me check back the reason we had to make this change.
Quoted 125 lines
Quoted 98 lines
drivers/clk/qcom/dispcc-sdm845.c +91
-0+ { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr =0x2138 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr =0x2184 , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr =0x216c , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), { }@@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg =0x2054 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_aux_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg =0x2048 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2048 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_crypto_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg =0x2040 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2040 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk" , + .parent_names = (const char *[]){drivers/clk/qcom/dispcc-sdm845.c enum { · line 558
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */ Not sure what this comment is for. But it's interesting nonetheless.
drivers/clk/qcom/dispcc-sdm845.c enum { · line 571
Quoted 13 lines
drivers/clk/qcom/dispcc-sdm845.c +13
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE ,
Quoted 2 lines
Why?
It was a requirement, but let me get back on this too.
Quoted 5 lines
Quoted 5 lines
drivers/clk/qcom/dispcc-sdm845.c +5
-0+ .ops = &clk_branch2_ops, + }, + }, +}; +
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Hello Stephen,
Quoted 71 lines · Taniya Das
Hello Stephen,
Quoted 52 lines · Stephen Boyd
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 38 lines
drivers/clk/qcom/dispcc-sdm845.c +29
-0@@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { +F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr =0x219c , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk_src" , + .parent_names = disp_cc_parent_names_2, + .num_parents =2 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { +F (108000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (180000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (360000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {drivers/clk/qcom/dispcc-sdm845.c enum { · line 186
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
Quoted 15 lines
drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c +9
-0+ .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.
Quoted 1 line
Let me check back the reason we had to make this change.
We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called.
Quoted 127 lines
Quoted 127 lines
Quoted 109 lines
drivers/clk/qcom/dispcc-sdm845.c +46
-0+ { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr =0x2138 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr =0x2184 , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr =0x216c , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ),{ }drivers/clk/qcom/dispcc-sdm845.c +55
-0@@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg =0x2054 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_aux_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg =0x2048 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2048 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_crypto_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg =0x2040 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2040 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 Quoted 1 line
(div 4) */
Not sure what this comment is for. But it's interesting nonetheless.
Quoted 13 lines
drivers/clk/qcom/dispcc-sdm845.c +13
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE ,
Quoted 5 lines
Quoted 2 lines
Why?
It was a requirement, but let me get back on this too.
I had a discussion with the Display Port teams and below is the requirement,
This flag is required since we reset/power-down the PLL every time they disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver properly.
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
drivers/clk/qcom/dispcc-sdm845.c +5
-0+ .ops = &clk_branch2_ops, + }, + }, +}; +
Stephen Boyd
maintainerRe: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoting Taniya Das (2018-10-28 03:34:55)
Quoted 76 lines
Hello Stephen,
Quoted 73 lines · Taniya Das
Hello Stephen,
Quoted 69 lines · Stephen Boyd
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 39 lines
drivers/clk/qcom/dispcc-sdm845.c +29
-0@@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { +F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr =0x219c , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk_src" , + .parent_names = disp_cc_parent_names_2, + .num_parents =2 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { +F (108000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (180000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (360000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {drivers/clk/qcom/dispcc-sdm845.c enum { · line 186
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c +9
-0+ .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact
frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.
Quoted 5 lines
Quoted 1 line
Let me check back the reason we had to make this change.
We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called.
What does this mean? I wanted to know about the weird frequencies listed above, and why it can't be done without a frequency table and direct rates passed up to the parent.
Quoted 131 lines
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drivers/clk/qcom/dispcc-sdm845.c +46
-0+ { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr =0x2138 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr =0x2184 , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr =0x216c , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ),{ }drivers/clk/qcom/dispcc-sdm845.c +55
-0@@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg =0x2054 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_aux_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg =0x2048 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2048 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_crypto_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg =0x2040 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2040 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 Quoted 1 line
(div 4) */
Not sure what this comment is for. But it's interesting nonetheless.
drivers/clk/qcom/dispcc-sdm845.c enum { · line 571
Quoted 13 lines
drivers/clk/qcom/dispcc-sdm845.c +13
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
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Quoted 2 lines
It was a requirement, but let me get back on this too.
I had a discussion with the Display Port teams and below is the requirement,
This flag is required since we reset/power-down the PLL every time they disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver properly.
Ok. So that explains the get rate nocache flag. Can you please add a comment that explains that these clk registers here are lost across suspend/resume of the display device? It really sounds like these display clks are inside of the display power domain and thus they lose their state across the display power domain power down. It would be better if we could properly implement suspend/restore for these clk registers across suspend/resume of the display device so that we don't need this nocache flag and the display code can work together with the clk code here to restore the frequency to the clk.
Is it really the case that the rcg here is always selecting a particular PLL and doing a div-1? Because that is very simple then to just write that setting again on genpd restore.
Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoted 79 lines · Stephen Boyd
Quoting Taniya Das (2018-10-28 03:34:55)
Quoted 78 lines
Hello Stephen,
Quoted 74 lines · Taniya Das
Hello Stephen,
Quoted 53 lines · Stephen Boyd
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 39 lines
drivers/clk/qcom/dispcc-sdm845.c +29
-0@@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { +F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr =0x219c , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk_src" , + .parent_names = disp_cc_parent_names_2, + .num_parents =2 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { +F (108000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (180000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (360000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,3 ,0 ,0 ), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {drivers/clk/qcom/dispcc-sdm845.c enum { · line 186
Quoted 10 lines
drivers/clk/qcom/dispcc-sdm845.c +10
-0+ .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
Quoted 16 lines
drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c +9
-0+ .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact
frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.Let me check back the reason we had to make this change.
Quoted 8 lines
Quoted 3 lines
We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called.
What does this mean? I wanted to know about the weird frequencies listed above, and why it can't be done without a frequency table and direct rates passed up to the parent.
OOps, my bad :(.
We added these changes to handle higher clock rates. These rates when greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz freq list in clock driver.
Let me check if they can do something like the byte/pixel clocks of
display.
Quoted 153 lines
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drivers/clk/qcom/dispcc-sdm845.c +46
-0+ { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr =0x2138 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr =0x2184 , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel1_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr =0x216c , + .mnd_width =16 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_pixel_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_dp_ops, + }, +}; +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {F (19200000 ,P_BI_TCXO ,1 ,0 ,0 ),{ }drivers/clk/qcom/dispcc-sdm845.c +55
-0@@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg =0x2054 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2054 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_aux_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_aux_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg =0x2048 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2048 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_crypto_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg =0x2040 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2040 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 Quoted 1 line
(div 4) */
Not sure what this comment is for. But it's interesting nonetheless.
drivers/clk/qcom/dispcc-sdm845.c enum { · line 571
Quoted 13 lines
drivers/clk/qcom/dispcc-sdm845.c +13
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
Quoted 7 lines
Quoted 2 lines
It was a requirement, but let me get back on this too.
I had a discussion with the Display Port teams and below is the requirement,
This flag is required since we reset/power-down the PLL every time they disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver properly.
Ok. So that explains the get rate nocache flag. Can you please add a comment that explains that these clk registers here are lost across suspend/resume of the display device? It really sounds like these display clks are inside of the display power domain and thus they lose their state across the display power domain power down. It would be better if we could properly implement suspend/restore for these clk registers across suspend/resume of the display device so that we don't need this nocache flag and the display code can work together with the clk code here to restore the frequency to the clk.
Is it really the case that the rcg here is always selecting a particular PLL and doing a div-1? Because that is very simple then to just write that setting again on genpd restore.
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Stephen Boyd
maintainerRe: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoting Taniya Das (2018-10-29 23:01:44)
Quoted 37 lines · Stephen Boyd
Quoted 27 lines
Quoting Taniya Das (2018-10-28 03:34:55)
Quoted 26 lines · Taniya Das
Quoted 24 lines · Stephen Boyd
Quoted 12 lines
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 11 lines
drivers/clk/qcom/dispcc-sdm845.c +6
-0+ }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ),Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
Quoted 2 lines
drivers/clk/qcom/dispcc-sdm845.c +2
-0+F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact
frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.Let me check back the reason we had to make this change.
Quoted 8 lines
Quoted 3 lines
We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called.
What does this mean? I wanted to know about the weird frequencies listed above, and why it can't be done without a frequency table and direct rates passed up to the parent.
Quoted 8 lines
OOps, my bad :(.
We added these changes to handle higher clock rates. These rates when greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz freq list in clock driver.
Let me check if they can do something like the byte/pixel clocks of
display.
Well then we really should just throw away the freq table here and have rcg ops that pass the frequency up to the display PLL. Also, those numbers look like gigabits per second (Gbit/s) for the DP spec which isn't exactly the same as a clk frequency. What frequency does the PLL run at for these various DP link speeds?
Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
+ Chandan from Display Port team,
Quoted 47 lines · Stephen Boyd
Quoting Taniya Das (2018-10-29 23:01:44)
Quoted 37 lines · Stephen Boyd
Quoted 27 lines
Quoting Taniya Das (2018-10-28 03:34:55)
Quoted 26 lines · Taniya Das
Quoted 24 lines · Stephen Boyd
Quoted 12 lines
Quoting Taniya Das (2018-10-09 06:57:47)
Quoted 11 lines
drivers/clk/qcom/dispcc-sdm845.c +6
-0+ }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ),Quoted 9 lines
drivers/clk/qcom/dispcc-sdm845.c
Quoted 2 lines
drivers/clk/qcom/dispcc-sdm845.c +2
-0+F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact
frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.Let me check back the reason we had to make this change.
Quoted 8 lines
Quoted 3 lines
We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called.
What does this mean? I wanted to know about the weird frequencies listed above, and why it can't be done without a frequency table and direct rates passed up to the parent.
Quoted 8 lines
OOps, my bad :(.
We added these changes to handle higher clock rates. These rates when greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz freq list in clock driver.
Let me check if they can do something like the byte/pixel clocks of
display.
Quoted 6 lines
Well then we really should just throw away the freq table here and have rcg ops that pass the frequency up to the display PLL. Also, those numbers look like gigabits per second (Gbit/s) for the DP spec which isn't exactly the same as a clk frequency. What frequency does the PLL run at for these various DP link speeds?
Could you please help with the above query from Stephen?
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Stephen Boyd
maintainerRe: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoting Taniya Das (2018-10-31 22:02:22)
Quoted 9 lines
+ Chandan from Display Port team,
Quoted 5 lines · Stephen Boyd
Also, those
numbers look like gigabits per second (Gbit/s) for the DP spec which isn't exactly the same as a clk frequency. What frequency does the PLL run at for these various DP link speeds?Could you please help with the above query from Stephen?
Can I safely assume that it matches the link rate shown on Wikipedia for display port[1]? I.e.
RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link symbol rate)
HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link symbol rate)
HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link symbol rate), introduced in DP 1.2
HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link symbol rate), introduced in DP 1.3
So then they're MHz but the table is written in kHz when it should be written in Hz. Either way, the table can be removed and then we just need to fix the DP PHY PLL code to accept Hz instead of kHz.
Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoted 10 lines · Stephen Boyd
Quoting Taniya Das (2018-10-31 22:02:22)
Quoted 9 lines
+ Chandan from Display Port team,
Quoted 5 lines · Stephen Boyd
Also, those
numbers look like gigabits per second (Gbit/s) for the DP spec which isn't exactly the same as a clk frequency. What frequency does the PLL run at for these various DP link speeds?Could you please help with the above query from Stephen?
Hello Stephen,
For DP link speed of 5.4Gbit/s, the PLL will be running at 10.8 Ghz. For all the other DP link speeds, the PLL will be running at 8.1 Ghz.
Quoted 18 lines
Can I safely assume that it matches the link rate shown on Wikipedia for display port[1]? I.e.
RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link symbol rate)
HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link symbol rate)
HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link symbol rate), introduced in DP 1.2
HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link symbol rate), introduced in DP 1.3So then they're MHz but the table is written in kHz when it should be written in Hz. Either way, the table can be removed and then we just need to fix the DP PHY PLL code to accept Hz instead of kHz.
Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
In reply to Stephen BoydHello Stephen,
Quoted 6 lines · Stephen Boyd
Quoting Taniya Das (2018-10-28 03:34:55)
Quoted 5 lines
Hello Stephen,
Quoted 2 lines · Taniya Das
Hello Stephen,
/snip
Quoted 33 lines
Quoted 33 lines
Quoted 32 lines
Quoted 14 lines
drivers/clk/qcom/dispcc-sdm845.c enum { · line 185
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drivers/clk/qcom/dispcc-sdm845.c +11
-0+static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr =0x2154 , + .mnd_width =0 , + .hid_width =5 , + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_crypto_clk_src" , + .parent_names = disp_cc_parent_names_1, + .num_parents =4 , + .flags =CLK_GET_RATE_NOCACHE ,Why?
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drivers/clk/qcom/dispcc-sdm845.c enum { · line 194
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drivers/clk/qcom/dispcc-sdm845.c +9
-0+ .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { +F (162000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (270000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), +F (540000 ,P_DP_PHY_PLL_LINK_CLK ,1 ,0 ,0 ), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact
frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do.Let me check back the reason we had to make this change.
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We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called.
What does this mean? I wanted to know about the weird frequencies listed above, and why it can't be done without a frequency table and direct rates passed up to the parent.
/snip
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drivers/clk/qcom/dispcc-sdm845.c +3
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT ,drivers/clk/qcom/dispcc-sdm845.c enum { · line 571
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drivers/clk/qcom/dispcc-sdm845.c +10
-0+ .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE,Why?
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It was a requirement, but let me get back on this too.
I had a discussion with the Display Port teams and below is the requirement,
This flag is required since we reset/power-down the PLL every time they disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver properly.
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Ok. So that explains the get rate nocache flag. Can you please add a comment that explains that these clk registers here are lost across suspend/resume of the display device? It really sounds like these display clks are inside of the display power domain and thus they lose their state across the display power domain power down. It would be better if we could properly implement suspend/restore for these clk registers across suspend/resume of the display device so that we don't need this nocache flag and the display code can work together with the clk code here to restore the frequency to the clk.
We already handle the suspend/restore for these clk registers
in Dp PLL domain. Without the "NOCACHE_FLAG", and if we are requesting the same clock rate for any of the clocks, the set_rate call never reaches the DP PLL Ops.
I am not clear on what you are suggesting for removing the "NOCACHE_FLAG" for the DisplayPort clocks. Are you suggesting design changes in DP PLL driver or in dispcc-driver? Can you please provide more details?
thanks
Chandan
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Is it really the case that the rcg here is always selecting a particular PLL and doing a div-1? Because that is very simple then to just write that setting again on genpd restore.
Stephen Boyd
maintainerRe: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Quoting [email protected] (2019-02-01 16:05:55)
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Quoting Taniya Das (2018-10-28 03:34:55)
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drivers/clk/qcom/dispcc-sdm845.c +13
-0+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg =0x2044 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x2044 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="disp_cc_mdss_dp_link_intf_clk" , + .parent_names = (const char *[]){ +"disp_cc_mdss_dp_link_clk_src" , + }, + .num_parents =1 , + .flags =CLK_GET_RATE_NOCACHE ,Quoted 5 lines
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Why?
It was a requirement, but let me get back on this too.
I had a discussion with the Display Port teams and below is the requirement,
This flag is required since we reset/power-down the PLL every time they
disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver properly.
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Ok. So that explains the get rate nocache flag. Can you please add a comment that explains that these clk registers here are lost across suspend/resume of the display device? It really sounds like these display clks are inside of the display power domain and thus they lose their state across the display power domain power down. It would be better if we could properly implement suspend/restore for these clk registers across suspend/resume of the display device so that we don't need this nocache flag and the display code can work together with the clk code here to restore the frequency to the clk.
This patch came again and it didn't have any comments to this effect in the code around the flag.
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We already handle the suspend/restore for these clk registers in Dp PLL domain. Without the "
NOCACHE_FLAG", and if we are requesting the same clock rate
for any of the clocks, theset_ratecall never reaches the DP PLL Ops.
So do you restore the frequency of the PLL manually? Or that is done by calling clk_set_rate() on the leaf clk again?
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I am not clear on what you are suggesting for removing the "
NOCACHE_FLAG" for
the DisplayPort clocks. Are you suggesting design changes in DP PLL driver or in dispcc-driver?
Can you please provide more details?
I'm suggesting that the clk framework needs to be told that the PLL has lost the rate and thus should do a save/restore of the registers so that the clk framework can be back in sync with the clk hardware. Maybe it's as simple as calling clk_set_rate(&pll, XO_RATE) or clk_set_parent(&pll, &xo_clk), so that we can recalc the rate down the tree and fix up the child clk frequencies. Or, maybe we need to add some sort of mechanism to the clk framework so it can be told that the frequency here has changed. Or we need to add a hook in the power domain for the DP PLL to tell the clk framework that the clk has changed rate and thus should recalc down to the children. Something like this, instead of an obtuse flag that tells us very little about what's going on.