drm/amdgpu: fix bug with IH ring setup
Subsystems (2)
PATCH 1/1 drm/amdgpu: fix bug with IH ring setup
The bug limits the IH ring wptr address to 40bit. When the system memory is bigger than 1TB, the bus address is more than 40bit, this causes the interrupt cannot be handled and cleared correctly.
--- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/amd/amdgpu/vega10_ih.c +1 -1
@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)else wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs *4 );WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_WPTR_ADDR_LO,lower_32_bits (wptr_off)); -WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_WPTR_ADDR_HI,upper_32_bits (wptr_off) &0xFF ); +WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_WPTR_ADDR_HI,upper_32_bits (wptr_off) &0xFFFF );/* set rptr, wptr to 0 */ WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_RPTR,0 );
Signature · 6 lines
2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): 1542050408-19731-1-git-send-email-Philip.Yang-5C7GfCeVMHo@public.gmane.org
Deucher, Alexander
Reviewed-by________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Yang, Philip <[email protected]>
Sent: Monday, November 12, 2018 2:20 PM
To: [email protected]
Cc: Yang, Philip
Subject: [PATCH] drm/amdgpu: fix bug with IH ring setup
The bug limits the IH ring wptr address to 40bit. When the system memory is bigger than 1TB, the bus address is more than 40bit, this causes the interrupt cannot be handled and cleared correctly.
--- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/amd/amdgpu/vega10_ih.c +1 -1
@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)else wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs *4 );WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_WPTR_ADDR_LO,lower_32_bits (wptr_off)); -WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_WPTR_ADDR_HI,upper_32_bits (wptr_off) &0xFF ); +WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_WPTR_ADDR_HI,upper_32_bits (wptr_off) &0xFFFF );/* set rptr, wptr to 0 */ WREG32_SOC15 (OSSSYS ,0 , mmIH_RB_RPTR,0 );
--
2.7.4
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_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): BN6PR12MB18094950A3FC8AA193D0A821F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org
Christian König
Reviewed-byAm 12.11.18 um 20:33 schrieb Deucher, Alexander:
Quoted 35 lines
Reviewed-by Alex Deucher <[email protected]>------------------------------------------------------------------------
*From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Yang, Philip <[email protected]> *Sent:* Monday, November 12, 2018 2:20 PM
*To:* [email protected]
*Cc:* Yang, Philip
*Subject:* [PATCH] drm/amdgpu: fix bug with IH ring setup
The bug limits the IH ring wptr address to 40bit. When the system memory
is bigger than 1TB, the bus address is more than 40bit, this causes the
interrupt cannot be handled and cleared correctly.Change-Id I3cd1b8ad046b38945372f2fd1a2d225624893e28Signed-off-by Philip Yang <[email protected]>---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-1 file changed, 1 insertion(+), 1 deletion(-)drivers/gpu/drm/amd/amdgpu/vega10_ih.c +0
-0@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)else
wptr_off=adev->wb.gpu_addr+ (adev->irq.ih.wptr_offs* 4);WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); -WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);
Quoted 14 lines
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);Signature · 11 lines
2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[email protected]
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