arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
Subsystems (5)
Dinh Nguyen
maintainerPATCH 1/3 arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
From: Dinh Nguyen <[email protected]>
The standard reset-simple driver the uses the "altr,rst-mgr" binding is not getting initialized early enough in the boot process, so timers that the kernel needs are still left in reset. Thus an early reset driver was created. This early reset driver is only for the SoCFPGA 32-bit platform.
The Stratix10 platform does not need any of the timers that in reset to boot, thus we don't need to early reset driver. Therefore, use the "altr,stratix10-rst-mgr" binding for the reset-simple platform driver on the Stratix10 platform.
Also remove the "altr,modrst-offset" property because the driver no longer needs it.
--- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +1 -2
@@ -308,9 +308,8 @@ rst: rstmgr@ffd11000 { #reset-cells = <1>; - compatible = "altr,rst-mgr"; + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg = <0xffd11000 0x1000>; - altr,modrst-offset = <0x20>; }; spi0: spi@ffda4000 {
Signature · 1 line
2.17.1
Dinh Nguyen
maintainerPATCH v3 2/3 reset: socfpga: add an early reset driver for SoCFPGA
From: Dinh Nguyen <[email protected]>
Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup.
We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver.
---
v3: use "altr,stratix10-rst-mgr" for Stratix10
remove "altr,modrst-offset" from reset-simple
v2: Do not build separate reset driver for STRATIX10
fix warning: symbol 'socfpga_reset_init' was not declared. Should it be static?
--- arch/arm/mach-socfpga/socfpga.c | 4 ++ drivers/reset/Kconfig | 9 +++- drivers/reset/Makefile | 1 + drivers/reset/reset-simple.c | 12 +---- drivers/reset/reset-socfpga.c | 88 +++++++++++++++++++++++++++++++++ 5 files changed, 103 insertions(+), 11 deletions(-) create mode 100644 drivers/reset/reset-socfpga.c
arch/arm/mach-socfpga/socfpga.c +4 -0
@@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr;void __iomem *sdr_ctl_base_addr;unsigned long socfpga_cpu1start_addr; +extern void __init socfpga_reset_init (void ); +void __init socfpga_sysmgr_init (void ) {struct device_node *np;
@@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void)if (IS_ENABLED (CONFIG_EDAC_ALTERA_OCRAM ))socfpga_init_ocram_ecc (); +socfpga_reset_init (); }static void __init socfpga_arria10_init_irq (void )
@@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void)socfpga_init_arria10_l2_ecc ();if (IS_ENABLED (CONFIG_EDAC_ALTERA_OCRAM ))socfpga_init_arria10_ocram_ecc (); +socfpga_reset_init (); }static void socfpga_cyclone5_restart (enum reboot_mode mode,const char *cmd)
drivers/reset/Kconfig +8 -1
@@ -109,7 +109,7 @@ config RESET_QCOM_PDC config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous,
@@ -128,6 +128,13 @@ config RESET_STM32MP157 help This enables the RCC reset controller driver for STM32 MPUs. +config RESET_SOCFPGA + bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA + default ARCH_SOCFPGA && !ARCH_STRATIX10 + select RESET_SIMPLE + help + This enables the reset driver for SoCFPGA. + config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI default ARCH_SUNXI
drivers/reset/Makefile +1 -0
@@ -19,6 +19,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
drivers/reset/reset-simple.c +2 -10
@@ -109,7 +109,7 @@ struct reset_simple_devdata {#define SOCFPGA_NR_BANKS 8static const struct reset_simple_devdata reset_simple_socfpga = { - .reg_offset =0x10 , + .reg_offset =0x20 , .nr_resets =SOCFPGA_NR_BANKS *32 , .status_active_low = true, };
@@ -120,7 +120,7 @@ static const struct reset_simple_devdata reset_simple_active_low = { };static const struct of_device_id reset_simple_dt_ids[] = { - { .compatible ="altr,rst-mgr" , .data = &reset_simple_socfpga }, + { .compatible ="altr,stratix10-rst-mgr" ,"altr,rst-mgr" , .data = &reset_simple_socfpga }, { .compatible ="st,stm32-rcc" , }, { .compatible ="allwinner,sun6i-a31-clock-reset" , .data = &reset_simple_active_low },
@@ -166,14 +166,6 @@ static int reset_simple_probe(struct platform_device *pdev) data->status_active_low = devdata->status_active_low; } -if (of_device_is_compatible (dev->of_node,"altr,rst-mgr" ) && -of_property_read_u32 (dev->of_node,"altr,modrst-offset" , - ®_offset)) { -dev_warn (dev, -"missing altr,modrst-offset property, assuming 0x%x!\n" , - reg_offset); - } - data->membase += reg_offset;return devm_reset_controller_register (dev, &data->rcdev);
drivers/reset/reset-socfpga.c new file +88 -0
88 lines not on this page · raw message
Signature · 1 line
2.17.1
Philipp Zabel
maintainerRe: [PATCHv3 2/3] reset: socfpga: add an early reset driver for SoCFPGA
Hi Dinh,
Quoted 74 lines · Dinh Nguyen
From: Dinh Nguyen <[email protected]>
Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup.
We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: use "altr,stratix10-rst-mgr" for Stratix10
remove "altr,modrst-offset" from reset-simple
v2: Do not build separate reset driver for STRATIX10
fix warning: symbol 'socfpga_reset_init' was not declared. Should it be static?--- arch/arm/mach-socfpga/socfpga.c | 4 ++ drivers/reset/Kconfig | 9 +++- drivers/reset/Makefile | 1 + drivers/reset/reset-simple.c | 12 +---- drivers/reset/reset-socfpga.c | 88 +++++++++++++++++++++++++++++++++ 5 files changed, 103 insertions(+), 11 deletions(-) create mode 100644 drivers/reset/reset-socfpga.carch/arm/mach-socfpga/socfpga.c +4
-0@@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr;void __iomem *sdr_ctl_base_addr;unsigned long socfpga_cpu1start_addr; +extern void __init socfpga_reset_init (void ); +void __init socfpga_sysmgr_init (void ) {struct device_node *np;@@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void)if (IS_ENABLED (CONFIG_EDAC_ALTERA_OCRAM ))socfpga_init_ocram_ecc (); +socfpga_reset_init (); }static void __init socfpga_arria10_init_irq (void )@@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void)socfpga_init_arria10_l2_ecc ();if (IS_ENABLED (CONFIG_EDAC_ALTERA_OCRAM ))socfpga_init_arria10_ocram_ecc (); +socfpga_reset_init (); }static void socfpga_cyclone5_restart (enum reboot_mode mode,const char *cmd)drivers/reset/Kconfig +1
-1@@ -109,7 +109,7 @@ config RESET_QCOM_PDC config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous,
drivers/reset/Kconfig config RESET_STM32MP157 · line 133
Quoted 6 lines
drivers/reset/Kconfig +3
-0@@ -128,6 +128,13 @@ config RESET_STM32MP157 help This enables the RCC reset controller driver for STM32 MPUs. +config RESET_SOCFPGA + bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA + default ARCH_SOCFPGA && !ARCH_STRATIX10
I don't understand the "&& !ARCH_STRATIX10" part.
Isn't ARCH_SOCFPGA disabled anyway when ARCH_STRATIX10 is enabled?
Quoted 33 lines
drivers/reset/Kconfig +4
-0+ select RESET_SIMPLE + help + This enables the reset driver for SoCFPGA. + config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI default ARCH_SUNXIdrivers/reset/Makefile +1
-0@@ -19,6 +19,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.odrivers/reset/reset-simple.c +1
-1@@ -109,7 +109,7 @@ struct reset_simple_devdata {#define SOCFPGA_NR_BANKS 8static const struct reset_simple_devdata reset_simple_socfpga = { - .reg_offset =0x10 , + .reg_offset =0x20 , .nr_resets =SOCFPGA_NR_BANKS *32 , .status_active_low = true, };
drivers/reset/reset-simple.c static const struct reset_simple_devdata reset_simple_active_low = { · line 123
Quoted 5 lines
drivers/reset/reset-simple.c +1
-1@@ -120,7 +120,7 @@ static const struct reset_simple_devdata reset_simple_active_low = { };static const struct of_device_id reset_simple_dt_ids[] = { - { .compatible ="altr,rst-mgr" , .data = &reset_simple_socfpga }, + { .compatible ="altr,stratix10-rst-mgr" ,"altr,rst-mgr" , .data = &reset_simple_socfpga },
checkpatch.pl complains about missing whitespace and a long line here.
Quoted 24 lines
drivers/reset/reset-simple.c +0
-8{ .compatible = "st,stm32-rcc", }, { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low },@@ -166,14 +166,6 @@ static int reset_simple_probe(struct platform_device *pdev) data->status_active_low = devdata->status_active_low; } -if (of_device_is_compatible (dev->of_node,"altr,rst-mgr" ) && -of_property_read_u32 (dev->of_node,"altr,modrst-offset" , - ®_offset)) { -dev_warn (dev, -"missing altr,modrst-offset property, assuming 0x%x!\n" , - reg_offset); - } - data->membase += reg_offset;return devm_reset_controller_register (dev, &data->rcdev);drivers/reset/reset-socfpga.c new file +0
-0
drivers/reset/reset-socfpga.c line 1
Quoted 1 line
drivers/reset/reset-socfpga.c new file +1
-0@@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0
I think checkpatch.pl complains about the tab here.
regards
Philipp
Dinh Nguyen
maintainerPATCH 3/3 ARM: socfpga: dts: document "altr,stratix10-rst-mgr" binding
In reply to Dinh Nguyen"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
--- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/reset/socfpga-reset.txt +2 -1
@@ -1,7 +1,8 @@ Altera SOCFPGA Reset Manager Required properties: -- compatible : "altr,rst-mgr" +- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10) + "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC - reg : Should contain 1 register ranges(address and length) - altr,modrst-offset : Should contain the offset of the first modrst register. - #reset-cells: 1
Signature · 1 line
2.17.1
Philipp Zabel
maintainerRe: [PATCH 3/3] ARM: socfpga: dts: document "altr,stratix10-rst-mgr" binding
Hi Dinh,
Quoted 12 lines · Dinh Nguyen
"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
Signed-off-by Dinh Nguyen <[email protected]>--- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/reset/socfpga-reset.txt +0
-0
Documentation/devicetree/bindings/reset/socfpga-reset.txt line 5
Quoted 6 lines
Documentation/devicetree/bindings/reset/socfpga-reset.txt +2
-1@@ -1,7 +1,8 @@ Altera SOCFPGA Reset Manager Required properties: -- compatible : "altr,rst-mgr" +- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10) + "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
git grep '\(altr\|intel\),stratix10'
currently only shows "intel,stratix10-clkmgr". Should this be "intel,stratix10-rst-mgr"? I think keeping "altr," is fine for consistency, just wanted to point it out.
Documentation/devicetree/bindings/reset/socfpga-reset.txt line 8
Quoted 3 lines
Documentation/devicetree/bindings/reset/socfpga-reset.txt +0
-0- reg : Should contain 1 register ranges(address and length) - altr,modrst-offset : Should contain the offset of the first modrst register. - #reset-cells: 1
regards
Philipp
Dinh Nguyen
maintainerRe: [PATCH 3/3] ARM: socfpga: dts: document "altr,stratix10-rst-mgr" binding
Quoted 24 lines · Philipp Zabel
Hi Dinh,
Quoted 12 lines · Dinh Nguyen
"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
Signed-off-by Dinh Nguyen <[email protected]>--- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/reset/socfpga-reset.txt +0
-0Documentation/devicetree/bindings/reset/socfpga-reset.txt line 5
Quoted 6 lines
Documentation/devicetree/bindings/reset/socfpga-reset.txt +2
-1@@ -1,7 +1,8 @@ Altera SOCFPGA Reset Manager Required properties: -- compatible : "altr,rst-mgr" +- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10) + "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoCgit grep '\(altr\|intel\),stratix10'
Quoted 4 lines
currently only shows "intel,stratix10-clkmgr". Should this be "intel,stratix10-rst-mgr"? I think keeping "altr," is fine for consistency, just wanted to point it out.
Thanks for pointing it out. I think it's okay to keep it "altr".
Dinh
Philipp Zabel
maintainerHi Dinh,
Quoted 26 lines · Dinh Nguyen
From: Dinh Nguyen <[email protected]>
The standard reset-simple driver the uses the "altr,rst-mgr" binding is not getting initialized early enough in the boot process, so timers that the kernel needs are still left in reset. Thus an early reset driver was created. This early reset driver is only for the SoCFPGA 32-bit platform.
The Stratix10 platform does not need any of the timers that in reset to boot, thus we don't need to early reset driver. Therefore, use the "altr,stratix10-rst-mgr" binding for the reset-simple platform driver on the Stratix10 platform.
Also remove the "altr,modrst-offset" property because the driver no longer needs it.
Signed-off-by Dinh Nguyen <[email protected]>--- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +0
-0
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi line 315
Quoted 10 lines
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +1
-2@@ -308,9 +308,8 @@ rst: rstmgr@ffd11000 { #reset-cells = <1>; - compatible = "altr,rst-mgr"; + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg = <0xffd11000 0x1000>; - altr,modrst-offset = <0x20>; }; spi0: spi@ffda4000 {
Do you want me to pick this up as well, or just patches 2 and 3?
regards
Philipp
Dinh Nguyen
maintainerQuoted 38 lines · Philipp Zabel
Hi Dinh,
Quoted 35 lines · Dinh Nguyen
From: Dinh Nguyen <[email protected]>
The standard reset-simple driver the uses the "altr,rst-mgr" binding is not getting initialized early enough in the boot process, so timers that the kernel needs are still left in reset. Thus an early reset driver was created. This early reset driver is only for the SoCFPGA 32-bit platform.
The Stratix10 platform does not need any of the timers that in reset to boot, thus we don't need to early reset driver. Therefore, use the "altr,stratix10-rst-mgr" binding for the reset-simple platform driver on the Stratix10 platform.
Also remove the "altr,modrst-offset" property because the driver no longer needs it.
Signed-off-by Dinh Nguyen <[email protected]>--- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +1
-2@@ -308,9 +308,8 @@ rst: rstmgr@ffd11000 { #reset-cells = <1>; - compatible = "altr,rst-mgr"; + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg = <0xffd11000 0x1000>; - altr,modrst-offset = <0x20>; };
Quoted 4 lines
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi line 315
Quoted 1 line
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +0
-0spi0: spi@ffda4000 {Do you want me to pick this up as well, or just patches 2 and 3?
I'll take this patch through arm-soc to avoid conflicts. Can you please pick up 2 and 3?
Thanks,
Dinh