Add U-Boot support for MediaTek SoCs - MT7623n & MT7629

This patch adds support for MTK boot image generation.

Signed-off-by Weijie Gao <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

---
 Makefile             |  22 ++
 common/image.c       |   1 +
 include/image.h      |   1 +
 scripts/Makefile.spl |  11 +
 tools/Makefile       |   1 +
 tools/mtkimage.c     | 749 +++++++++++++++++++++++++++++++++++++++++++++++++++
 tools/mtkimage.h     | 199 ++++++++++++++
 7 files changed, 984 insertions(+)
 create mode 100644 tools/mtkimage.c
 create mode 100644 tools/mtkimage.h

Hi Ryder,

Quoted 4 lines · Ryder Lee

This patch adds support for MTK boot image generation.

Signed-off-by Weijie Gao <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

Quoted 11 lines

---
 Makefile             |  22 ++
 common/image.c       |   1 +
 include/image.h      |   1 +
 scripts/Makefile.spl |  11 +
 tools/Makefile       |   1 +
 tools/mtkimage.c     | 749 +++++++++++++++++++++++++++++++++++++++++++++++++++
 tools/mtkimage.h     | 199 ++++++++++++++
 7 files changed, 984 insertions(+)
 create mode 100644 tools/mtkimage.c
 create mode 100644 tools/mtkimage.h

The mkimage stuff looks fine.

But can you use binman for the pad/cat part of this? See for example sunxi. - sunxi-u-boot.dtsi

Also mtkimage.c is too close to mkimage.c - how about mtk_image.c ?

This patch adds MT7629 device tree and the includes it needs.

Signed-off-by Ryder Lee <[email protected]>

---
 arch/arm/dts/Makefile                    |   3 +
 arch/arm/dts/mt7629-rfb.dts              |  71 +++++++++
 arch/arm/dts/mt7629.dtsi                 | 244 +++++++++++++++++++++++++++++++
 include/dt-bindings/clock/mt7629-clk.h   | 206 ++++++++++++++++++++++++++
 include/dt-bindings/power/mt7629-power.h |  13 ++
 5 files changed, 537 insertions(+)
 create mode 100644 arch/arm/dts/mt7629-rfb.dts
 create mode 100644 arch/arm/dts/mt7629.dtsi
 create mode 100644 include/dt-bindings/clock/mt7629-clk.h
 create mode 100644 include/dt-bindings/power/mt7629-power.h

This adds device tree for MT7623 development board - Bananapi R2 Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 arch/arm/dts/Makefile                    |   1 +
 arch/arm/dts/mt7623.dtsi                 | 255 +++++++++++++++++++
 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 ++++++++++++++++
 include/dt-bindings/clock/mt7623-clk.h   | 413 +++++++++++++++++++++++++++++++
 include/dt-bindings/power/mt7623-power.h |  19 ++
 5 files changed, 895 insertions(+)
 create mode 100644 arch/arm/dts/mt7623.dtsi
 create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
 create mode 100644 include/dt-bindings/clock/mt7623-clk.h
 create mode 100644 include/dt-bindings/power/mt7623-power.h

This adds a general board file based on MT7629 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks.

Signed-off-by Ryder Lee <[email protected]>

Signed-off-by Weijie Gao <[email protected]>

---
 arch/arm/Kconfig                              |  14 +++
 arch/arm/Makefile                             |   1 +
 arch/arm/include/asm/arch-mediatek/misc.h     |  17 ++++
 arch/arm/mach-mediatek/Kconfig                |  24 +++++
 arch/arm/mach-mediatek/Makefile               |   6 ++
 arch/arm/mach-mediatek/cpu.c                  |  34 +++++++
 arch/arm/mach-mediatek/init.h                 |  11 +++
 arch/arm/mach-mediatek/mt7629/Makefile        |   4 +
 arch/arm/mach-mediatek/mt7629/init.c          | 131 ++++++++++++++++++++++++++
 arch/arm/mach-mediatek/mt7629/lowlevel_init.S |  50 ++++++++++
 arch/arm/mach-mediatek/spl.c                  |  43 +++++++++
 board/mediatek/mt7629/Kconfig                 |  17 ++++
 board/mediatek/mt7629/MAINTAINERS             |   7 ++
 board/mediatek/mt7629/Makefile                |   3 +
 board/mediatek/mt7629/mt7629_rfb.c            |  16 ++++
 configs/mt7629_rfb_defconfig                  |  73 ++++++++++++++
 include/configs/mt7629.h                      |  62 ++++++++++++
 17 files changed, 513 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h
 create mode 100644 arch/arm/mach-mediatek/Kconfig
 create mode 100644 arch/arm/mach-mediatek/Makefile
 create mode 100644 arch/arm/mach-mediatek/cpu.c
 create mode 100644 arch/arm/mach-mediatek/init.h
 create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt7629/init.c

 create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S
 create mode 100644 arch/arm/mach-mediatek/spl.c
 create mode 100644 board/mediatek/mt7629/Kconfig
 create mode 100644 board/mediatek/mt7629/MAINTAINERS
 create mode 100644 board/mediatek/mt7629/Makefile
 create mode 100644 board/mediatek/mt7629/mt7629_rfb.c
 create mode 100644 configs/mt7629_rfb_defconfig
 create mode 100644 include/configs/mt7629.h

arch/arm/Kconfig +1 -0

index ccf2a84..eac03f0 100644
@@ -668,6 +668,18 @@ config ARCH_MESON
          targeted at media players and tablet computers. We currently
          support the S905 (GXBaby) 64-bit SoC.
 
+config ARCH_MEDIATEK

arch/arm/Kconfig +3 -0

+
 config ARCH_MX8M
        bool "NXP i.MX8M platform"
        select ARM64

@@ -1423,6 +1435,8 @@ source "arch/arm/mach-rmobile/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 
+source "arch/arm/mach-mediatek/Kconfig"
+
 source "arch/arm/mach-qemu/Kconfig"
 
 source "arch/arm/mach-rockchip/Kconfig"

arch/arm/Makefile +1 -0

index 8f50560..ddb9618 100644
@@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3)             += k3
 machine-$(CONFIG_ARCH_KEYSTONE)                += keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)             += kirkwood
+machine-$(CONFIG_ARCH_MEDIATEK)                += mediatek
 machine-$(CONFIG_ARCH_MESON)           += meson
 machine-$(CONFIG_ARCH_MVEBU)           += mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA

arch/arm/include/asm/arch-mediatek/misc.h new file +17 -0

new file mode 100644
index 0000000..2530e78
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_MISC_H_
+#define __MEDIATEK_MISC_H_
+
+#define VER_BASE               0x08000000
+#define VER_SIZE               0x10
+
+#define APHW_CODE              0x00
+#define APHW_SUBCODE           0x04
+#define APHW_VER               0x08
+#define APSW_VER               0x0c
+
+#endif /* __MEDIATEK_MISC_H_ */

arch/arm/mach-mediatek/Kconfig new file +8 -0

new file mode 100644
index 0000000..a932e70
@@ -0,0 +1,24 @@
+if ARCH_MEDIATEK
+
+config SYS_SOC
+       default "mediatek"
+
+config SYS_VENDOR
+       default "mediatek"
+

arch/arm/mach-mediatek/Kconfig new file +6 -0

+
+endchoice
+
+source "board/mediatek/mt7629/Kconfig"
+
+endif

arch/arm/mach-mediatek/Makefile new file +6 -0

new file mode 100644
index 0000000..852d330
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y  += cpu.o
+obj-$(CONFIG_SPL_BUILD)        += spl.o
+
+obj-$(CONFIG_TARGET_MT7629) += mt7629/

arch/arm/mach-mediatek/cpu.c new file +0 -0

new file mode 100644
index 0000000..2bfeab7

arch/arm/mach-mediatek/cpu.c new file +25 -0

+
+int arch_misc_init(void)
+{
+       struct udevice *wdt;
+       int ret;
+
+       ret = uclass_get_device(UCLASS_WDT, 0, &wdt);
+       if (!ret)
+               wdt_stop(wdt);
+
+       return 0;
+}
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+
+       return 0;
+}
+
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}

arch/arm/mach-mediatek/init.h new file +11 -0

new file mode 100644
index 0000000..1d896fb
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_INIT_H_
+#define __MEDIATEK_INIT_H_
+
+extern int mtk_soc_early_init(void);
+
+#endif /* __MEDIATEK_INIT_H_ */

arch/arm/mach-mediatek/mt7629/Makefile new file +4 -0

new file mode 100644
index 0000000..007eb4a
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o

arch/arm/mach-mediatek/mt7629/init.c new file +5 -0

new file mode 100644
index 0000000..8f195b5
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <[email protected]>
+ */

arch/arm/mach-mediatek/mt7629/init.c new file +49 -0

+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define L2_SHARE_CFG_MP0       0x7f0
+#define L2_SHARE_MODE_OFF      BIT(8)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mtk_pll_early_init(void)
+{
+       unsigned long pll_rates[] = {
+               [CLK_APMIXED_ARMPLL] = 1250000000,
+               [CLK_APMIXED_MAINPLL] = 1120000000,
+               [CLK_APMIXED_UNIV2PLL] = 1200000000,
+               [CLK_APMIXED_ETH1PLL] = 500000000,
+               [CLK_APMIXED_ETH2PLL] = 700000000,
+               [CLK_APMIXED_SGMIPLL] = 650000000,
+       };
+       struct udevice *dev;
+       int ret, i;
+
+       ret = uclass_get_device_by_driver(UCLASS_CLK,
+                       DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
+       if (ret)
+               return ret;
+
+       /* configure default rate then enable apmixedsys */
+       for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+               struct clk clk = { .id = i, .dev = dev };
+
+               ret = clk_set_rate(&clk, pll_rates[i]);
+               if (ret)
+                       return ret;
+
+               ret = clk_enable(&clk);
+               if (ret)
+                       return ret;
+       }
+
+       /* setup mcu bus */
+       ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+                       DM_GET_DRIVER(mtk_mcucfg), &dev);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+int mtk_soc_early_init(void)

arch/arm/mach-mediatek/mt7629/init.c new file +43 -0

+       if (!base)
+               return -ENOENT;
+
+       /* disable L2C shared mode */
+       writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       struct ram_info ram;
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret)
+               return ret;
+
+       ret = ram_get_info(dev, &ram);
+       if (ret)
+               return ret;
+
+       debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+       gd->ram_size = ram.size;
+
+       return 0;
+}
+
+int print_cpuinfo(void)
+{
+       void __iomem *chipid;
+       u32 hwcode, swver;
+
+       chipid = ioremap(VER_BASE, VER_SIZE);
+       hwcode = readl(chipid + APHW_CODE);
+       swver = readl(chipid + APSW_VER);
+
+       printf("CPU:   MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
+
+       return 0;
+}

new file mode 100644
index 0000000..83ccbba

board/mediatek/mt7629/Makefile new file +3 -0

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y += mt7629_rfb.o

board/mediatek/mt7629/mt7629_rfb.c new file +3 -0

new file mode 100644
index 0000000..08468b5
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.

board/mediatek/mt7629/mt7629_rfb.c new file +3 -0

+
+       return 0;
+}

include/configs/mt7629.h new file +46 -0

new file mode 100644
index 0000000..9b51e90
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <[email protected]>
+ */
+
+#ifndef __MT7629_H
+#define __MT7629_H
+
+#include <linux/sizes.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_SYS_MAXARGS             8
+#define CONFIG_SYS_BOOTM_LEN           SZ_64M
+#define CONFIG_SYS_CBSIZE              SZ_1K
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE +    \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          SZ_4M
+
+/* Environment */
+#define CONFIG_ENV_SIZE                        SZ_4K
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Defines for SPL */
+#define CONFIG_SPL_STACK               0x106000
+#define CONFIG_SPL_TEXT_BASE           0x201000
+#define CONFIG_SPL_MAX_SIZE            SZ_64K
+#define CONFIG_SPL_MAX_FOOTPRINT       SZ_64K
+#define CONFIG_SPL_PAD_TO              0x10000
+
+#define CONFIG_SPI_ADDR                        0x30000000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_UBOOT_BASE          (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+
+/* SPL -> Uboot */
+#define CONFIG_SYS_UBOOT_START         CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + SZ_2M - \

include/configs/mt7629.h new file +6 -1

+#define CONFIG_BAUDRATE                        115200
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE          0x40000000
+
+#endif
--

1.9.1

Hi Ryder,

Quoted 33 lines · Ryder Lee

This adds a general board file based on MT7629 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks.

Signed-off-by Ryder Lee <[email protected]>

Signed-off-by Weijie Gao <[email protected]>

---
 arch/arm/Kconfig                              |  14 +++
 arch/arm/Makefile                             |   1 +
 arch/arm/include/asm/arch-mediatek/misc.h     |  17 ++++
 arch/arm/mach-mediatek/Kconfig                |  24 +++++
 arch/arm/mach-mediatek/Makefile               |   6 ++
 arch/arm/mach-mediatek/cpu.c                  |  34 +++++++
 arch/arm/mach-mediatek/init.h                 |  11 +++
 arch/arm/mach-mediatek/mt7629/Makefile        |   4 +
 arch/arm/mach-mediatek/mt7629/init.c          | 131 ++++++++++++++++++++++++++
 arch/arm/mach-mediatek/mt7629/lowlevel_init.S |  50 ++++++++++
 arch/arm/mach-mediatek/spl.c                  |  43 +++++++++
 board/mediatek/mt7629/Kconfig                 |  17 ++++
 board/mediatek/mt7629/MAINTAINERS             |   7 ++
 board/mediatek/mt7629/Makefile                |   3 +
 board/mediatek/mt7629/mt7629_rfb.c            |  16 ++++
 configs/mt7629_rfb_defconfig                  |  73 ++++++++++++++
 include/configs/mt7629.h                      |  62 ++++++++++++
 17 files changed, 513 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h
 create mode 100644 arch/arm/mach-mediatek/Kconfig
 create mode 100644 arch/arm/mach-mediatek/Makefile
 create mode 100644 arch/arm/mach-mediatek/cpu.c
 create mode 100644 arch/arm/mach-mediatek/init.h
 create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt7629/init.c

Quoted 8 lines

 create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S
 create mode 100644 arch/arm/mach-mediatek/spl.c
 create mode 100644 board/mediatek/mt7629/Kconfig
 create mode 100644 board/mediatek/mt7629/MAINTAINERS
 create mode 100644 board/mediatek/mt7629/Makefile
 create mode 100644 board/mediatek/mt7629/mt7629_rfb.c
 create mode 100644 configs/mt7629_rfb_defconfig
 create mode 100644 include/configs/mt7629.h

Looks good. A few nits below

Quoted 10 lines

arch/arm/Kconfig +1 -0

index ccf2a84..eac03f0 100644
@@ -668,6 +668,18 @@ config ARCH_MESON
          targeted at media players and tablet computers. We currently
          support the S905 (GXBaby) 64-bit SoC.
 
+config ARCH_MEDIATEK

arch/arm/Kconfig config ARCH_MESON · line 681

Quoted 10 lines

arch/arm/Kconfig +10 -0

+       bool "MediaTek SoCs"
+       select DM
+       select OF_CONTROL
+       select SPL_DM if SPL
+       select SPL_LIBCOMMON_SUPPORT if SPL
+       select SPL_LIBGENERIC_SUPPORT if SPL
+       select SPL_OF_CONTROL if SPL
+       select SUPPORT_SPL
+       help
+         Support for the MediaTek SoCs family.

Please add more info. What type of SoCs are these? What are the capabilities? Link to web site? datasheets? wiki? Or maybe point to a doc/README.mediatek?

Quoted 62 lines

arch/arm/Kconfig +3 -0

+
 config ARCH_MX8M
        bool "NXP i.MX8M platform"
        select ARM64

@@ -1423,6 +1435,8 @@ source "arch/arm/mach-rmobile/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 
+source "arch/arm/mach-mediatek/Kconfig"
+
 source "arch/arm/mach-qemu/Kconfig"
 
 source "arch/arm/mach-rockchip/Kconfig"

arch/arm/Makefile +1 -0

index 8f50560..ddb9618 100644
@@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3)             += k3
 machine-$(CONFIG_ARCH_KEYSTONE)                += keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)             += kirkwood
+machine-$(CONFIG_ARCH_MEDIATEK)                += mediatek
 machine-$(CONFIG_ARCH_MESON)           += meson
 machine-$(CONFIG_ARCH_MVEBU)           += mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA

arch/arm/include/asm/arch-mediatek/misc.h new file +17 -0

new file mode 100644
index 0000000..2530e78
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_MISC_H_
+#define __MEDIATEK_MISC_H_
+
+#define VER_BASE               0x08000000
+#define VER_SIZE               0x10
+
+#define APHW_CODE              0x00
+#define APHW_SUBCODE           0x04
+#define APHW_VER               0x08
+#define APSW_VER               0x0c
+
+#endif /* __MEDIATEK_MISC_H_ */

arch/arm/mach-mediatek/Kconfig new file +8 -0

new file mode 100644
index 0000000..a932e70
@@ -0,0 +1,24 @@
+if ARCH_MEDIATEK
+
+config SYS_SOC
+       default "mediatek"
+
+config SYS_VENDOR
+       default "mediatek"
+

arch/arm/mach-mediatek/Kconfig line 18

Quoted 10 lines

arch/arm/mach-mediatek/Kconfig new file +10 -0

+choice
+       prompt "MediaTek board select"
+
+config TARGET_MT7629
+       bool "MediaTek MT7629 SoC"
+       select CPU_V7A
+       select SPL
+       select ARCH_MISC_INIT
+       help
+               Support MediaTek MT7629 SoC.

Please describe the features of this SoC.

Quoted 24 lines

arch/arm/mach-mediatek/Kconfig new file +6 -0

+
+endchoice
+
+source "board/mediatek/mt7629/Kconfig"
+
+endif

arch/arm/mach-mediatek/Makefile new file +6 -0

new file mode 100644
index 0000000..852d330
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y  += cpu.o
+obj-$(CONFIG_SPL_BUILD)        += spl.o
+
+obj-$(CONFIG_TARGET_MT7629) += mt7629/

arch/arm/mach-mediatek/cpu.c new file +0 -0

new file mode 100644
index 0000000..2bfeab7

arch/arm/mach-mediatek/cpu.c line 9

Quoted 9 lines

arch/arm/mach-mediatek/cpu.c new file +9 -0

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <wdt.h>

dm/ goes after wdt.h

https://www.denx.de/wiki/U-Boot/CodingStyle

Quoted 63 lines

arch/arm/mach-mediatek/cpu.c new file +25 -0

+
+int arch_misc_init(void)
+{
+       struct udevice *wdt;
+       int ret;
+
+       ret = uclass_get_device(UCLASS_WDT, 0, &wdt);
+       if (!ret)
+               wdt_stop(wdt);
+
+       return 0;
+}
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+
+       return 0;
+}
+
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}

arch/arm/mach-mediatek/init.h new file +11 -0

new file mode 100644
index 0000000..1d896fb
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_INIT_H_
+#define __MEDIATEK_INIT_H_
+
+extern int mtk_soc_early_init(void);
+
+#endif /* __MEDIATEK_INIT_H_ */

arch/arm/mach-mediatek/mt7629/Makefile new file +4 -0

new file mode 100644
index 0000000..007eb4a
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o

arch/arm/mach-mediatek/mt7629/init.c new file +5 -0

new file mode 100644
index 0000000..8f195b5
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <[email protected]>
+ */

arch/arm/mach-mediatek/mt7629/init.c line 15

Quoted 10 lines

arch/arm/mach-mediatek/mt7629/init.c new file +10 -0

+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/sections.h>

fix ordering

Quoted 49 lines

arch/arm/mach-mediatek/mt7629/init.c new file +49 -0

+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define L2_SHARE_CFG_MP0       0x7f0
+#define L2_SHARE_MODE_OFF      BIT(8)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mtk_pll_early_init(void)
+{
+       unsigned long pll_rates[] = {
+               [CLK_APMIXED_ARMPLL] = 1250000000,
+               [CLK_APMIXED_MAINPLL] = 1120000000,
+               [CLK_APMIXED_UNIV2PLL] = 1200000000,
+               [CLK_APMIXED_ETH1PLL] = 500000000,
+               [CLK_APMIXED_ETH2PLL] = 700000000,
+               [CLK_APMIXED_SGMIPLL] = 650000000,
+       };
+       struct udevice *dev;
+       int ret, i;
+
+       ret = uclass_get_device_by_driver(UCLASS_CLK,
+                       DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
+       if (ret)
+               return ret;
+
+       /* configure default rate then enable apmixedsys */
+       for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+               struct clk clk = { .id = i, .dev = dev };
+
+               ret = clk_set_rate(&clk, pll_rates[i]);
+               if (ret)
+                       return ret;
+
+               ret = clk_enable(&clk);
+               if (ret)
+                       return ret;
+       }
+
+       /* setup mcu bus */
+       ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+                       DM_GET_DRIVER(mtk_mcucfg), &dev);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+int mtk_soc_early_init(void)

arch/arm/mach-mediatek/mt7629/init.c line 74

Quoted 10 lines

arch/arm/mach-mediatek/mt7629/init.c new file +10 -0

+{
+       struct udevice *dev;
+       int ret;
+
+       /* initialize early clocks */
+       ret = mtk_pll_early_init();
+       if (ret)
+               return ret;
+
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);

Consider uclass_first_device_err(). Same elsewhere.

arch/arm/mach-mediatek/mt7629/init.c line 87

Quoted 13 lines

arch/arm/mach-mediatek/mt7629/init.c new file +13 -0

+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+int mach_cpu_init(void)
+{
+       void __iomem *base;
+       int node;
+
+       node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+                       "mediatek,mt7629-mcucfg");

Add a driver fopr this - don't access it directly. This could be a syscon device perhaps?

arch/arm/mach-mediatek/mt7629/init.c line 88

Quoted 1 line

arch/arm/mach-mediatek/mt7629/init.c new file +1 -0

+       base = (void __iomem *)fdtdec_get_addr(gd->fdt_blob, node, "reg");

dev_read_addr(). Please use the live tree functions.

Quoted 43 lines

arch/arm/mach-mediatek/mt7629/init.c new file +43 -0

+       if (!base)
+               return -ENOENT;
+
+       /* disable L2C shared mode */
+       writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       struct ram_info ram;
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret)
+               return ret;
+
+       ret = ram_get_info(dev, &ram);
+       if (ret)
+               return ret;
+
+       debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+       gd->ram_size = ram.size;
+
+       return 0;
+}
+
+int print_cpuinfo(void)
+{
+       void __iomem *chipid;
+       u32 hwcode, swver;
+
+       chipid = ioremap(VER_BASE, VER_SIZE);
+       hwcode = readl(chipid + APHW_CODE);
+       swver = readl(chipid + APSW_VER);
+
+       printf("CPU:   MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
+
+       return 0;
+}

[..]

Quoted 17 lines

new file mode 100644
index 0000000..83ccbba

board/mediatek/mt7629/Makefile new file +3 -0

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y += mt7629_rfb.o

board/mediatek/mt7629/mt7629_rfb.c new file +3 -0

new file mode 100644
index 0000000..08468b5
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.

board/mediatek/mt7629/mt7629_rfb.c line 13

Quoted 10 lines

board/mediatek/mt7629/mt7629_rfb.c new file +10 -0

+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

Do we need these?

Quoted 3 lines

board/mediatek/mt7629/mt7629_rfb.c new file +3 -0

+
+       return 0;
+}

[..]

Quoted 52 lines

include/configs/mt7629.h new file +46 -0

new file mode 100644
index 0000000..9b51e90
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <[email protected]>
+ */
+
+#ifndef __MT7629_H
+#define __MT7629_H
+
+#include <linux/sizes.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_SYS_MAXARGS             8
+#define CONFIG_SYS_BOOTM_LEN           SZ_64M
+#define CONFIG_SYS_CBSIZE              SZ_1K
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE +    \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          SZ_4M
+
+/* Environment */
+#define CONFIG_ENV_SIZE                        SZ_4K
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Defines for SPL */
+#define CONFIG_SPL_STACK               0x106000
+#define CONFIG_SPL_TEXT_BASE           0x201000
+#define CONFIG_SPL_MAX_SIZE            SZ_64K
+#define CONFIG_SPL_MAX_FOOTPRINT       SZ_64K
+#define CONFIG_SPL_PAD_TO              0x10000
+
+#define CONFIG_SPI_ADDR                        0x30000000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_UBOOT_BASE          (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+
+/* SPL -> Uboot */
+#define CONFIG_SYS_UBOOT_START         CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + SZ_2M - \

include/configs/mt7629.h line 56

Quoted 10 lines

include/configs/mt7629.h new file +10 -0

+                                        GENERATED_GBL_DATA_SIZE)
+
+/* UBoot -> Kernel */
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x40000000
+#define CONFIG_LOADADDR                        0x42007f1c
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+/* Serial device */
+#define CONFIG_SYS_NS16550_CLK         40000000
+#define CONFIG_SYS_NS16550_MEM32

Can you use the device tree for this?

Quoted 9 lines

include/configs/mt7629.h new file +6 -1

+#define CONFIG_BAUDRATE                        115200
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE          0x40000000
+
+#endif
--

1.9.1

From: Weijie Gao <[email protected]>

This adds a general board file based on MT7623 SoCs from MediaTek.

As this u-boot is loaded by preloader, there is no low level initializtion codes.

Signed-off-by Weijie Gao <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 arch/arm/mach-mediatek/Kconfig                |  8 +++
 arch/arm/mach-mediatek/Makefile               |  1 +
 arch/arm/mach-mediatek/mt7623/Makefile        |  4 ++
 arch/arm/mach-mediatek/mt7623/init.c          | 54 +++++++++++++++
 arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++++++
 arch/arm/mach-mediatek/mt7623/preloader.h     | 99 +++++++++++++++++++++++++++
 board/mediatek/mt7623/Kconfig                 | 13 ++++
 board/mediatek/mt7623/MAINTAINERS             |  7 ++
 board/mediatek/mt7623/Makefile                |  3 +
 board/mediatek/mt7623/mt7623_rfb.c            | 16 +++++
 configs/mt7623n_bpir2_defconfig               | 53 ++++++++++++++
 include/configs/mt7623.h                      | 61 +++++++++++++++++
 12 files changed, 341 insertions(+)
 create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt7623/init.c

 create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
 create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
 create mode 100644 board/mediatek/mt7623/Kconfig
 create mode 100644 board/mediatek/mt7623/MAINTAINERS
 create mode 100644 board/mediatek/mt7623/Makefile
 create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
 create mode 100644 configs/mt7623n_bpir2_defconfig
 create mode 100644 include/configs/mt7623.h

Hi,

Quoted 26 lines · Ryder Lee

From: Weijie Gao <[email protected]>

This adds a general board file based on MT7623 SoCs from MediaTek.

As this u-boot is loaded by preloader, there is no low level initializtion codes.

Signed-off-by Weijie Gao <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 arch/arm/mach-mediatek/Kconfig                |  8 +++
 arch/arm/mach-mediatek/Makefile               |  1 +
 arch/arm/mach-mediatek/mt7623/Makefile        |  4 ++
 arch/arm/mach-mediatek/mt7623/init.c          | 54 +++++++++++++++
 arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++++++
 arch/arm/mach-mediatek/mt7623/preloader.h     | 99 +++++++++++++++++++++++++++
 board/mediatek/mt7623/Kconfig                 | 13 ++++
 board/mediatek/mt7623/MAINTAINERS             |  7 ++
 board/mediatek/mt7623/Makefile                |  3 +
 board/mediatek/mt7623/mt7623_rfb.c            | 16 +++++
 configs/mt7623n_bpir2_defconfig               | 53 ++++++++++++++
 include/configs/mt7623.h                      | 61 +++++++++++++++++
 12 files changed, 341 insertions(+)
 create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt7623/init.c

Quoted 9 lines

 create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
 create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
 create mode 100644 board/mediatek/mt7623/Kconfig
 create mode 100644 board/mediatek/mt7623/MAINTAINERS
 create mode 100644 board/mediatek/mt7623/Makefile
 create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
 create mode 100644 configs/mt7623n_bpir2_defconfig
 create mode 100644 include/configs/mt7623.h

There is a new SPL handoff and bloblist feature that I hope will land in the next release. Can you please look at using this instead of an SoC-specififc mechanism?

See u-boot-dm/spl-working

This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future.

- Specific SoC part: the group of structures used to hold the hardware configuration for each SoC.

We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it.

Signed-off-by Ryder Lee <[email protected]>

---
 drivers/clk/Makefile              |   1 +
 drivers/clk/mediatek/Makefile     |   6 +
 drivers/clk/mediatek/clk-mt7629.c | 709 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.c    | 492 ++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h    | 153 ++++++++
 5 files changed, 1361 insertions(+)
 create mode 100644 drivers/clk/mediatek/Makefile
 create mode 100644 drivers/clk/mediatek/clk-mt7629.c
 create mode 100644 drivers/clk/mediatek/clk-mtk.c
 create mode 100644 drivers/clk/mediatek/clk-mtk.h

drivers/clk/mediatek/clk-mtk.c new file +11 -0

+
+       priv->tree = tree;
+
+       return 0;
+}
+
+int mtk_clk_gate_init(struct udevice *dev,
+                     const struct mtk_clk_tree *tree,
+                     const struct mtk_gate *gates)
+{
+       struct mtk_cg_priv *priv = dev_get_priv(dev);

Hi Ryder,

Quoted 11 lines · Ryder Lee

This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future.

- Specific SoC part: the group of structures used to hold the hardware configuration for each SoC.

We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it.

Signed-off-by Ryder Lee <[email protected]>

Quoted 11 lines

---
 drivers/clk/Makefile              |   1 +
 drivers/clk/mediatek/Makefile     |   6 +
 drivers/clk/mediatek/clk-mt7629.c | 709 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.c    | 492 ++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h    | 153 ++++++++
 5 files changed, 1361 insertions(+)
 create mode 100644 drivers/clk/mediatek/Makefile
 create mode 100644 drivers/clk/mediatek/clk-mt7629.c
 create mode 100644 drivers/clk/mediatek/clk-mtk.c
 create mode 100644 drivers/clk/mediatek/clk-mtk.h

Looks good except for a few things below.

[..]

drivers/clk/mediatek/clk-mtk.c line 471

Quoted 13 lines

drivers/clk/mediatek/clk-mtk.c new file +13 -0

+const struct clk_ops mtk_clk_gate_ops = {
+       .enable = mtk_clk_gate_enable,
+       .disable = mtk_clk_gate_disable,
+       .get_rate = mtk_clk_gate_get_rate,
+};
+
+int mtk_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree)
+{
+       struct mtk_clk_priv *priv = dev_get_priv(dev);
+
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base)
+               return -ENOENT;

Why do you export these two functions? Devices should be probed in the normal DM way.

Quoted 11 lines

drivers/clk/mediatek/clk-mtk.c new file +11 -0

+
+       priv->tree = tree;
+
+       return 0;
+}
+
+int mtk_clk_gate_init(struct udevice *dev,
+                     const struct mtk_clk_tree *tree,
+                     const struct mtk_gate *gates)
+{
+       struct mtk_cg_priv *priv = dev_get_priv(dev);

drivers/clk/mediatek/clk-mtk.c line 492

Quoted 10 lines

drivers/clk/mediatek/clk-mtk.c new file +10 -0

+
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base)
+               return -ENOENT;
+
+       priv->tree = tree;
+       priv->gates = gates;
+
+       return 0;
+}

[...]

Regards,
Simon

Quoted 30 lines · Simon Glass

Hi Ryder,

Quoted 11 lines · Ryder Lee

This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future.

- Specific SoC part: the group of structures used to hold the hardware configuration for each SoC.

We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it.

Signed-off-by Ryder Lee <[email protected]>

Quoted 11 lines

---
 drivers/clk/Makefile              |   1 +
 drivers/clk/mediatek/Makefile     |   6 +
 drivers/clk/mediatek/clk-mt7629.c | 709 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.c    | 492 ++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h    | 153 ++++++++
 5 files changed, 1361 insertions(+)
 create mode 100644 drivers/clk/mediatek/Makefile
 create mode 100644 drivers/clk/mediatek/clk-mt7629.c
 create mode 100644 drivers/clk/mediatek/clk-mtk.c
 create mode 100644 drivers/clk/mediatek/clk-mtk.h

Looks good except for a few things below.

[..]

Quoted 16 lines

drivers/clk/mediatek/clk-mtk.c line 471

Quoted 13 lines

drivers/clk/mediatek/clk-mtk.c new file +13 -0

+const struct clk_ops mtk_clk_gate_ops = {
+       .enable = mtk_clk_gate_enable,
+       .disable = mtk_clk_gate_disable,
+       .get_rate = mtk_clk_gate_get_rate,
+};
+
+int mtk_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree)
+{
+       struct mtk_clk_priv *priv = dev_get_priv(dev);
+
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base)
+               return -ENOENT;

Why do you export these two functions? Devices should be probed in the normal DM way.

Yes, they are probed in the normal way. These functions are used by several clock blocks and MTK SoCs. so I put the common parts here to keep the code as clean as possible.

This patch adds a driver for MT7623 clock blocks.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/clk/mediatek/Makefile     |   1 +
 drivers/clk/mediatek/clk-mt7623.c | 870 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 871 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt7623.c

This patch adds clock source and clock event for the timer found on the Mediatek SoCs.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/timer/Kconfig     |  7 ++++
 drivers/timer/Makefile    |  1 +
 drivers/timer/mtk_timer.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 93 insertions(+)
 create mode 100644 drivers/timer/mtk_timer.c

This patch adds a common driver for the Mediatek SoC integrated watchdog.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/watchdog/Kconfig   |   8 +++
 drivers/watchdog/Makefile  |   1 +
 drivers/watchdog/mtk_wdt.c | 135 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 144 insertions(+)
 create mode 100644 drivers/watchdog/mtk_wdt.c

This patch adds pinctrl support for MT7629 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. Hence the driver also implements the gpio functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use the same binding and driver, then being a little more abstract could help in the long run.

Signed-off-by Ryder Lee <[email protected]>

---
 arch/arm/include/asm/arch-mediatek/gpio.h     |   9 +
 drivers/pinctrl/Kconfig                       |   1 +
 drivers/pinctrl/Makefile                      |   1 +
 drivers/pinctrl/mediatek/Kconfig              |  11 +
 drivers/pinctrl/mediatek/Makefile             |   6 +
 drivers/pinctrl/mediatek/pinctrl-mt7629.c     | 488 +++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +++++++++
 8 files changed, 1250 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
 create mode 100644 drivers/pinctrl/mediatek/Kconfig
 create mode 100644 drivers/pinctrl/mediatek/Makefile
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h

drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file +7 -0

+int mtk_pinctrl_probe(struct udevice *dev, struct mtk_pinctrl_soc *soc)
+{
+       struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       priv->base = dev_read_addr_ptr(dev);
+       if (priv->base == (void *)FDT_ADDR_T_NONE)

Hi Ryder,

Quoted 27 lines · Ryder Lee

This patch adds pinctrl support for MT7629 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. Hence the driver also implements the gpio functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use the same binding and driver, then being a little more abstract could help in the long run.

Signed-off-by Ryder Lee <[email protected]>

---
 arch/arm/include/asm/arch-mediatek/gpio.h     |   9 +
 drivers/pinctrl/Kconfig                       |   1 +
 drivers/pinctrl/Makefile                      |   1 +
 drivers/pinctrl/mediatek/Kconfig              |  11 +
 drivers/pinctrl/mediatek/Makefile             |   6 +
 drivers/pinctrl/mediatek/pinctrl-mt7629.c     | 488 +++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +++++++++
 8 files changed, 1250 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
 create mode 100644 drivers/pinctrl/mediatek/Kconfig
 create mode 100644 drivers/pinctrl/mediatek/Makefile
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h

[..]

Quoted 11 lines

drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file +11 -0

+int mtk_pinctrl_probe(struct udevice *dev, struct mtk_pinctrl_soc *soc)
+{
+       struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       priv->base = dev_read_addr_ptr(dev);
+       if (priv->base == (void *)FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->soc = soc;
+

drivers/pinctrl/mediatek/pinctrl-mtk-common.c line 552

Quoted 6 lines

drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file +6 -0

+       ret = mtk_gpiochip_register(dev);
+       if (ret)
+               return ret;
+
+       return 0;
+}

How come this function is exported? It should be probed like any other driver.

Hi Simon,

Quoted 44 lines · Simon Glass

Hi Ryder,

Quoted 27 lines · Ryder Lee

This patch adds pinctrl support for MT7629 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. Hence the driver also implements the gpio functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use the same binding and driver, then being a little more abstract could help in the long run.

Signed-off-by Ryder Lee <[email protected]>

---
 arch/arm/include/asm/arch-mediatek/gpio.h     |   9 +
 drivers/pinctrl/Kconfig                       |   1 +
 drivers/pinctrl/Makefile                      |   1 +
 drivers/pinctrl/mediatek/Kconfig              |  11 +
 drivers/pinctrl/mediatek/Makefile             |   6 +
 drivers/pinctrl/mediatek/pinctrl-mt7629.c     | 488 +++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +++++++++
 8 files changed, 1250 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
 create mode 100644 drivers/pinctrl/mediatek/Kconfig
 create mode 100644 drivers/pinctrl/mediatek/Makefile
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h

[..]

Quoted 11 lines

drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file +11 -0

+int mtk_pinctrl_probe(struct udevice *dev, struct mtk_pinctrl_soc *soc)
+{
+       struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       priv->base = dev_read_addr_ptr(dev);
+       if (priv->base == (void *)FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->soc = soc;
+

Quoted 8 lines

drivers/pinctrl/mediatek/pinctrl-mtk-common.c line 552

Quoted 6 lines

drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file +6 -0

+       ret = mtk_gpiochip_register(dev);
+       if (ret)
+               return ret;
+
+       return 0;
+}

How come this function is exported? It should be probed like any other driver.

It makes no difference. We could reuse it for other MTK chips in this way.

In pinctrl-mt7623.c (patch 11/18):

static int mtk_pinctrl_mt7623_probe(struct udevice *dev) {

//common probed function

        mtk_pinctrl_probe(dev, &mt7623_data);

//proprietary operations for the chip....

        mt7623_bonding_disable(dev);
        ....
}

The similar usage is meson_pinctrl_probe() in pinctrl-meson.c

This patch adds pinctrl support for MT7623 SoC. And most of the structures are used to hold the hardware configuration for each pin.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/pinctrl/mediatek/Kconfig              |    4 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt7623.c     | 1284 +++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |    1 +
 4 files changed, 1290 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c

+void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);

Hi Ryder,

Quoted 6 lines · Ryder Lee

This patch adds pinctrl support for MT7623 SoC. And most of the structures are used to hold the hardware configuration for each pin.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

Quoted 7 lines

---
 drivers/pinctrl/mediatek/Kconfig              |    4 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt7623.c     | 1284 +++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |    1 +
 4 files changed, 1290 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c

[..]

Quoted 1 line

+void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);

What is this for? It has no comment and is an exported function. We should not export things from drivers unless there is a good reason.

Regards,
Simon

Quoted 19 lines · Simon Glass

Hi Ryder,

Quoted 13 lines · Ryder Lee

This patch adds pinctrl support for MT7623 SoC. And most of the structures are used to hold the hardware configuration for each pin.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/pinctrl/mediatek/Kconfig              |    4 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt7623.c     | 1284 +++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |    1 +
 4 files changed, 1290 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c

[..]

Quoted 4 lines

Quoted 1 line

+void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);

What is this for? It has no comment and is an exported function. We should not export things from drivers unless there is a good reason.

This is a common 'read-modify-write' helper. I think we could export it in this shared header?

This adds a power domain driver for the Mediatek SCPSYS unit.

The System Control Processor System (SCPSYS) has several power management related tasks in the system. The tasks include thermal measurement, dynamic voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control. The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power domain control.

For now this driver only adds power domain support.

Signed-off-by Ryder Lee <[email protected]>

---
 drivers/power/domain/Kconfig            |   7 +
 drivers/power/domain/Makefile           |   1 +
 drivers/power/domain/mtk-power-domain.c | 326 ++++++++++++++++++++++++++++++++
 3 files changed, 334 insertions(+)
 create mode 100644 drivers/power/domain/mtk-power-domain.c

This adds power domain (scpsys) support for MT7623 SoC.

Signed-off-by Ryder Lee <[email protected]>

---
 drivers/power/domain/mtk-power-domain.c | 80 +++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

This patch adds an extra operation in ns16550.c to suuport MediaTek SoCs as we have a highspeed register which influences the calcualtion of the divisor.

Note that we don't support the baudrate greater than 115200 currently.

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/serial/ns16550.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

This patch adds a DDR3 driver for MT7629 SoC.

Signed-off-by Wu Zou <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

---
 drivers/ram/Makefile               |   1 +
 drivers/ram/mediatek/Makefile      |   7 +
 drivers/ram/mediatek/ddr3-mt7629.c | 766 +++++++++++++++++++++++++++++++++++++
 3 files changed, 774 insertions(+)
 create mode 100644 drivers/ram/mediatek/Makefile
 create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c

drivers/ram/mediatek/ddr3-mt7629.c new file +24 -0

+static int mtk_ddr3_probe(struct udevice *dev)
+{
+       struct mtk_ddr3_priv *priv = dev_get_priv(dev);
+
+       priv->emi = dev_read_addr_index(dev, 0);
+       if (priv->emi == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->ddrphy = dev_read_addr_index(dev, 1);
+       if (priv->ddrphy == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->dramc_ao = dev_read_addr_index(dev, 2);
+       if (priv->dramc_ao == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+#ifdef CONFIG_SPL_BUILD
+       int ret;
+
+       ret = clk_get_by_index(dev, 0, &priv->phy);
+       if (ret)
+               return ret;
+
+       ret = clk_get_by_index(dev, 1, &priv->phy_mux);

Quoted 11 lines · Ryder Lee

This patch adds a DDR3 driver for MT7629 SoC.

Signed-off-by Wu Zou <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

---
 drivers/ram/Makefile               |   1 +
 drivers/ram/mediatek/Makefile      |   7 +
 drivers/ram/mediatek/ddr3-mt7629.c | 766 +++++++++++++++++++++++++++++++++++++
 3 files changed, 774 insertions(+)
 create mode 100644 drivers/ram/mediatek/Makefile
 create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c

Reviewed-by Simon Glass <[email protected]>

Thoughts below.

[..]

drivers/ram/mediatek/ddr3-mt7629.c line 23

Quoted 2 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +2 -0

+#define DDRPHY_PLL1                    0x0000
+#define DDRPHY_PLL2                    0x0004

Why not use a C struct for these registers?

[..]

drivers/ram/mediatek/ddr3-mt7629.c line 590

Quoted 5 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +5 -0

+       writel(0x400, priv->dramc_ao + DRAMC_MRS);
+       writel(0x1d7000, priv->dramc_ao + DRAMC_MRS);
+       writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
+       writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
+       udelay(100);

Are these delays specified in a datasheet? Why did you chose 100? Perhaps add an enum for this value? Is there a way to check for when the hardware is ready, e.g. by reading a registers in a loop?

[..]

Quoted 29 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +29 -0

+static int mtk_ddr3_probe(struct udevice *dev)
+{
+       struct mtk_ddr3_priv *priv = dev_get_priv(dev);
+
+       priv->emi = dev_read_addr_index(dev, 0);
+       if (priv->emi == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->ddrphy = dev_read_addr_index(dev, 1);
+       if (priv->ddrphy == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->dramc_ao = dev_read_addr_index(dev, 2);
+       if (priv->dramc_ao == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+#ifdef CONFIG_SPL_BUILD
+       int ret;
+
+       ret = clk_get_by_index(dev, 0, &priv->phy);
+       if (ret)
+               return ret;
+
+       ret = clk_get_by_index(dev, 1, &priv->phy_mux);
+       if (ret)
+               return ret;
+
+       ret = clk_get_by_index(dev, 2, &priv->mem);
+       if (ret)

drivers/ram/mediatek/ddr3-mt7629.c line 714

Quoted 5 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +5 -0

+               return ret;
+
+       ret = clk_get_by_index(dev, 3, &priv->mem_mux);
+       if (ret)
+               return ret;

Do you have phandles for these clocks? I only worry that it is a bit brittle to have them numbered.

drivers/ram/mediatek/ddr3-mt7629.c line 722

Quoted 8 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +8 -0

+
+       ret = mtk_ddr3_init(dev);
+       if (ret)
+               return ret;
+#endif
+       return 0;
+}
+

Regards,
Simon

Quoted 15 lines · Simon Glass

Quoted 11 lines · Ryder Lee

This patch adds a DDR3 driver for MT7629 SoC.

Signed-off-by Wu Zou <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

---
 drivers/ram/Makefile               |   1 +
 drivers/ram/mediatek/Makefile      |   7 +
 drivers/ram/mediatek/ddr3-mt7629.c | 766 +++++++++++++++++++++++++++++++++++++
 3 files changed, 774 insertions(+)
 create mode 100644 drivers/ram/mediatek/Makefile
 create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c

Reviewed-by Simon Glass <[email protected]>

Quoted 8 lines

Thoughts below.

[..]

drivers/ram/mediatek/ddr3-mt7629.c line 23

Quoted 2 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +2 -0

+#define DDRPHY_PLL1                    0x0000
+#define DDRPHY_PLL2                    0x0004

Why not use a C struct for these registers?

These are copy-n-paste from our SDK. I've considered converting these into C struct but it will take me a while. Just let it be.

But, I could do that if you insist.

Quoted 9 lines

[..]

Quoted 5 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +5 -0

+       writel(0x400, priv->dramc_ao + DRAMC_MRS);
+       writel(0x1d7000, priv->dramc_ao + DRAMC_MRS);
+       writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
+       writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
+       udelay(100);

Quoted 3 lines

Are these delays specified in a datasheet? Why did you chose 100? Perhaps add an enum for this value? Is there a way to check for when the hardware is ready, e.g. by reading a registers in a loop?

Rule of thumb. There is no registers to read here, but I can try to reduce the delay time.

Quoted 32 lines

[..]

Quoted 29 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +29 -0

+static int mtk_ddr3_probe(struct udevice *dev)
+{
+       struct mtk_ddr3_priv *priv = dev_get_priv(dev);
+
+       priv->emi = dev_read_addr_index(dev, 0);
+       if (priv->emi == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->ddrphy = dev_read_addr_index(dev, 1);
+       if (priv->ddrphy == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->dramc_ao = dev_read_addr_index(dev, 2);
+       if (priv->dramc_ao == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+#ifdef CONFIG_SPL_BUILD
+       int ret;
+
+       ret = clk_get_by_index(dev, 0, &priv->phy);
+       if (ret)
+               return ret;
+
+       ret = clk_get_by_index(dev, 1, &priv->phy_mux);
+       if (ret)
+               return ret;
+
+       ret = clk_get_by_index(dev, 2, &priv->mem);
+       if (ret)

Quoted 8 lines

drivers/ram/mediatek/ddr3-mt7629.c line 714

Quoted 5 lines

drivers/ram/mediatek/ddr3-mt7629.c new file +5 -0

+               return ret;
+
+       ret = clk_get_by_index(dev, 3, &priv->mem_mux);
+       if (ret)
+               return ret;

Do you have phandles for these clocks? I only worry that it is a bit brittle to have them numbered.

Yes. I choose clk_get_by_index() here as I stripped the 'clock-names' via CONFIG_OF_SPL_REMOVE_PROPS to reduce the size .

Also I don't understand why we cannot use clk_set_defaults() in pre-relocate state?

From: Weijie Gao <[email protected]>

This patch adds MT7623 host controller driver for accessing SD/MMC.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Weijie Gao <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

Tested-by Matthias Brugger <[email protected]>

---
 drivers/mmc/Kconfig  |    9 +
 drivers/mmc/Makefile |    1 +
 drivers/mmc/mtk-sd.c | 1331 ++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1341 insertions(+)
 create mode 100644 drivers/mmc/mtk-sd.c

drivers/mmc/Kconfig +6 -0

+       help
+         This selects the MediaTek(R) Secure digital and Multimedia card Interface.
+         If you have a machine with a integrated SD/MMC card reader, say Y or M here.
+         This is needed if support for any SD/SDIO/MMC devices is required.
+         If unsure, say N.
+
 endif
 
 config TEGRA124_MMC_DISABLE_EXT_LOOPBACK

drivers/mmc/Makefile +1 -0

index 23c5b0d..801a26d 100644
@@ -65,3 +65,4 @@ obj-$(CONFIG_MMC_SUNXI)                       += sunxi_mmc.o
 obj-$(CONFIG_MMC_UNIPHIER)             += tmio-common.o uniphier-sd.o
 obj-$(CONFIG_RENESAS_SDHI)             += tmio-common.o renesas-sdhi.o
 obj-$(CONFIG_MMC_BCM2835)              += bcm2835_sdhost.o
+obj-$(CONFIG_MMC_MTK)                  += mtk-sd.o

drivers/mmc/mtk-sd.c new file +10 -0

new file mode 100644
index 0000000..5027764
@@ -0,0 +1,1331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek SD/MMC Card Interface driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Weijie Gao <[email protected]>
+ */
+
+#include <clk.h>
+#include <common.h>

drivers/mmc/mtk-sd.c new file +179 -0

+#define   MSDC_CFG_CKSTB               BIT(7)
+#define   MSDC_CFG_PIO                 BIT(3)
+#define   MSDC_CFG_RST                 BIT(2)
+#define   MSDC_CFG_CKPDN               BIT(1)
+#define   MSDC_CFG_MODE                        BIT(0)
+
+#define MSDC_IOCON                     0x04
+#define   MSDC_IOCON_W_DSPL            BIT(8)
+#define   MSDC_IOCON_DSPL              BIT(2)
+#define   MSDC_IOCON_RSPL              BIT(1)
+
+#define MSDC_PS                                0x08
+#define   MSDC_PS_DAT0                 BIT(16)
+#define   MSDC_PS_CDEN                 BIT(0)
+
+#define MSDC_INT                       0x0c
+#define MSDC_INTEN                     0x10
+#define   MSDC_INT_ACMDRDY             BIT(3)
+#define   MSDC_INT_ACMDTMO             BIT(4)
+#define   MSDC_INT_ACMDCRCERR          BIT(5)
+#define   MSDC_INT_CMDRDY              BIT(8)
+#define   MSDC_INT_CMDTMO              BIT(9)
+#define   MSDC_INT_RSPCRCERR           BIT(10)
+#define   MSDC_INT_XFER_COMPL          BIT(12)
+#define   MSDC_INT_DATTMO              BIT(14)
+#define   MSDC_INT_DATCRCERR           BIT(15)
+
+#define MSDC_FIFOCS                    0x14
+#define   MSDC_FIFOCS_CLR              BIT(31)
+#define   MSDC_FIFOCS_TXCNT_M          0xff
+#define   MSDC_FIFOCS_TXCNT_S          16
+#define   MSDC_FIFOCS_RXCNT_M          0xff
+#define   MSDC_FIFOCS_RXCNT_S          0
+
+#define MSDC_TXDATA                    0x18
+#define MSDC_RXDATA                    0x1c
+
+#define SDC_CFG                                0x30
+#define   SDC_CFG_DTOC_M               0xff
+#define   SDC_CFG_DTOC_S               24
+#define   SDC_CFG_SDIOIDE              BIT(20)
+#define   SDC_CFG_SDIO                 BIT(19)
+#define   SDC_CFG_BUSWIDTH_M           0x03
+#define   SDC_CFG_BUSWIDTH_S           16
+
+#define SDC_CMD                                0x34
+#define   SDC_CMD_BLK_LEN_M            0xfff
+#define   SDC_CMD_BLK_LEN_S            16
+#define   SDC_CMD_STOP                 BIT(14)
+#define   SDC_CMD_WR                   BIT(13)
+#define   SDC_CMD_DTYPE_M              0x03
+#define   SDC_CMD_DTYPE_S              11
+#define   SDC_CMD_RSPTYP_M             0x07
+#define   SDC_CMD_RSPTYP_S             7
+#define   SDC_CMD_CMD_M                        0x3f
+#define   SDC_CMD_CMD_S                        0
+
+#define SDC_ARG                                0x38
+
+#define SDC_STS                                0x3c
+#define   SDC_STS_CMDBUSY              BIT(1)
+#define   SDC_STS_SDCBUSY              BIT(0)
+
+#define SDC_RESP0                      0x40
+#define SDC_RESP1                      0x44
+#define SDC_RESP2                      0x48
+#define SDC_RESP3                      0x4c
+
+#define SDC_BLK_NUM                    0x50
+
+#define SDC_ADV_CFG0                   0x64
+#define   SDC_RX_ENHANCE_EN            BIT(20)
+
+#define MSDC_PATCH_BIT                 0xb0
+#define   MSDC_INT_DAT_LATCH_CK_SEL_M  0x07
+#define   MSDC_INT_DAT_LATCH_CK_SEL_S  7
+
+#define MSDC_PATCH_BIT1                        0xb4
+#define   MSDC_PB1_STOP_DLY_M          0x0f
+#define   MSDC_PB1_STOP_DLY_S          8
+
+#define MSDC_PATCH_BIT2                        0xb8
+#define   MSDC_PB2_CRCSTSENSEL_M       0x07
+#define   MSDC_PB2_CRCSTSENSEL_S       29
+#define   MSDC_PB2_CFGCRCSTS           BIT(28)
+#define   MSDC_PB2_RESPSTSENSEL_M      0x07
+#define   MSDC_PB2_RESPSTSENSEL_S      16
+#define   MSDC_PB2_CFGRESP             BIT(15)
+#define   MSDC_PB2_RESPWAIT_M          0x03
+#define   MSDC_PB2_RESPWAIT_S          2
+
+#define MSDC_PAD_TUNE                  0xec
+#define   MSDC_PAD_TUNE_CMDRRDLY_M     0x1f
+#define   MSDC_PAD_TUNE_CMDRRDLY_S     22
+#define   MSDC_PAD_TUNE_CMD_SEL                BIT(21)
+#define   MSDC_PAD_TUNE_CMDRDLY_M      0x1f
+#define   MSDC_PAD_TUNE_CMDRDLY_S      16
+#define   MSDC_PAD_TUNE_RXDLYSEL       BIT(15)
+#define   MSDC_PAD_TUNE_RD_SEL         BIT(13)
+#define   MSDC_PAD_TUNE_DATRRDLY_M     0x1f
+#define   MSDC_PAD_TUNE_DATRRDLY_S     8
+#define   MSDC_PAD_TUNE_DATWRDLY_M     0x1f
+#define   MSDC_PAD_TUNE_DATWRDLY_S     0
+
+#define MSDC_PAD_TUNE0                 0xf0
+
+#define PAD_DS_TUNE                    0x188
+
+#define EMMC50_CFG0                    0x208
+#define   EMMC50_CFG_CFCSTS_SEL                BIT(4)
+
+#define SDC_FIFO_CFG                   0x228
+#define   SDC_FIFO_CFG_WRVALIDSEL      BIT(24)
+#define   SDC_FIFO_CFG_RDVALIDSEL      BIT(25)
+
+/* SDC_CFG_BUSWIDTH */
+#define MSDC_BUS_1BITS                 0x0
+#define MSDC_BUS_4BITS                 0x1
+#define MSDC_BUS_8BITS                 0x2
+
+#define MSDC_FIFO_SIZE                 128
+
+#define PAD_DELAY_MAX                  32
+
+#define CMD_INTS_MASK  \
+       (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
+
+#define DATA_INTS_MASK \
+       (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
+
+struct msdc_compatible {
+       u8 clk_div_bits;
+       bool pad_tune0;
+       bool async_fifo;
+       bool data_tune;
+       bool busy_check;
+       bool stop_clk_fix;
+       bool enhance_rx;
+};
+
+struct msdc_delay_phase {
+       u8 maxlen;
+       u8 start;
+       u8 final_phase;
+};
+
+struct msdc_plat {
+       struct mmc_config cfg;
+       struct mmc mmc;
+};
+
+struct msdc_tune_para {
+       u32 iocon;
+       u32 pad_tune;
+};
+
+struct msdc_host {
+       void __iomem *base;
+       struct mmc *mmc;
+
+       struct msdc_compatible *dev_comp;
+
+       struct clk src_clk;
+       struct clk h_clk;
+
+       u32 mclk;
+       u32 src_clk_freq;
+       u32 sclk;
+
+       u32 timeout_ns;
+       u32 timeout_clks;
+
+       u32 hs400_ds_delay;
+       u32 hs200_cmd_int_delay;
+       u32 hs200_write_int_delay;
+       u32 latch_ck;
+       u32 r_smpl;
+       bool hs400_mode;
+

drivers/mmc/mtk-sd.c new file +113 -0

+};
+
+static void msdc_reset_hw(struct msdc_host *host)
+{
+       u32 reg;
+
+       setbits_le32(host->base + MSDC_CFG, MSDC_CFG_RST);
+
+       readl_poll_timeout(host->base + MSDC_CFG, reg,
+                          !(reg & MSDC_CFG_RST), 1000000);
+}
+
+static void msdc_fifo_clr(struct msdc_host *host)
+{
+       u32 reg;
+
+       setbits_le32(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
+
+       readl_poll_timeout(host->base + MSDC_FIFOCS, reg,
+                          !(reg & MSDC_FIFOCS_CLR), 1000000);
+}
+
+static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
+{
+       return (readl(host->base + MSDC_FIFOCS) >> MSDC_FIFOCS_RXCNT_S) &
+               MSDC_FIFOCS_RXCNT_M;
+}
+
+static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
+{
+       return (readl(host->base + MSDC_FIFOCS) >> MSDC_FIFOCS_TXCNT_S) &
+               MSDC_FIFOCS_TXCNT_M;
+}
+
+static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
+{
+       u32 resp;
+
+       switch (cmd->resp_type) {
+               /* Actually, R1, R5, R6, R7 are the same */
+       case MMC_RSP_R1:
+               resp = 0x1;
+               break;
+       case MMC_RSP_R1b:
+               resp = 0x7;
+               break;
+       case MMC_RSP_R2:
+               resp = 0x2;
+               break;
+       case MMC_RSP_R3:
+               resp = 0x3;
+               break;
+       case MMC_RSP_NONE:
+       default:
+               resp = 0x0;
+               break;
+       }
+
+       return resp;
+}
+
+static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
+                                   struct mmc_cmd *cmd,
+                                   struct mmc_data *data)
+{
+       u32 opcode = cmd->cmdidx;
+       u32 resp_type = msdc_cmd_find_resp(host, cmd);
+       uint blocksize = 0;
+       u32 dtype = 0;
+       u32 rawcmd = 0;
+
+       switch (opcode) {
+       case MMC_CMD_WRITE_MULTIPLE_BLOCK:
+       case MMC_CMD_READ_MULTIPLE_BLOCK:
+               dtype = 2;
+               break;
+       case MMC_CMD_WRITE_SINGLE_BLOCK:
+       case MMC_CMD_READ_SINGLE_BLOCK:
+       case SD_CMD_APP_SEND_SCR:
+               dtype = 1;
+               break;
+       case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
+       case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
+       case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
+               if (data)
+                       dtype = 1;
+       }
+
+       if (data) {
+               if (data->flags == MMC_DATA_WRITE)
+                       rawcmd |= SDC_CMD_WR;
+
+               if (data->blocks > 1)
+                       dtype = 2;
+
+               blocksize = data->blocksize;
+       }
+
+       rawcmd |= ((opcode & SDC_CMD_CMD_M) << SDC_CMD_CMD_S) |
+               ((resp_type & SDC_CMD_RSPTYP_M) << SDC_CMD_RSPTYP_S) |
+               ((blocksize & SDC_CMD_BLK_LEN_M) << SDC_CMD_BLK_LEN_S) |
+               ((dtype & SDC_CMD_DTYPE_M) << SDC_CMD_DTYPE_S);
+
+       if (opcode == MMC_CMD_STOP_TRANSMISSION)
+               rawcmd |= SDC_CMD_STOP;
+
+       return rawcmd;
+}
+
+static int msdc_cmd_done(struct msdc_host *host, int events,
+                        struct mmc_cmd *cmd)
+{
+       u32 *rsp = cmd->response;

drivers/mmc/mtk-sd.c new file +7 -0

+static int msdc_drv_probe(struct udevice *dev)
+{
+       struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+       struct msdc_plat *plat = dev_get_platdata(dev);
+       struct msdc_host *host = dev_get_priv(dev);
+       struct mmc_config *cfg = &plat->cfg;
+       int ret;