drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index
Subsystems (3)
PATCH 1/7 drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index
This is a preparation work to make reserved doorbell index per device, instead of using a global macro definition. By doing this, we can easily change doorbell layout for future ASICs while not affecting ASICs in production.
Change-Id If08e2bc9d0749748ed4083ba4eb32a4698763085
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 +++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)
drivers/gpu/drm/amd/amdgpu/amdgpu.h +50 -0
@@ -813,6 +813,55 @@ struct amd_powerplay {uint32_t pp_feature; }; +/* Reserved doorbells for amdgpu (including multimedia). +* KFD can use all the rest in the 2M doorbell bar. +* For asic before vega10, doorbell is 32-bit, so the +* index/offset is in dword. For vega10 and after, doorbell +* can be 64-bit, so the index defined is in qword. +*/ +struct amdgpu_doorbell_index { +uint32_t kiq; +uint32_t mec_ring0; +uint32_t mec_ring1; +uint32_t mec_ring2; +uint32_t mec_ring3; +uint32_t mec_ring4; +uint32_t mec_ring5; +uint32_t mec_ring6; +uint32_t mec_ring7; +uint32_t userqueue_start; +uint32_t userqueue_end; +uint32_t gfx_ring0; +uint32_t sdma_engine0; +uint32_t sdma_engine1; +uint32_t sdma_engine2; +uint32_t sdma_engine3; +uint32_t sdma_engine4; +uint32_t sdma_engine5; +uint32_t sdma_engine6; +uint32_t sdma_engine7; +uint32_t ih; +union { +struct { +uint32_t vcn_ring0_1; +uint32_t vcn_ring2_3; +uint32_t vcn_ring4_5; +uint32_t vcn_ring6_7; + } vcn; +struct { +uint32_t uvd_ring0_1; +uint32_t uvd_ring2_3; +uint32_t uvd_ring4_5; +uint32_t uvd_ring6_7; +uint32_t vce_ring0_1; +uint32_t vce_ring2_3; +uint32_t vce_ring4_5; +uint32_t vce_ring6_7; + } uvd_vce; + }; +uint32_t max_assignment; +}; +#define AMDGPU_RESET_MAGIC_NUM 64struct amdgpu_device {struct device *dev;
@@ -1026,6 +1075,7 @@ struct amdgpu_device {unsigned long last_mm_index;bool in_gpu_reset;struct mutex lock_reset; +struct amdgpu_doorbell_index doorbell_index; };static inline struct amdgpu_device *amdgpu_ttm_adev (struct ttm_bo_device *bdev)
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PATCH 2/7 drm/amdgpu: Vega10 doorbell index initialization
v2: Use enum definition instead of hardcoded value
Change-Id Ib72058337f0aa53adfc6c6aae5341a7cd665111a
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+)
drivers/gpu/drm/amd/amdgpu/soc15.h +1 -0
@@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,int vega10_reg_base_init (struct amdgpu_device *adev);int vega20_reg_base_init (struct amdgpu_device *adev); +void vega10_doorbell_index_init (struct amdgpu_device *adev);#endif
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c +28 -0
@@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)return 0 ; } +void vega10_doorbell_index_init (struct amdgpu_device *adev) +{ + adev->doorbell_index.kiq =AMDGPU_DOORBELL64_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_DOORBELL64_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_DOORBELL64_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_DOORBELL64_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_DOORBELL64_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_DOORBELL64_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_DOORBELL64_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_DOORBELL64_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_DOORBELL64_MEC_RING7 ; + adev->doorbell_index.userqueue_start =AMDGPU_DOORBELL64_USERQUEUE_START ; + adev->doorbell_index.userqueue_end =AMDGPU_DOORBELL64_USERQUEUE_END ; + adev->doorbell_index.gfx_ring0 =AMDGPU_DOORBELL64_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1; + adev->doorbell_index.ih =AMDGPU_DOORBELL64_IH ; + adev->doorbell_index.uvd_vce.uvd_ring0_1 =AMDGPU_DOORBELL64_UVD_RING0_1 ; + adev->doorbell_index.uvd_vce.uvd_ring2_3 =AMDGPU_DOORBELL64_UVD_RING2_3 ; + adev->doorbell_index.uvd_vce.uvd_ring4_5 =AMDGPU_DOORBELL64_UVD_RING4_5 ; + adev->doorbell_index.uvd_vce.uvd_ring6_7 =AMDGPU_DOORBELL64_UVD_RING6_7 ; + adev->doorbell_index.uvd_vce.vce_ring0_1 =AMDGPU_DOORBELL64_VCE_RING0_1 ; + adev->doorbell_index.uvd_vce.vce_ring2_3 =AMDGPU_DOORBELL64_VCE_RING2_3 ; + adev->doorbell_index.uvd_vce.vce_ring4_5 =AMDGPU_DOORBELL64_VCE_RING4_5 ; + adev->doorbell_index.uvd_vce.vce_ring6_7 =AMDGPU_DOORBELL64_VCE_RING6_7 ; +/* In unit of dword doorbell */ + adev->doorbell_index.max_assignment =AMDGPU_DOORBELL64_MAX_ASSIGNMENT <<1 ; +}
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Alex Deucher
Reviewed-byRe: [PATCH 2/7] drm/amdgpu: Vega10 doorbell index initialization
Quoted 7 lines · Oak Zeng
v2: Use enum definition instead of hardcoded value
Change-Id Ib72058337f0aa53adfc6c6aae5341a7cd665111aSigned-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Reviewed-by Alex Deucher <[email protected]>
Quoted 55 lines
--- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+)drivers/gpu/drm/amd/amdgpu/soc15.h +1
-0@@ -58,4 +58,5 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,int vega10_reg_base_init (struct amdgpu_device *adev);int vega20_reg_base_init (struct amdgpu_device *adev); +void vega10_doorbell_index_init (struct amdgpu_device *adev);#endif drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c +28
-1@@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)return 0 ; } +void vega10_doorbell_index_init (struct amdgpu_device *adev) +{ + adev->doorbell_index.kiq =AMDGPU_DOORBELL64_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_DOORBELL64_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_DOORBELL64_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_DOORBELL64_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_DOORBELL64_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_DOORBELL64_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_DOORBELL64_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_DOORBELL64_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_DOORBELL64_MEC_RING7 ; + adev->doorbell_index.userqueue_start =AMDGPU_DOORBELL64_USERQUEUE_START ; + adev->doorbell_index.userqueue_end =AMDGPU_DOORBELL64_USERQUEUE_END ; + adev->doorbell_index.gfx_ring0 =AMDGPU_DOORBELL64_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1; + adev->doorbell_index.ih =AMDGPU_DOORBELL64_IH ; + adev->doorbell_index.uvd_vce.uvd_ring0_1 =AMDGPU_DOORBELL64_UVD_RING0_1 ; + adev->doorbell_index.uvd_vce.uvd_ring2_3 =AMDGPU_DOORBELL64_UVD_RING2_3 ; + adev->doorbell_index.uvd_vce.uvd_ring4_5 =AMDGPU_DOORBELL64_UVD_RING4_5 ; + adev->doorbell_index.uvd_vce.uvd_ring6_7 =AMDGPU_DOORBELL64_UVD_RING6_7 ; + adev->doorbell_index.uvd_vce.vce_ring0_1 =AMDGPU_DOORBELL64_VCE_RING0_1 ; + adev->doorbell_index.uvd_vce.vce_ring2_3 =AMDGPU_DOORBELL64_VCE_RING2_3 ; + adev->doorbell_index.uvd_vce.vce_ring4_5 =AMDGPU_DOORBELL64_VCE_RING4_5 ; + adev->doorbell_index.uvd_vce.vce_ring6_7 =AMDGPU_DOORBELL64_VCE_RING6_7 ; +/* In unit of dword doorbell */ + adev->doorbell_index.max_assignment =AMDGPU_DOORBELL64_MAX_ASSIGNMENT <<1 ; +} --2.7.4
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PATCH 3/7 drm/amdgpu: Vega12 doorbell index initialization
In reply to a message not in the archivev2: Changed file name for consistency
Change-Id Ib2c570224321bb7002d2ed01f43ac70203e86f88
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c | 54 ++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c
drivers/gpu/drm/amd/amdgpu/Makefile +1 -1
@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ - vega20_reg_init.o nbio_v7_4.o + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o # add DF block amdgpu-y += \
drivers/gpu/drm/amd/amdgpu/soc15.h +1 -0
@@ -59,4 +59,5 @@ int vega10_reg_base_init(struct amdgpu_device *adev);int vega20_reg_base_init (struct amdgpu_device *adev);void vega10_doorbell_index_init (struct amdgpu_device *adev); +void vega12_doorbell_index_init (struct amdgpu_device *adev);#endif
drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c new file +54 -0
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Re: [PATCH 3/7] drm/amdgpu: Vega12 doorbell index initialization
Quoted 7 lines · Oak Zeng
v2: Changed file name for consistency
Change-Id Ib2c570224321bb7002d2ed01f43ac70203e86f88Signed-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Just drop this patch and use the vega10 definition for vega12 and raven.
Alex
Quoted 93 lines
--- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c | 54 ++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vega12_reg_init.cdrivers/gpu/drm/amd/amdgpu/Makefile +1
-1@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ - vega20_reg_init.o nbio_v7_4.o + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o # add DF block amdgpu-y += \drivers/gpu/drm/amd/amdgpu/soc15.h +1
-0@@ -59,4 +59,5 @@ int vega10_reg_base_init(struct amdgpu_device *adev);int vega20_reg_base_init (struct amdgpu_device *adev);void vega10_doorbell_index_init (struct amdgpu_device *adev); +void vega12_doorbell_index_init (struct amdgpu_device *adev);#endif drivers/gpu/drm/amd/amdgpu/vega12_reg_init.c new file +54
-1@@ -0,0 +1,54 @@ +/* +* Copyright 2018 Advanced Micro Devices, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +*/ + +#include "amdgpu.h" + +void vega12_doorbell_index_init (struct amdgpu_device *adev) +{ + adev->doorbell_index.kiq =AMDGPU_DOORBELL64_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_DOORBELL64_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_DOORBELL64_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_DOORBELL64_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_DOORBELL64_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_DOORBELL64_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_DOORBELL64_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_DOORBELL64_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_DOORBELL64_MEC_RING7 ; + adev->doorbell_index.userqueue_start =AMDGPU_DOORBELL64_USERQUEUE_START ; + adev->doorbell_index.userqueue_end =AMDGPU_DOORBELL64_USERQUEUE_END ; + adev->doorbell_index.gfx_ring0 =AMDGPU_DOORBELL64_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1; + adev->doorbell_index.ih =AMDGPU_DOORBELL64_IH ; + adev->doorbell_index.uvd_vce.uvd_ring0_1 =AMDGPU_DOORBELL64_UVD_RING0_1 ; + adev->doorbell_index.uvd_vce.uvd_ring2_3 =AMDGPU_DOORBELL64_UVD_RING2_3 ; + adev->doorbell_index.uvd_vce.uvd_ring4_5 =AMDGPU_DOORBELL64_UVD_RING4_5 ; + adev->doorbell_index.uvd_vce.uvd_ring6_7 =AMDGPU_DOORBELL64_UVD_RING6_7 ; + adev->doorbell_index.uvd_vce.vce_ring0_1 =AMDGPU_DOORBELL64_VCE_RING0_1 ; + adev->doorbell_index.uvd_vce.vce_ring2_3 =AMDGPU_DOORBELL64_VCE_RING2_3 ; + adev->doorbell_index.uvd_vce.vce_ring4_5 =AMDGPU_DOORBELL64_VCE_RING4_5 ; + adev->doorbell_index.uvd_vce.vce_ring6_7 =AMDGPU_DOORBELL64_VCE_RING6_7 ; +/* In unit of dword doorbell */ + adev->doorbell_index.max_assignment =AMDGPU_DOORBELL64_MAX_ASSIGNMENT <<1 ; +} + --2.7.4
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PATCH 4/7 drm/amdgpu: Doorbell index initialization for ASICs before vega10
In reply to a message not in the archivev2: Use enum definition instead of hardcoded number
Change-Id Id64eb98f5b1c24b51eb2fd5a083086fc3515813d
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/vi.h | 2 +- drivers/gpu/drm/amd/amdgpu/vi_reg_init.c | 43 ++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vi_reg_init.c
drivers/gpu/drm/amd/amdgpu/Makefile +1 -1
@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ - vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o vi_reg_init.o # add DF block amdgpu-y += \
drivers/gpu/drm/amd/amdgpu/vi.h +1 -1
@@ -29,5 +29,5 @@void vi_srbm_select (struct amdgpu_device *adev,u32 me,u32 pipe,u32 queue,u32 vmid);int vi_set_ip_blocks (struct amdgpu_device *adev); - +void vi_doorbell_index_init (struct amdgpu_device *adev);#endif
drivers/gpu/drm/amd/amdgpu/vi_reg_init.c new file +43 -0
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Re: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
Quoted 7 lines · Oak Zeng
v2: Use enum definition instead of hardcoded number
Change-Id Id64eb98f5b1c24b51eb2fd5a083086fc3515813dSigned-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Since this covers cik and vi, maybe call it cik_doorbell_index_init() or legacy_doorbell_index_init()?
Alex
Quoted 83 lines
--- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/vi.h | 2 +- drivers/gpu/drm/amd/amdgpu/vi_reg_init.c | 43 ++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vi_reg_init.cdrivers/gpu/drm/amd/amdgpu/Makefile +1
-1@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ - vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o vi_reg_init.o # add DF block amdgpu-y += \drivers/gpu/drm/amd/amdgpu/vi.h +1
-1@@ -29,5 +29,5 @@void vi_srbm_select (struct amdgpu_device *adev,u32 me,u32 pipe,u32 queue,u32 vmid);int vi_set_ip_blocks (struct amdgpu_device *adev); - +void vi_doorbell_index_init (struct amdgpu_device *adev);#endif drivers/gpu/drm/amd/amdgpu/vi_reg_init.c new file +43
-1@@ -0,0 +1,43 @@ +/* +* Copyright 2018 Advanced Micro Devices, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +*/ + +#include "amdgpu.h" + +void vi_doorbell_index_init (struct amdgpu_device *adev) +{ + adev->doorbell_index.kiq =AMDGPU_DOORBELL_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_DOORBELL_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_DOORBELL_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_DOORBELL_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_DOORBELL_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_DOORBELL_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_DOORBELL_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_DOORBELL_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_DOORBELL_MEC_RING7 ; + adev->doorbell_index.gfx_ring0 =AMDGPU_DOORBELL_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.ih =AMDGPU_DOORBELL_IH ; + adev->doorbell_index.max_assignment =AMDGPU_DOORBELL_MAX_ASSIGNMENT ; +} + --2.7.4
Quoted 4 lines
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RE: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
Ok, I can change it legacy_doorbell_index_init(). I will keep this function in vi.c. The reason I don't want to put it in cik.c is cik.c is only compiled optionally.
Another thing I want to know is, my understanding is si doesn't use doorbell, does it?
thanks,
Oak
-----Original Message-----
From: Alex Deucher <[email protected]>
Sent: Sunday, November 25, 2018 1:46 PM
To: Zeng, Oak <[email protected]>
Subject: Fwd: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
---------- Forwarded message ---------
From: Alex Deucher <[email protected]>
Date: Wed, Nov 21, 2018 at 5:40 PM
Subject: Re: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
To: <[email protected]>
Cc: amd-gfx list <[email protected]>, Oak Zeng <[email protected]>
Quoted 7 lines · Oak Zeng
v2: Use enum definition instead of hardcoded number
Change-Id Id64eb98f5b1c24b51eb2fd5a083086fc3515813dSigned-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Since this covers cik and vi, maybe call it cik_doorbell_index_init() or legacy_doorbell_index_init()?
Alex
Quoted 98 lines
--- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/vi.h | 2 +- drivers/gpu/drm/amd/amdgpu/vi_reg_init.c | 43 ++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 2 deletions(-) create mode 100644
drivers/gpu/drm/amd/amdgpu/vi_reg_init.cdrivers/gpu/drm/amd/amdgpu/Makefile +0
-0@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.ogfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \drivers/gpu/drm/amd/amdgpu/Makefile +1
-1- vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o vi_reg_init.o # add DF block amdgpu-y += \(quoted diff) +0
-0
b/drivers/gpu/drm/amd/amdgpu/vi.hindex 0429fe3..abcb52e 100644drivers/gpu/drm/amd/amdgpu/vi.h +1
-1@@ -29,5 +29,5 @@void vi_srbm_select (struct amdgpu_device *adev,u32 me,u32 pipe,u32 queue,u32 vmid);int vi_set_ip_blocks (struct amdgpu_device *adev); - +void vi_doorbell_index_init (struct amdgpu_device *adev);#endif drivers/gpu/drm/amd/amdgpu/vi_reg_init.c new file +54
-1@@ -0,0 +1,43 @@ +/* +* Copyright 2018 Advanced Micro Devices, Inc. +* +* Permission is hereby granted, free of charge, to any person +obtaining a +* copy of this software and associated documentation files (the +"Software"), +* to deal in the Software without restriction, including without +limitation +* the rights to use, copy, modify, merge, publish, distribute, +sublicense, +* and/or sell copies of the Software, and to permit persons to whom +the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be +included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT +SHALL +* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, +DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +OR +* OTHER DEALINGS IN THE SOFTWARE. +* +*/ + +#include "amdgpu.h" + +void vi_doorbell_index_init (struct amdgpu_device *adev) { + adev->doorbell_index.kiq =AMDGPU_DOORBELL_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_DOORBELL_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_DOORBELL_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_DOORBELL_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_DOORBELL_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_DOORBELL_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_DOORBELL_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_DOORBELL_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_DOORBELL_MEC_RING7 ; + adev->doorbell_index.gfx_ring0 =AMDGPU_DOORBELL_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.ih =AMDGPU_DOORBELL_IH ; + adev->doorbell_index.max_assignment = +AMDGPU_DOORBELL_MAX_ASSIGNMENT ; } + --2.7.4
Quoted 4 lines
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Re: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
Correct. SI does not use doorbells.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Zeng, Oak <[email protected]>
Sent: Monday, November 26, 2018 12:20:10 PM
To: Alex Deucher
Cc: [email protected]
Subject: RE: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
Ok, I can change it legacy_doorbell_index_init(). I will keep this function in vi.c. The reason I don't want to put it in cik.c is cik.c is only compiled optionally.
Another thing I want to know is, my understanding is si doesn't use doorbell, does it?
thanks,
Oak
-----Original Message-----
From: Alex Deucher <[email protected]>
Sent: Sunday, November 25, 2018 1:46 PM
To: Zeng, Oak <[email protected]>
Subject: Fwd: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
---------- Forwarded message ---------
From: Alex Deucher <[email protected]>
Date: Wed, Nov 21, 2018 at 5:40 PM
Subject: Re: [PATCH 4/7] drm/amdgpu: Doorbell index initialization for ASICs before vega10
To: <[email protected]>
Cc: amd-gfx list <[email protected]>, Oak Zeng <[email protected]>
Quoted 7 lines · Oak Zeng
v2: Use enum definition instead of hardcoded number
Change-Id Id64eb98f5b1c24b51eb2fd5a083086fc3515813dSigned-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Since this covers cik and vi, maybe call it cik_doorbell_index_init() or legacy_doorbell_index_init()?
Alex
Quoted 98 lines
--- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/vi.h | 2 +- drivers/gpu/drm/amd/amdgpu/vi_reg_init.c | 43 ++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 2 deletions(-) create mode 100644
drivers/gpu/drm/amd/amdgpu/vi_reg_init.cdrivers/gpu/drm/amd/amdgpu/Makefile +0
-0@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.ogfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \drivers/gpu/drm/amd/amdgpu/Makefile +1
-1- vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o + vega20_reg_init.o nbio_v7_4.o vega12_reg_init.o vi_reg_init.o # add DF block amdgpu-y += \(quoted diff) +0
-0
b/drivers/gpu/drm/amd/amdgpu/vi.hindex 0429fe3..abcb52e 100644drivers/gpu/drm/amd/amdgpu/vi.h +1
-1@@ -29,5 +29,5 @@void vi_srbm_select (struct amdgpu_device *adev,u32 me,u32 pipe,u32 queue,u32 vmid);int vi_set_ip_blocks (struct amdgpu_device *adev); - +void vi_doorbell_index_init (struct amdgpu_device *adev);#endif drivers/gpu/drm/amd/amdgpu/vi_reg_init.c new file +54
-1@@ -0,0 +1,43 @@ +/* +* Copyright 2018 Advanced Micro Devices, Inc. +* +* Permission is hereby granted, free of charge, to any person +obtaining a +* copy of this software and associated documentation files (the +"Software"), +* to deal in the Software without restriction, including without +limitation +* the rights to use, copy, modify, merge, publish, distribute, +sublicense, +* and/or sell copies of the Software, and to permit persons to whom +the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be +included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT +SHALL +* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, +DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +OR +* OTHER DEALINGS IN THE SOFTWARE. +* +*/ + +#include "amdgpu.h" + +void vi_doorbell_index_init (struct amdgpu_device *adev) { + adev->doorbell_index.kiq =AMDGPU_DOORBELL_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_DOORBELL_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_DOORBELL_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_DOORBELL_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_DOORBELL_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_DOORBELL_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_DOORBELL_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_DOORBELL_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_DOORBELL_MEC_RING7 ; + adev->doorbell_index.gfx_ring0 =AMDGPU_DOORBELL_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.ih =AMDGPU_DOORBELL_IH ; + adev->doorbell_index.max_assignment = +AMDGPU_DOORBELL_MAX_ASSIGNMENT ; } + --2.7.4
Quoted 4 lines
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PATCH 5/7 drm/amdgpu: Call doorbell index init on device initialization
In reply to a message not in the archiveChange-Id I2f004bbbe2565035460686f4fc16e86b77a2a9b5
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ 1 file changed, 7 insertions(+)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +7 -0
@@ -513,6 +513,13 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)*/ static int amdgpu_device_doorbell_init (struct amdgpu_device *adev) { +if (adev->asic_type <CHIP_VEGA10 ) +vi_doorbell_index_init (adev); +else if (adev->asic_type ==CHIP_VEGA10 ) +vega10_doorbell_index_init (adev); +else +vega12_doorbell_index_init (adev); +/* No doorbell on SI hardware generation */ if (adev->asic_type <CHIP_BONAIRE ) { adev->doorbell.base =0 ;
Signature · 6 lines
2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 5/7] drm/amdgpu: Call doorbell index init on device initialization
Quoted 5 lines · Oak Zeng
Change-Id I2f004bbbe2565035460686f4fc16e86b77a2a9b5Signed-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
I think it would be cleaner to call this in the soc files directly (cik.c, vi.c, soc15.c in the set_ip_blocks() functions). It keeps the asic specific bits out of amdgpu_device.c.
Quoted 25 lines
--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ 1 file changed, 7 insertions(+)drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +7
-1@@ -513,6 +513,13 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)*/ static int amdgpu_device_doorbell_init (struct amdgpu_device *adev) { +if (adev->asic_type <CHIP_VEGA10 ) +vi_doorbell_index_init (adev); +else if (adev->asic_type ==CHIP_VEGA10 ) +vega10_doorbell_index_init (adev); +else +vega12_doorbell_index_init (adev); +/* No doorbell on SI hardware generation */ if (adev->asic_type <CHIP_BONAIRE ) { adev->doorbell.base =0 ; --2.7.4
Quoted 4 lines
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PATCH 6/7 drm/amdgpu: Use asic specific doorbell index instead of macro definition
In reply to a message not in the archiveChange-Id Iffff84475efcfb482c474fccb133010abb5df5f4
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 ++++++++------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +++++++++---------------- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- 12 files changed, 36 insertions(+), 54 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +8 -19
@@ -181,25 +181,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)* process in case of 64-bit doorbells so we * can use each doorbell assignment twice. */ -if (adev->asic_type ==CHIP_VEGA10 ) { - gpu_resources.sdma_doorbell[0 ][i] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >>1 ); - gpu_resources.sdma_doorbell[0 ][i+1 ] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 +0x200 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i+1 ] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 +0x200 + (i >>1 ); - }else { - gpu_resources.sdma_doorbell[0 ][i] = - AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >>1 ); - gpu_resources.sdma_doorbell[0 ][i+1 ] = - AMDGPU_DOORBELL64_sDMA_ENGINE0 +0x200 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i] = - AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i+1 ] = - AMDGPU_DOORBELL64_sDMA_ENGINE1 +0x200 + (i >>1 ); - } + gpu_resources.sdma_doorbell[0 ][i] = + adev->doorbell_index.sdma_engine0 + (i >>1 ); + gpu_resources.sdma_doorbell[0 ][i+1 ] = + adev->doorbell_index.sdma_engine0 +0x200 + (i >>1 ); + gpu_resources.sdma_doorbell[1 ][i] = + adev->doorbell_index.sdma_engine1 + (i >>1 ); + gpu_resources.sdma_doorbell[1 ][i+1 ] = + adev->doorbell_index.sdma_engine1 +0x200 + (i >>1 ); }/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for * SDMA, IH and VCN. So don't use them for the CP.
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +1 -1
@@ -537,7 +537,7 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) adev->doorbell.size =pci_resource_len (adev->pdev,2 ); adev->doorbell.num_doorbells =min_t (u32, adev->doorbell.size /sizeof (u32), -AMDGPU_DOORBELL_MAX_ASSIGNMENT +1 ); + adev->doorbell_index.max_assignment+1 );if (adev->doorbell.num_doorbells ==0 )return -EINVAL ;
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +1 -1
@@ -250,7 +250,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, ring->adev =NULL ; ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_KIQ ; + ring->doorbell_index = adev->doorbell_index.kiq; r =amdgpu_gfx_kiq_acquire (adev, ring);if (r)
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +1 -1
@@ -4363,7 +4363,7 @@ static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_MEC_RING0 + ring_id; + ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;sprintf (ring->name,"comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue); irq_type =AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +5 -5
@@ -1890,7 +1890,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_MEC_RING0 + ring_id; + ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring_id *GFX8_MEC_HPD_SIZE );sprintf (ring->name,"comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue);
@@ -2001,7 +2001,7 @@ static int gfx_v8_0_sw_init(void *handle)/* no gfx doorbells on iceland */ if (adev->asic_type !=CHIP_TOPAZ ) { ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_GFX_RING0 ; + ring->doorbell_index = adev->doorbell_index.gfx_ring0; } r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
@@ -4215,7 +4215,7 @@ static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu tmp =REG_SET_FIELD (0 ,CP_RB_DOORBELL_RANGE_LOWER ,DOORBELL_RANGE_LOWER , -AMDGPU_DOORBELL_GFX_RING0 ); + adev->doorbell_index.gfx_ring0);WREG32 (mmCP_RB_DOORBELL_RANGE_LOWER, tmp); WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
@@ -4644,8 +4644,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)static void gfx_v8_0_set_mec_doorbell_range (struct amdgpu_device *adev) {if (adev->asic_type >CHIP_TONGA ) { -WREG32 (mmCP_MEC_DOORBELL_RANGE_LOWER,AMDGPU_DOORBELL_KIQ <<2 ); -WREG32 (mmCP_MEC_DOORBELL_RANGE_UPPER,AMDGPU_DOORBELL_MEC_RING7 <<2 ); +WREG32 (mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq <<2 ); +WREG32 (mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 <<2 ); }/* enable doorbells */ WREG32_FIELD (CP_PQ_STATUS ,DOORBELL_ENABLE ,1 );
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +4 -4
@@ -1566,7 +1566,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + ring_id) <<1 ; + ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) <<1 ; ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring_id *GFX9_MEC_HPD_SIZE );sprintf (ring->name,"comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue);
@@ -1655,7 +1655,7 @@ static int gfx_v9_0_sw_init(void *handle)else sprintf (ring->name,"gfx_%d" , i); ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL64_GFX_RING0 <<1 ; + ring->doorbell_index = adev->doorbell_index.gfx_ring0 <<1 ; r =amdgpu_ring_init (adev, ring,1024 , &adev->gfx.eop_irq,AMDGPU_CP_IRQ_GFX_EOP );if (r)
@@ -2981,9 +2981,9 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)/* enable the doorbell if requested */ if (ring->use_doorbell) {WREG32_SOC15 (GC ,0 , mmCP_MEC_DOORBELL_RANGE_LOWER, - (AMDGPU_DOORBELL64_KIQ *2 ) <<2 ); + (adev->doorbell_index.kiq *2 ) <<2 );WREG32_SOC15 (GC ,0 , mmCP_MEC_DOORBELL_RANGE_UPPER, - (AMDGPU_DOORBELL64_USERQUEUE_END *2 ) <<2 ); + (adev->doorbell_index.userqueue_end *2 ) <<2 ); } WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +1 -1
@@ -1146,7 +1146,7 @@ static int sdma_v3_0_sw_init(void *handle)if (!amdgpu_sriov_vf (adev)) { ring->use_doorbell = true; ring->doorbell_index = (i ==0 ) ? - AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.sdma_engine0 : adev->doorbell_index.sdma_engine1; }else { ring->use_pollmem = true; }
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +9 -16
@@ -1517,15 +1517,13 @@ static int sdma_v4_0_sw_init(void *handle) ring->ring_obj =NULL ; ring->use_doorbell = true; +DRM_INFO ("use_doorbell being set to: [%s]\n" , + ring->use_doorbell?"true" :"false" ); +/* doorbell size is 2 dwords, get DWORD offset */ -if (adev->asic_type ==CHIP_VEGA10 ) - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); -else - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index = (i ==0 ) ? + (adev->doorbell_index.sdma_engine0 <<1 ) + : (adev->doorbell_index.sdma_engine1 <<1 );sprintf (ring->name,"sdma%d" , i); r = amdgpu_ring_init(adev, ring, 1024,
@@ -1544,14 +1542,9 @@ static int sdma_v4_0_sw_init(void *handle)/* paging queue use same doorbell index/routing as gfx queue * with 0x400 (4096 dwords) offset on second doorbell page */ -if (adev->asic_type ==CHIP_VEGA10 ) - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); -else - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index = (i ==0 ) ? + (adev->doorbell_index.sdma_engine0 <<1 ) + : (adev->doorbell_index.sdma_engine1 <<1 ); ring->doorbell_index +=0x400 ;sprintf (ring->name,"page%d" , i);
drivers/gpu/drm/amd/amdgpu/tonga_ih.c +1 -1
@@ -322,7 +322,7 @@ static int tonga_ih_sw_init(void *handle)return r; adev->irq.ih.use_doorbell = true; - adev->irq.ih.doorbell_index =AMDGPU_DOORBELL_IH ; + adev->irq.ih.doorbell_index = adev->doorbell_index.ih; r =amdgpu_irq_init (adev);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +2 -2
@@ -455,9 +455,9 @@ static int uvd_v7_0_sw_init(void *handle)* sriov, so set unused location for other unused rings. */ if (i ==0 ) - ring->doorbell_index =AMDGPU_DOORBELL64_UVD_RING0_1 *2 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 *2 ;else - ring->doorbell_index =AMDGPU_DOORBELL64_UVD_RING2_3 *2 +1 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 *2 +1 ; } r =amdgpu_ring_init (adev, ring,512 , &adev->uvd.inst[j].irq,0 );if (r)
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +2 -2
@@ -466,9 +466,9 @@ static int vce_v4_0_sw_init(void *handle)* so set unused location for other unused rings. */ if (i ==0 ) - ring->doorbell_index =AMDGPU_DOORBELL64_VCE_RING0_1 *2 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring0_1 *2 ;else - ring->doorbell_index =AMDGPU_DOORBELL64_VCE_RING2_3 *2 +1 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring2_3 *2 +1 ; } r =amdgpu_ring_init (adev, ring,512 , &adev->vce.irq,0 );if (r)
drivers/gpu/drm/amd/amdgpu/vega10_ih.c +1 -1
@@ -385,7 +385,7 @@ static int vega10_ih_sw_init(void *handle)return r; adev->irq.ih.use_doorbell = true; - adev->irq.ih.doorbell_index =AMDGPU_DOORBELL64_IH <<1 ; + adev->irq.ih.doorbell_index = adev->doorbell_index.ih <<1 ; r =amdgpu_irq_init (adev);
Signature · 6 lines
2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): 1542837620-13571-6-git-send-email-ozeng-5C7GfCeVMHo@public.gmane.org
Alex Deucher
Reviewed-byRe: [PATCH 6/7] drm/amdgpu: Use asic specific doorbell index instead of macro definition
Quoted 5 lines · Oak Zeng
Change-Id Iffff84475efcfb482c474fccb133010abb5df5f4Signed-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Reviewed-by Alex Deucher <[email protected]>
Quoted 286 lines
--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 ++++++++------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +++++++++---------------- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- 12 files changed, 36 insertions(+), 54 deletions(-)drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +8
-19@@ -181,25 +181,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)* process in case of 64-bit doorbells so we * can use each doorbell assignment twice. */ -if (adev->asic_type ==CHIP_VEGA10 ) { - gpu_resources.sdma_doorbell[0 ][i] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >>1 ); - gpu_resources.sdma_doorbell[0 ][i+1 ] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 +0x200 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i+1 ] = - AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 +0x200 + (i >>1 ); - }else { - gpu_resources.sdma_doorbell[0 ][i] = - AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >>1 ); - gpu_resources.sdma_doorbell[0 ][i+1 ] = - AMDGPU_DOORBELL64_sDMA_ENGINE0 +0x200 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i] = - AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >>1 ); - gpu_resources.sdma_doorbell[1 ][i+1 ] = - AMDGPU_DOORBELL64_sDMA_ENGINE1 +0x200 + (i >>1 ); - } + gpu_resources.sdma_doorbell[0 ][i] = + adev->doorbell_index.sdma_engine0 + (i >>1 ); + gpu_resources.sdma_doorbell[0 ][i+1 ] = + adev->doorbell_index.sdma_engine0 +0x200 + (i >>1 ); + gpu_resources.sdma_doorbell[1 ][i] = + adev->doorbell_index.sdma_engine1 + (i >>1 ); + gpu_resources.sdma_doorbell[1 ][i+1 ] = + adev->doorbell_index.sdma_engine1 +0x200 + (i >>1 ); }/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for * SDMA, IH and VCN. So don't use them for the CP. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +1
-1@@ -537,7 +537,7 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) adev->doorbell.size =pci_resource_len (adev->pdev,2 ); adev->doorbell.num_doorbells =min_t (u32, adev->doorbell.size /sizeof (u32), -AMDGPU_DOORBELL_MAX_ASSIGNMENT +1 ); + adev->doorbell_index.max_assignment+1 );if (adev->doorbell.num_doorbells ==0 )return -EINVAL ;drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +1
-1@@ -250,7 +250,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, ring->adev =NULL ; ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_KIQ ; + ring->doorbell_index = adev->doorbell_index.kiq; r =amdgpu_gfx_kiq_acquire (adev, ring);if (r)drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +1
-1@@ -4363,7 +4363,7 @@ static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_MEC_RING0 + ring_id; + ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;sprintf (ring->name,"comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue); irq_type =AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +5
-5@@ -1890,7 +1890,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_MEC_RING0 + ring_id; + ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring_id *GFX8_MEC_HPD_SIZE );sprintf (ring->name,"comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue);@@ -2001,7 +2001,7 @@ static int gfx_v8_0_sw_init(void *handle)/* no gfx doorbells on iceland */ if (adev->asic_type !=CHIP_TOPAZ ) { ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL_GFX_RING0 ; + ring->doorbell_index = adev->doorbell_index.gfx_ring0; } r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,@@ -4215,7 +4215,7 @@ static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu tmp =REG_SET_FIELD (0 ,CP_RB_DOORBELL_RANGE_LOWER ,DOORBELL_RANGE_LOWER , -AMDGPU_DOORBELL_GFX_RING0 ); + adev->doorbell_index.gfx_ring0);WREG32 (mmCP_RB_DOORBELL_RANGE_LOWER, tmp); WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,@@ -4644,8 +4644,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)static void gfx_v8_0_set_mec_doorbell_range (struct amdgpu_device *adev) {if (adev->asic_type >CHIP_TONGA ) { -WREG32 (mmCP_MEC_DOORBELL_RANGE_LOWER,AMDGPU_DOORBELL_KIQ <<2 ); -WREG32 (mmCP_MEC_DOORBELL_RANGE_UPPER,AMDGPU_DOORBELL_MEC_RING7 <<2 ); +WREG32 (mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq <<2 ); +WREG32 (mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 <<2 ); }/* enable doorbells */ WREG32_FIELD (CP_PQ_STATUS ,DOORBELL_ENABLE ,1 );drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +4
-4@@ -1566,7 +1566,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, ring->ring_obj =NULL ; ring->use_doorbell = true; - ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + ring_id) <<1 ; + ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) <<1 ; ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring_id *GFX9_MEC_HPD_SIZE );sprintf (ring->name,"comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue);@@ -1655,7 +1655,7 @@ static int gfx_v9_0_sw_init(void *handle)else sprintf (ring->name,"gfx_%d" , i); ring->use_doorbell = true; - ring->doorbell_index =AMDGPU_DOORBELL64_GFX_RING0 <<1 ; + ring->doorbell_index = adev->doorbell_index.gfx_ring0 <<1 ; r =amdgpu_ring_init (adev, ring,1024 , &adev->gfx.eop_irq,AMDGPU_CP_IRQ_GFX_EOP );if (r)@@ -2981,9 +2981,9 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)/* enable the doorbell if requested */ if (ring->use_doorbell) {WREG32_SOC15 (GC ,0 , mmCP_MEC_DOORBELL_RANGE_LOWER, - (AMDGPU_DOORBELL64_KIQ *2 ) <<2 ); + (adev->doorbell_index.kiq *2 ) <<2 );WREG32_SOC15 (GC ,0 , mmCP_MEC_DOORBELL_RANGE_UPPER, - (AMDGPU_DOORBELL64_USERQUEUE_END *2 ) <<2 ); + (adev->doorbell_index.userqueue_end *2 ) <<2 ); } WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +1
-1@@ -1146,7 +1146,7 @@ static int sdma_v3_0_sw_init(void *handle)if (!amdgpu_sriov_vf (adev)) { ring->use_doorbell = true; ring->doorbell_index = (i ==0 ) ? - AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.sdma_engine0 : adev->doorbell_index.sdma_engine1; }else { ring->use_pollmem = true; }drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +9
-16@@ -1517,15 +1517,13 @@ static int sdma_v4_0_sw_init(void *handle) ring->ring_obj =NULL ; ring->use_doorbell = true; +DRM_INFO ("use_doorbell being set to: [%s]\n" , + ring->use_doorbell?"true" :"false" ); +/* doorbell size is 2 dwords, get DWORD offset */ -if (adev->asic_type ==CHIP_VEGA10 ) - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); -else - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index = (i ==0 ) ? + (adev->doorbell_index.sdma_engine0 <<1 ) + : (adev->doorbell_index.sdma_engine1 <<1 );sprintf (ring->name,"sdma%d" , i); r = amdgpu_ring_init(adev, ring, 1024,@@ -1544,14 +1542,9 @@ static int sdma_v4_0_sw_init(void *handle)/* paging queue use same doorbell index/routing as gfx queue * with 0x400 (4096 dwords) offset on second doorbell page */ -if (adev->asic_type ==CHIP_VEGA10 ) - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); -else - ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index = (i ==0 ) ? + (adev->doorbell_index.sdma_engine0 <<1 ) + : (adev->doorbell_index.sdma_engine1 <<1 ); ring->doorbell_index +=0x400 ;sprintf (ring->name,"page%d" , i);drivers/gpu/drm/amd/amdgpu/tonga_ih.c +1
-1@@ -322,7 +322,7 @@ static int tonga_ih_sw_init(void *handle)return r; adev->irq.ih.use_doorbell = true; - adev->irq.ih.doorbell_index =AMDGPU_DOORBELL_IH ; + adev->irq.ih.doorbell_index = adev->doorbell_index.ih; r =amdgpu_irq_init (adev);drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +2
-2@@ -455,9 +455,9 @@ static int uvd_v7_0_sw_init(void *handle)* sriov, so set unused location for other unused rings. */ if (i ==0 ) - ring->doorbell_index =AMDGPU_DOORBELL64_UVD_RING0_1 *2 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 *2 ;else - ring->doorbell_index =AMDGPU_DOORBELL64_UVD_RING2_3 *2 +1 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 *2 +1 ; } r =amdgpu_ring_init (adev, ring,512 , &adev->uvd.inst[j].irq,0 );if (r)drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +2
-2@@ -466,9 +466,9 @@ static int vce_v4_0_sw_init(void *handle)* so set unused location for other unused rings. */ if (i ==0 ) - ring->doorbell_index =AMDGPU_DOORBELL64_VCE_RING0_1 *2 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring0_1 *2 ;else - ring->doorbell_index =AMDGPU_DOORBELL64_VCE_RING2_3 *2 +1 ; + ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring2_3 *2 +1 ; } r =amdgpu_ring_init (adev, ring,512 , &adev->vce.irq,0 );if (r)drivers/gpu/drm/amd/amdgpu/vega10_ih.c +1
-2@@ -385,7 +385,7 @@ static int vega10_ih_sw_init(void *handle)return r; adev->irq.ih.use_doorbell = true; - adev->irq.ih.doorbell_index =AMDGPU_DOORBELL64_IH <<1 ; + adev->irq.ih.doorbell_index = adev->doorbell_index.ih <<1 ; r =amdgpu_irq_init (adev); --2.7.4
Quoted 4 lines
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 7/7 drm/amdgpu: Use new doorbell layout for vega20 and future asic
In reply to a message not in the archivev2: Use enum definition instead of hardcoded value
Change-Id I04d22fb717ac50483c0835f160a2e860e344f358
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 ++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 33 ++++++++++++++++++ 4 files changed, 87 insertions(+), 1 deletion(-)
drivers/gpu/drm/amd/amdgpu/amdgpu.h +50 -0
@@ -392,6 +392,56 @@ struct amdgpu_doorbell {u32 num_doorbells;/* Number of doorbells actually reserved for amdgpu. */ }; +typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT +{ +/* Compute + GFX: 0~255 */ +AMDGPU_VEGA20_DOORBELL_KIQ =0x000 , +AMDGPU_VEGA20_DOORBELL_HIQ =0x001 , +AMDGPU_VEGA20_DOORBELL_DIQ =0x002 , +AMDGPU_VEGA20_DOORBELL_MEC_RING0 =0x003 , +AMDGPU_VEGA20_DOORBELL_MEC_RING1 =0x004 , +AMDGPU_VEGA20_DOORBELL_MEC_RING2 =0x005 , +AMDGPU_VEGA20_DOORBELL_MEC_RING3 =0x006 , +AMDGPU_VEGA20_DOORBELL_MEC_RING4 =0x007 , +AMDGPU_VEGA20_DOORBELL_MEC_RING5 =0x008 , +AMDGPU_VEGA20_DOORBELL_MEC_RING6 =0x009 , +AMDGPU_VEGA20_DOORBELL_MEC_RING7 =0x00A , +AMDGPU_VEGA20_DOORBELL_USERQUEUE_START =0x00B , +AMDGPU_VEGA20_DOORBELL_USERQUEUE_END =0x08A , +AMDGPU_VEGA20_DOORBELL_GFX_RING0 =0x08B , +/* SDMA:256~335*/ + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 =0x100 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 =0x10A , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 =0x114 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 =0x11E , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 =0x128 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 =0x132 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 =0x13C , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 =0x146 , +/* IH: 376~391 */ +AMDGPU_VEGA20_DOORBELL_IH =0x178 , +/* MMSCH: 392~407 +* overlap the doorbell assignment with VCN as they are mutually exclusive +* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD +*/ +AMDGPU_VEGA20_DOORBELL64_VCN0_1 =0x188 ,/* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ +AMDGPU_VEGA20_DOORBELL64_VCN2_3 =0x189 , +AMDGPU_VEGA20_DOORBELL64_VCN4_5 =0x18A , +AMDGPU_VEGA20_DOORBELL64_VCN6_7 =0x18B , + +AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 =0x188 , +AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 =0x189 , +AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 =0x18A , +AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 =0x18B , + +AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 =0x18C , +AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 =0x18D , +AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 =0x18E , +AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 =0x18F , +AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT =0x18F , +AMDGPU_VEGA20_DOORBELL_INVALID =0xFFFF +}AMDGPU_VEGA20_DOORBELL_ASSIGNMENT ; +/* * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space */
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +3 -1
@@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)vi_doorbell_index_init (adev); else if (adev->asic_type == CHIP_VEGA10) vega10_doorbell_index_init(adev); - else + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_RAVEN) vega12_doorbell_index_init(adev); + else +vega20_doorbell_index_init (adev );/* No doorbell on SI hardware generation */ if (adev->asic_type <CHIP_BONAIRE ) {
drivers/gpu/drm/amd/amdgpu/soc15.h +1 -0
@@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);void vega10_doorbell_index_init (struct amdgpu_device *adev);void vega12_doorbell_index_init (struct amdgpu_device *adev); +void vega20_doorbell_index_init (struct amdgpu_device *adev);#endif
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c +33 -0
@@ -54,4 +54,37 @@ int vega20_reg_base_init(struct amdgpu_device *adev)return 0 ; } +void vega20_doorbell_index_init (struct amdgpu_device *adev) +{ + adev->doorbell_index.kiq =AMDGPU_VEGA20_DOORBELL_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_VEGA20_DOORBELL_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_VEGA20_DOORBELL_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_VEGA20_DOORBELL_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_VEGA20_DOORBELL_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_VEGA20_DOORBELL_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_VEGA20_DOORBELL_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_VEGA20_DOORBELL_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_VEGA20_DOORBELL_MEC_RING7 ; + adev->doorbell_index.userqueue_start =AMDGPU_VEGA20_DOORBELL_USERQUEUE_START ; + adev->doorbell_index.userqueue_end =AMDGPU_VEGA20_DOORBELL_USERQUEUE_END ; + adev->doorbell_index.gfx_ring0 =AMDGPU_VEGA20_DOORBELL_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.sdma_engine2 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2; + adev->doorbell_index.sdma_engine3 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3; + adev->doorbell_index.sdma_engine4 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4; + adev->doorbell_index.sdma_engine5 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5; + adev->doorbell_index.sdma_engine6 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6; + adev->doorbell_index.sdma_engine7 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7; + adev->doorbell_index.ih =AMDGPU_VEGA20_DOORBELL_IH ; + adev->doorbell_index.uvd_vce.uvd_ring0_1 =AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 ; + adev->doorbell_index.uvd_vce.uvd_ring2_3 =AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 ; + adev->doorbell_index.uvd_vce.uvd_ring4_5 =AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 ; + adev->doorbell_index.uvd_vce.uvd_ring6_7 =AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 ; + adev->doorbell_index.uvd_vce.vce_ring0_1 =AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 ; + adev->doorbell_index.uvd_vce.vce_ring2_3 =AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 ; + adev->doorbell_index.uvd_vce.vce_ring4_5 =AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 ; + adev->doorbell_index.uvd_vce.vce_ring6_7 =AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 ; + adev->doorbell_index.max_assignment =AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT <<1 ; +}
Signature · 6 lines
2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): 1542837620-13571-7-git-send-email-ozeng-5C7GfCeVMHo@public.gmane.org
Re: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
Quoted 7 lines · Oak Zeng
v2: Use enum definition instead of hardcoded value
Change-Id I04d22fb717ac50483c0835f160a2e860e344f358Signed-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
This patch should come before patch 5 so we update all of the asics before we switch to using the new interface.
Alex
Quoted 139 lines
--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 ++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 33 ++++++++++++++++++ 4 files changed, 87 insertions(+), 1 deletion(-)drivers/gpu/drm/amd/amdgpu/amdgpu.h +50
-0@@ -392,6 +392,56 @@ struct amdgpu_doorbell {u32 num_doorbells;/* Number of doorbells actually reserved for amdgpu. */ }; +typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT +{ +/* Compute + GFX: 0~255 */ +AMDGPU_VEGA20_DOORBELL_KIQ =0x000 , +AMDGPU_VEGA20_DOORBELL_HIQ =0x001 , +AMDGPU_VEGA20_DOORBELL_DIQ =0x002 , +AMDGPU_VEGA20_DOORBELL_MEC_RING0 =0x003 , +AMDGPU_VEGA20_DOORBELL_MEC_RING1 =0x004 , +AMDGPU_VEGA20_DOORBELL_MEC_RING2 =0x005 , +AMDGPU_VEGA20_DOORBELL_MEC_RING3 =0x006 , +AMDGPU_VEGA20_DOORBELL_MEC_RING4 =0x007 , +AMDGPU_VEGA20_DOORBELL_MEC_RING5 =0x008 , +AMDGPU_VEGA20_DOORBELL_MEC_RING6 =0x009 , +AMDGPU_VEGA20_DOORBELL_MEC_RING7 =0x00A , +AMDGPU_VEGA20_DOORBELL_USERQUEUE_START =0x00B , +AMDGPU_VEGA20_DOORBELL_USERQUEUE_END =0x08A , +AMDGPU_VEGA20_DOORBELL_GFX_RING0 =0x08B , +/* SDMA:256~335*/ + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 =0x100 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 =0x10A , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 =0x114 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 =0x11E , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 =0x128 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 =0x132 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 =0x13C , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 =0x146 , +/* IH: 376~391 */ +AMDGPU_VEGA20_DOORBELL_IH =0x178 , +/* MMSCH: 392~407 +* overlap the doorbell assignment with VCN as they are mutually exclusive +* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD +*/ +AMDGPU_VEGA20_DOORBELL64_VCN0_1 =0x188 ,/* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ +AMDGPU_VEGA20_DOORBELL64_VCN2_3 =0x189 , +AMDGPU_VEGA20_DOORBELL64_VCN4_5 =0x18A , +AMDGPU_VEGA20_DOORBELL64_VCN6_7 =0x18B , + +AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 =0x188 , +AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 =0x189 , +AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 =0x18A , +AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 =0x18B , + +AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 =0x18C , +AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 =0x18D , +AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 =0x18E , +AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 =0x18F , +AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT =0x18F , +AMDGPU_VEGA20_DOORBELL_INVALID =0xFFFF +}AMDGPU_VEGA20_DOORBELL_ASSIGNMENT ; +/* * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space */ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +3
-1@@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)vi_doorbell_index_init (adev); else if (adev->asic_type == CHIP_VEGA10) vega10_doorbell_index_init(adev); - else + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_RAVEN) vega12_doorbell_index_init(adev); + else +vega20_doorbell_index_init (adev );/* No doorbell on SI hardware generation */ if (adev->asic_type <CHIP_BONAIRE ) {drivers/gpu/drm/amd/amdgpu/soc15.h +1
-0@@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);void vega10_doorbell_index_init (struct amdgpu_device *adev);void vega12_doorbell_index_init (struct amdgpu_device *adev); +void vega20_doorbell_index_init (struct amdgpu_device *adev);#endif drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c +33
-1@@ -54,4 +54,37 @@ int vega20_reg_base_init(struct amdgpu_device *adev)return 0 ; } +void vega20_doorbell_index_init (struct amdgpu_device *adev) +{ + adev->doorbell_index.kiq =AMDGPU_VEGA20_DOORBELL_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_VEGA20_DOORBELL_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_VEGA20_DOORBELL_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_VEGA20_DOORBELL_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_VEGA20_DOORBELL_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_VEGA20_DOORBELL_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_VEGA20_DOORBELL_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_VEGA20_DOORBELL_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_VEGA20_DOORBELL_MEC_RING7 ; + adev->doorbell_index.userqueue_start =AMDGPU_VEGA20_DOORBELL_USERQUEUE_START ; + adev->doorbell_index.userqueue_end =AMDGPU_VEGA20_DOORBELL_USERQUEUE_END ; + adev->doorbell_index.gfx_ring0 =AMDGPU_VEGA20_DOORBELL_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.sdma_engine2 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2; + adev->doorbell_index.sdma_engine3 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3; + adev->doorbell_index.sdma_engine4 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4; + adev->doorbell_index.sdma_engine5 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5; + adev->doorbell_index.sdma_engine6 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6; + adev->doorbell_index.sdma_engine7 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7; + adev->doorbell_index.ih =AMDGPU_VEGA20_DOORBELL_IH ; + adev->doorbell_index.uvd_vce.uvd_ring0_1 =AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 ; + adev->doorbell_index.uvd_vce.uvd_ring2_3 =AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 ; + adev->doorbell_index.uvd_vce.uvd_ring4_5 =AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 ; + adev->doorbell_index.uvd_vce.uvd_ring6_7 =AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 ; + adev->doorbell_index.uvd_vce.vce_ring0_1 =AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 ; + adev->doorbell_index.uvd_vce.vce_ring2_3 =AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 ; + adev->doorbell_index.uvd_vce.vce_ring4_5 =AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 ; + adev->doorbell_index.uvd_vce.vce_ring6_7 =AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 ; + adev->doorbell_index.max_assignment =AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT <<1 ; +} --2.7.4
Quoted 4 lines
_______________________________________________
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_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
In reply to a message not in the archiveHi Alex/Felix,
This is a modified version based on your feedback. Do you have more comment?
Regards,
Oak
-----Original Message-----
From: Zeng, Oak <[email protected]>
Sent: Wednesday, November 21, 2018 5:01 PM
To: [email protected]
Cc: Zeng, Oak <[email protected]>
Subject: [PATCH 7/7] drm/amdgpu: Use new doorbell layout for vega20 and future asic
v2: Use enum definition instead of hardcoded value
Change-Id I04d22fb717ac50483c0835f160a2e860e344f358
Signed-off-by Oak Zeng <[email protected]>
Suggested-by Felix Kuehling <[email protected]>
Suggested-by Alex Deucher <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 ++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 33 ++++++++++++++++++ 4 files changed, 87 insertions(+), 1 deletion(-)
drivers/gpu/drm/amd/amdgpu/amdgpu.h +50 -0
@@ -392,6 +392,56 @@ struct amdgpu_doorbell {u32 num_doorbells;/* Number of doorbells actually reserved for amdgpu. */ }; +typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT +{ +/* Compute + GFX: 0~255 */ +AMDGPU_VEGA20_DOORBELL_KIQ =0x000 , +AMDGPU_VEGA20_DOORBELL_HIQ =0x001 , +AMDGPU_VEGA20_DOORBELL_DIQ =0x002 , +AMDGPU_VEGA20_DOORBELL_MEC_RING0 =0x003 , +AMDGPU_VEGA20_DOORBELL_MEC_RING1 =0x004 , +AMDGPU_VEGA20_DOORBELL_MEC_RING2 =0x005 , +AMDGPU_VEGA20_DOORBELL_MEC_RING3 =0x006 , +AMDGPU_VEGA20_DOORBELL_MEC_RING4 =0x007 , +AMDGPU_VEGA20_DOORBELL_MEC_RING5 =0x008 , +AMDGPU_VEGA20_DOORBELL_MEC_RING6 =0x009 , +AMDGPU_VEGA20_DOORBELL_MEC_RING7 =0x00A , +AMDGPU_VEGA20_DOORBELL_USERQUEUE_START =0x00B , +AMDGPU_VEGA20_DOORBELL_USERQUEUE_END =0x08A , +AMDGPU_VEGA20_DOORBELL_GFX_RING0 =0x08B , +/* SDMA:256~335*/ + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 =0x100 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 =0x10A , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 =0x114 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 =0x11E , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 =0x128 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 =0x132 , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 =0x13C , + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 =0x146 , +/* IH: 376~391 */ +AMDGPU_VEGA20_DOORBELL_IH =0x178 , +/* MMSCH: 392~407 +* overlap the doorbell assignment with VCN as they are mutually exclusive +* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD +*/ +AMDGPU_VEGA20_DOORBELL64_VCN0_1 =0x188 ,/* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ +AMDGPU_VEGA20_DOORBELL64_VCN2_3 =0x189 , +AMDGPU_VEGA20_DOORBELL64_VCN4_5 =0x18A , +AMDGPU_VEGA20_DOORBELL64_VCN6_7 =0x18B , + +AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 =0x188 , +AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 =0x189 , +AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 =0x18A , +AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 =0x18B , + +AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 =0x18C , +AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 =0x18D , +AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 =0x18E , +AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 =0x18F , +AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT =0x18F , +AMDGPU_VEGA20_DOORBELL_INVALID =0xFFFF +}AMDGPU_VEGA20_DOORBELL_ASSIGNMENT ; +/* * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space */
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +4 -1
@@ -517,8 +517,10 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)vi_doorbell_index_init (adev); else if (adev->asic_type == CHIP_VEGA10) vega10_doorbell_index_init(adev); - else + else if (adev->asic_type == CHIP_VEGA12 || adev->asic_type == +CHIP_RAVEN) vega12_doorbell_index_init(adev); + else +vega20_doorbell_index_init (adev );/* No doorbell on SI hardware generation */
if (adev->asic_type < CHIP_BONAIRE) {
drivers/gpu/drm/amd/amdgpu/soc15.h +1 -0
@@ -60,4 +60,5 @@ int vega20_reg_base_init(struct amdgpu_device *adev);void vega10_doorbell_index_init (struct amdgpu_device *adev);void vega12_doorbell_index_init (struct amdgpu_device *adev); +void vega20_doorbell_index_init (struct amdgpu_device *adev);#endif
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c +32 -0
@@ -54,4 +54,37 @@ int vega20_reg_base_init(struct amdgpu_device *adev)return 0 ; } +void vega20_doorbell_index_init (struct amdgpu_device *adev) { + adev->doorbell_index.kiq =AMDGPU_VEGA20_DOORBELL_KIQ ; + adev->doorbell_index.mec_ring0 =AMDGPU_VEGA20_DOORBELL_MEC_RING0 ; + adev->doorbell_index.mec_ring1 =AMDGPU_VEGA20_DOORBELL_MEC_RING1 ; + adev->doorbell_index.mec_ring2 =AMDGPU_VEGA20_DOORBELL_MEC_RING2 ; + adev->doorbell_index.mec_ring3 =AMDGPU_VEGA20_DOORBELL_MEC_RING3 ; + adev->doorbell_index.mec_ring4 =AMDGPU_VEGA20_DOORBELL_MEC_RING4 ; + adev->doorbell_index.mec_ring5 =AMDGPU_VEGA20_DOORBELL_MEC_RING5 ; + adev->doorbell_index.mec_ring6 =AMDGPU_VEGA20_DOORBELL_MEC_RING6 ; + adev->doorbell_index.mec_ring7 =AMDGPU_VEGA20_DOORBELL_MEC_RING7 ; + adev->doorbell_index.userqueue_start =AMDGPU_VEGA20_DOORBELL_USERQUEUE_START ; + adev->doorbell_index.userqueue_end =AMDGPU_VEGA20_DOORBELL_USERQUEUE_END ; + adev->doorbell_index.gfx_ring0 =AMDGPU_VEGA20_DOORBELL_GFX_RING0 ; + adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0; + adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1; + adev->doorbell_index.sdma_engine2 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2; + adev->doorbell_index.sdma_engine3 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3; + adev->doorbell_index.sdma_engine4 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4; + adev->doorbell_index.sdma_engine5 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5; + adev->doorbell_index.sdma_engine6 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6; + adev->doorbell_index.sdma_engine7 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7; + adev->doorbell_index.ih =AMDGPU_VEGA20_DOORBELL_IH ; + adev->doorbell_index.uvd_vce.uvd_ring0_1 =AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 ; + adev->doorbell_index.uvd_vce.uvd_ring2_3 =AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 ; + adev->doorbell_index.uvd_vce.uvd_ring4_5 =AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 ; + adev->doorbell_index.uvd_vce.uvd_ring6_7 =AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 ; + adev->doorbell_index.uvd_vce.vce_ring0_1 =AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 ; + adev->doorbell_index.uvd_vce.vce_ring2_3 =AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 ; + adev->doorbell_index.uvd_vce.vce_ring4_5 =AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 ; + adev->doorbell_index.uvd_vce.vce_ring6_7 =AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 ; + adev->doorbell_index.max_assignment = +AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT <<1 ; }
--
2.7.4
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Alex Deucher
Reviewed-byQuoted 10 lines · Oak Zeng
This is a preparation work to make reserved doorbell index per device, instead of using a global macro definition. By doing this, we can easily change doorbell layout for future ASICs while not affecting ASICs in production.
Change-Id If08e2bc9d0749748ed4083ba4eb32a4698763085Signed-off-by Oak Zeng <[email protected]>Suggested-by Felix Kuehling <[email protected]>Suggested-by Alex Deucher <[email protected]>
Reviewed-by Alex Deucher <[email protected]>
It would be nice to move all of the doorbell related enums and this structure into amdgpu_doorbell.h, but that can be later cleanup.
Alex
Quoted 75 lines
--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 +++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)drivers/gpu/drm/amd/amdgpu/amdgpu.h +50
-1@@ -813,6 +813,55 @@ struct amd_powerplay {uint32_t pp_feature; }; +/* Reserved doorbells for amdgpu (including multimedia). +* KFD can use all the rest in the 2M doorbell bar. +* For asic before vega10, doorbell is 32-bit, so the +* index/offset is in dword. For vega10 and after, doorbell +* can be 64-bit, so the index defined is in qword. +*/ +struct amdgpu_doorbell_index { +uint32_t kiq; +uint32_t mec_ring0; +uint32_t mec_ring1; +uint32_t mec_ring2; +uint32_t mec_ring3; +uint32_t mec_ring4; +uint32_t mec_ring5; +uint32_t mec_ring6; +uint32_t mec_ring7; +uint32_t userqueue_start; +uint32_t userqueue_end; +uint32_t gfx_ring0; +uint32_t sdma_engine0; +uint32_t sdma_engine1; +uint32_t sdma_engine2; +uint32_t sdma_engine3; +uint32_t sdma_engine4; +uint32_t sdma_engine5; +uint32_t sdma_engine6; +uint32_t sdma_engine7; +uint32_t ih; +union { +struct { +uint32_t vcn_ring0_1; +uint32_t vcn_ring2_3; +uint32_t vcn_ring4_5; +uint32_t vcn_ring6_7; + } vcn; +struct { +uint32_t uvd_ring0_1; +uint32_t uvd_ring2_3; +uint32_t uvd_ring4_5; +uint32_t uvd_ring6_7; +uint32_t vce_ring0_1; +uint32_t vce_ring2_3; +uint32_t vce_ring4_5; +uint32_t vce_ring6_7; + } uvd_vce; + }; +uint32_t max_assignment; +}; +#define AMDGPU_RESET_MAGIC_NUM 64struct amdgpu_device {struct device *dev;@@ -1026,6 +1075,7 @@ struct amdgpu_device {unsigned long last_mm_index;bool in_gpu_reset;struct mutex lock_reset; +struct amdgpu_doorbell_index doorbell_index; };static inline struct amdgpu_device *amdgpu_ttm_adev (struct ttm_bo_device *bdev) --2.7.4
Quoted 4 lines
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