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ARM: dts: imx6ul: Correct mask for GIC PPI interrupts

RFC Applied Fabio Estevam 2 participants 3 messages Nov 26, 2018 – Dec 5, 2018

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Fabio Estevam

author reviewer
#0 lore raw

RFC 1/2 ARM: dts: imx6ul: Correct mask for GIC PPI interrupts

The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to.

i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".

Tested on a imx6ul-evk.

Signed-off-by Fabio Estevam <[email protected]>

---
Hi,

This is based on the following commit:

commit 2acb79e15119512da9b6a49906840e7678cfb618

Author: Geert Uytterhoeven <[email protected]>
Date:   Mon May 7 15:19:52 2018 +0200

ARM: dts: r8a7790: Correct mask for GIC PPI interrupts

R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to all 8 processor cores.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>

and the confirmation from Liviu Dudau that GIC_CPU_MASK_SIMPLE() should take the number of cores in the system as the argument:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315298.html

 arch/arm/boot/dts/imx6ul.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/boot/dts/imx6ul.dtsi +4 -4
index c71d2d6..b8f5ef2 100644
@@ -108,10 +108,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 		interrupt-parent = <&intc>;
 		status = "disabled";
 	};
Signature · 1 line
2.7.4
author reviewer
#1 lore raw

RFC 2/2 ARM: dts: imx7: Correct mask for GIC PPI interrupts

The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to.

i.MX7S contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".

Likewise, i.MX7D contains two Cortex-A7 cores, so it should use "GIC_CPU_MASK_SIMPLE(2)" instead.

Tested on a imx7s-warp.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++
 arch/arm/boot/dts/imx7s.dtsi | 8 ++++----
 2 files changed, 13 insertions(+), 4 deletions(-)
arch/arm/boot/dts/imx7d.dtsi +9 -0
index 826224b..b066749 100644
@@ -24,6 +24,15 @@
 		};
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
 	cpu0_opp_table: opp-table {
 		compatible = "operating-points-v2";
 		opp-shared;
arch/arm/boot/dts/imx7s.dtsi +4 -4
index 477901c..be02a10 100644
@@ -160,10 +160,10 @@
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupt-parent = <&intc>;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	soc {
Signature · 1 line
2.7.4
Applied
#2 lore raw
In reply to Fabio Estevam
Quoted 9 lines · Fabio Estevam

The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to.

i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".

Tested on a imx6ul-evk.

Signed-off-by Fabio Estevam <[email protected]>

Applied both, thanks.

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