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drm/amdgpu: Fix num_doorbell calculation issue

PATCH In review Oak Zeng 2 participants 2 messages Nov 30, 2018 1 message not in the archive

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Oak Zeng

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PATCH 1/1 drm/amdgpu: Fix num_doorbell calculation issue

When paging queue is enabled, it use the second page of doorbell. The AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the kernel doorbells are in the first page. So with paging queue enabled, the total kernel doorbell range should be original num_doorbell plus one page (0x400 in dword), not *2.

Change-Id I62023bb91da33ca5532b22b263771b587b796d59
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +5 -2
index 8eaa40e..c75badf 100644
@@ -539,10 +539,13 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 		return -EINVAL;
 
 	/* For Vega, reserve and map two pages on doorbell BAR since SDMA
-	 * paging queue doorbell use the second page
+	 * paging queue doorbell use the second page. The
+	 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
+	 * doorbells are in the first page. So with paging queue enabled,
+	 * the max num_doorbells should + 1 page (0x400 in dword)
 	 */
 	if (adev->asic_type >= CHIP_VEGA10)
-		adev->doorbell.num_doorbells *= 2;
+		adev->doorbell.num_doorbells += 0x400;
 
 	adev->doorbell.ptr = ioremap(adev->doorbell.base,
 				     adev->doorbell.num_doorbells *
Signature · 6 lines
2.7.4

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A message that is not in the archive (sent off-list or not yet received): 1543592352-6915-1-git-send-email-ozeng-5C7GfCeVMHo@public.gmane.org

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________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Oak Zeng <[email protected]>
Sent: Friday, November 30, 2018 10:39:21 AM
To: [email protected]
Cc: Yang, Philip; Zeng, Oak; Yin, Tianci (Rico)
Subject: [PATCH] drm/amdgpu: Fix num_doorbell calculation issue

When paging queue is enabled, it use the second page of doorbell. The AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the kernel doorbells are in the first page. So with paging queue enabled, the total kernel doorbell range should be original num_doorbell plus one page (0x400 in dword), not *2.

Change-Id I62023bb91da33ca5532b22b263771b587b796d59
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +5 -2
index 8eaa40e..c75badf 100644
@@ -539,10 +539,13 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
                 return -EINVAL;
 
         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
-        * paging queue doorbell use the second page
+        * paging queue doorbell use the second page. The
+        * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
+        * doorbells are in the first page. So with paging queue enabled,
+        * the max num_doorbells should + 1 page (0x400 in dword)
          */
         if (adev->asic_type >= CHIP_VEGA10)
-               adev->doorbell.num_doorbells *= 2;
+               adev->doorbell.num_doorbells += 0x400;
 
         adev->doorbell.ptr = ioremap(adev->doorbell.base,
                                      adev->doorbell.num_doorbells *

--
2.7.4

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[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx