pinctrl: rockchip: fix rk3288 gpio0 pull up configuration

On rk3288, for gpio bank 0, the registers which configure pull-ups don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio's pull up settings in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of gpio0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Signed-off-by Sonny Rao <[email protected]>

---
 drivers/pinctrl/pinctrl-rockchip.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(quoted diff) +0 -0

b/drivers/pinctrl/pinctrl-rockchip.c index 5e8b2e0..bd00ae9 100644

drivers/pinctrl/pinctrl-rockchip.c +10 -2

@@ -722,7 +722,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank
 *bank, int reg, ret;
 	unsigned long flags;
 	u8 bit;
-	u32 data;
+	u32 data, mask;
 
 	dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 		 bank->bank_num, pin_num, pull);

@@ -751,6 +751,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank
 *bank, /* enable the write to the equivalent lower bits */
 		data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 
+		/*
+		 * on rk3288, gpio bank 0 doesn't support the write enable, and
+		 * upper 16 bit are always zero, so we create a mask which will
+		 * only update the bits we want in the lower 16, while still
+		 * preserving write enable bits in upper 16.
+		 */
+		mask = data | (data >> 16);
+
 		switch (pull) {
 		case PIN_CONFIG_BIAS_DISABLE:
 			break;

@@ -770,7 +778,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank
 *bank, return -EINVAL;
 		}
 
-		ret = regmap_write(regmap, reg, data);
+		ret = regmap_update_bits(regmap, reg, mask, data);
 
 		spin_unlock_irqrestore(&bank->slock, flags);
 		break;

On rk3288, for gpio bank 0, the registers which configure pull-up, iomux, and drive strength don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of bank0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Signed-off-by Sonny Rao <[email protected]>

---
v2: rebase onto latest pinctrl with drive strength and fix this bug on
iomux and drive strength as well.

 drivers/pinctrl/pinctrl-rockchip.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

(quoted diff) +0 -0

b/drivers/pinctrl/pinctrl-rockchip.c index c15f7f9..4ff5dc3 100644

drivers/pinctrl/pinctrl-rockchip.c +6 -4

@@ -438,7 +438,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank
 *bank, int pin, int mux) int reg, ret, mask;
 	unsigned long flags;
 	u8 bit;
-	u32 data;
+	u32 data, rmask;
 
 	if (iomux_num > 3)
 		return -EINVAL;

@@ -478,8 +478,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank
 *bank, int pin, int mux) spin_lock_irqsave(&bank->slock, flags);
 
 	data = (mask << (bit + 16));
+	rmask = data | (data >> 16);
 	data |= (mux & mask) << bit;
-	ret = regmap_write(regmap, reg, data);
+	ret = regmap_update_bits(regmap, reg, rmask, data);
 
 	spin_unlock_irqrestore(&bank->slock, flags);
 

@@ -634,7 +635,7 @@ static int rk3288_set_drive(struct rockchip_pin_bank
 *bank, int pin_num, struct regmap *regmap;
 	unsigned long flags;
 	int reg, ret, i;
-	u32 data;
+	u32 data, rmask;
 	u8 bit;
 
 	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);

@@ -657,9 +658,10 @@ static int rk3288_set_drive(struct rockchip_pin_bank
 *bank, int pin_num,
 
 	/* enable the write to the equivalent lower bits */
 	data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
 	data |= (ret << bit);
 
-	ret = regmap_write(regmap, reg, data);
+	ret = regmap_update_bits(regmap, reg, rmask, data);
 	spin_unlock_irqrestore(&bank->slock, flags);
 

drivers/pinctrl/pinctrl-rockchip.c +2 -1

 	return ret;

@@ -722,7 +724,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank
 *bank, int reg, ret;
 	unsigned long flags;
 	u8 bit;
-	u32 data;
+	u32 data, rmask;
 
 	dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 		 bank->bank_num, pin_num, pull);

@@ -750,6 +752,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank
 *bank,
 
 		/* enable the write to the equivalent lower bits */
 		data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+		rmask = data | (data >> 16);
 
 		switch (pull) {

drivers/pinctrl/pinctrl-rockchip.c +1 -1

 		case PIN_CONFIG_BIAS_DISABLE:

@@ -770,7 +773,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank
 *bank, return -EINVAL;
 		}
 
-		ret = regmap_write(regmap, reg, data);
+		ret = regmap_update_bits(regmap, reg, rmask, data);
 
 		spin_unlock_irqrestore(&bank->slock, flags);
 		break;

On rk3288, for gpio bank 0, the registers which configure pull-up, iomux, and drive strength don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of bank0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Signed-off-by Sonny Rao <[email protected]>

---
v2: rebase onto latest pinctrl with drive strength and fix this bug on
iomux and drive strength as well.

 drivers/pinctrl/pinctrl-rockchip.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

On rk3288, for gpio bank 0, the registers which configure pull-up, iomux, and drive strength don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of bank0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Signed-off-by Sonny Rao <[email protected]>

---
v2: rebase onto latest pinctrl with drive strength and fix this bug on
iomux and drive strength as well.

On rk3288, for gpio bank 0, the registers which configure pull-ups don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio's pull up settings in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of gpio0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Signed-off-by Sonny Rao <[email protected]>

Quoted 12 lines

On rk3288, for gpio bank 0, the registers which configure pull-ups don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio's pull up settings in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of gpio0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Quoted 1 line

Signed-off-by Sonny Rao <[email protected]>

Waiting for a v2 fixing the other issues pointed out by Heiko.

Am Freitag, 8. August 2014, 15:37:46 schrieb Linus Walleij:

Quoted 15 lines · Sonny Rao

Quoted 13 lines

On rk3288, for gpio bank 0, the registers which configure pull-ups don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio's pull up settings in that bank.

The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of gpio0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered.

Signed-off-by Sonny Rao <[email protected]>

Quoted 1 line

Waiting for a v2 fixing the other issues pointed out by Heiko.

Sonny posted v2 on 2014-08-01 as reply to my comment, but it might still be sitting in your inbox-backlog :-)

Checking Sonny's v2-mail again I see that you did somehow land in the Cc-list and not the To-list, which might be the reason you didn't see it yet?

Heiko