drm/amdgpu: Limit vm max ctx number to 4096
Subsystems (2)
PATCH 1/9 drm/amdgpu: Limit vm max ctx number to 4096
driver need to reserve resource for each ctx for
some hw features. so add this limitation.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)
drivers/gpu/drm/amd/amdgpu/amdgpu.h +1 -0
@@ -161,6 +161,7 @@ struct amdgpu_mgpu_infoextern int amdgpu_cik_support;#endif +#define AMDGPU_VM_MAX_NUM_CTX 4096#define AMDGPU_SG_THRESHOLD (256*1024*1024)#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL/* 3GB by default */ #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +1 -1
@@ -247,7 +247,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,return -ENOMEM ;mutex_lock (&mgr->lock); - r =idr_alloc (&mgr->ctx_handles, ctx,1 ,0 ,GFP_KERNEL ); + r =idr_alloc (&mgr->ctx_handles, ctx,1 ,AMDGPU_VM_MAX_NUM_CTX ,GFP_KERNEL );if (r <0 ) {mutex_unlock (&mgr->lock);kfree (ctx);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): 1544095957-21101-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org
PATCH 2/9 drm/amdgpu: Refine function amdgpu_csa_vaddr
on baremetal, driver create csa per ctx. So add a function argument: ctx_id to get csa gpu addr.
In Sriov, driver create csa per process, so ctx id always 1.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- 5 files changed, 11 insertions(+), 10 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +3 -2
@@ -24,11 +24,12 @@#include "amdgpu.h" -uint64_t amdgpu_csa_vaddr (struct amdgpu_device *adev) +uint64_t amdgpu_csa_vaddr (struct amdgpu_device *adev,uint32_t id) {uint64_t addr = adev->vm_manager.max_pfn <<AMDGPU_GPU_PAGE_SHIFT ; - addr -=AMDGPU_VA_RESERVED_SIZE ; + addr -=AMDGPU_VA_RESERVED_SIZE * id; + addr =amdgpu_gmc_sign_extend (addr);return addr;
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h +1 -1
@@ -28,7 +28,7 @@#define AMDGPU_CSA_SIZE (128 * 1024)uint32_t amdgpu_get_total_csa_size (struct amdgpu_device *adev); -uint64_t amdgpu_csa_vaddr (struct amdgpu_device *adev); +uint64_t amdgpu_csa_vaddr (struct amdgpu_device *adev,uint32_t id);int amdgpu_allocate_static_csa (struct amdgpu_device *adev,struct amdgpu_bo **bo,u32 domain,uint32_t size); int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +2 -2
@@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto error_vm; } -if (amdgpu_sriov_vf (adev)) { -uint64_t csa_addr =amdgpu_csa_vaddr (adev) &AMDGPU_GMC_HOLE_MASK ; +if (amdgpu_sriov_vf (adev)) { +uint64_t csa_addr =amdgpu_csa_vaddr (adev,1 ) &AMDGPU_GMC_HOLE_MASK ; r =amdgpu_map_static_csa (adev, &fpriv->vm, adev->virt.csa_obj, &fpriv->csa_va, csa_addr,AMDGPU_CSA_SIZE );if (r)
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +3 -3
@@ -7192,11 +7192,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring) } ce_payload = {};if (ring->adev->virt.chained_ib_support) { - ce_payload_addr =amdgpu_csa_vaddr (ring->adev) + + ce_payload_addr =amdgpu_csa_vaddr (ring->adev,1 ) + offsetof(struct vi_gfx_meta_data_chained_ib , ce_payload); cnt_ce = (sizeof (ce_payload.chained) >>2 ) +4 -2 ; }else { - ce_payload_addr =amdgpu_csa_vaddr (ring->adev) + + ce_payload_addr =amdgpu_csa_vaddr (ring->adev,1 ) + offsetof(struct vi_gfx_meta_data , ce_payload); cnt_ce = (sizeof (ce_payload.regular) >>2 ) +4 -2 ; }
@@ -7220,7 +7220,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)struct vi_de_ib_state_chained_ib chained; } de_payload = {}; - csa_addr =amdgpu_csa_vaddr (ring->adev); + csa_addr =amdgpu_csa_vaddr (ring->adev,1 ); gds_addr = csa_addr +4096 ;if (ring->adev->virt.chained_ib_support) { de_payload.chained.gds_backup_addrlo =lower_32_bits (gds_addr);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +2 -2
@@ -4327,7 +4327,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)int cnt; cnt = (sizeof (ce_payload) >>2 ) +4 -2 ; - csa_addr =amdgpu_csa_vaddr (ring->adev); + csa_addr =amdgpu_csa_vaddr (ring->adev,1 );amdgpu_ring_write (ring,PACKET3 (PACKET3_WRITE_DATA , cnt)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4345,7 +4345,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)uint64_t csa_addr, gds_addr;int cnt; - csa_addr =amdgpu_csa_vaddr (ring->adev); + csa_addr =amdgpu_csa_vaddr (ring->adev,1 ); gds_addr = csa_addr +4096 ; de_payload.gds_backup_addrlo =lower_32_bits (gds_addr); de_payload.gds_backup_addrhi =upper_32_bits (gds_addr);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 3/9 drm/amdgpu: Use dynamical reserved vm size
In reply to a message not in the archiveUse dynamical reserved vm size instand of hardcode.
driver always reserve AMDGPU_VA_RESERVED_SIZE at the bottom of VM space.
for gfx/sdma mcbp feature,
reserve AMDGPU_VA_RESERVED_SIZ * AMDGPU_VM_MAX_NUM_CTX at the top of VM space.
For sriov, only need to reserve AMDGPU_VA_RESERVED_SIZE at the top.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- 9 files changed, 25 insertions(+), 5 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +8 -0
@@ -24,6 +24,14 @@#include "amdgpu.h" +uint64_t amdgpu_get_reserved_csa_size (struct amdgpu_device *adev) +{ +if (amdgpu_sriov_vf (adev)) +return AMDGPU_VA_RESERVED_SIZE ; +else +return AMDGPU_VA_RESERVED_SIZE *AMDGPU_VM_MAX_NUM_CTX ; +} +uint64_t amdgpu_csa_vaddr (struct amdgpu_device *adev,uint32_t id) {uint64_t addr = adev->vm_manager.max_pfn <<AMDGPU_GPU_PAGE_SHIFT ;
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h +1 -0
@@ -27,6 +27,7 @@#define AMDGPU_CSA_SIZE (128 * 1024) +uint64_t amdgpu_get_reserved_csa_size (struct amdgpu_device *adev);uint32_t amdgpu_get_total_csa_size (struct amdgpu_device *adev);uint64_t amdgpu_csa_vaddr (struct amdgpu_device *adev,uint32_t id); int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo **bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +10 -0
@@ -557,6 +557,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,struct ww_acquire_ctx ticket;struct list_head list, duplicates;uint64_t va_flags; +uint64_t va_reserved, va_top;int r =0 ;if (args->va_address <AMDGPU_VA_RESERVED_SIZE ) {
@@ -565,6 +566,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, args->va_address, AMDGPU_VA_RESERVED_SIZE);return -EINVAL ; } + va_top = adev->vm_manager.max_pfn *AMDGPU_GPU_PAGE_SIZE ; + va_reserved = va_top - adev->vm_manager.reserved_vm_size; + +if (args->va_address > va_reserved && args->va_address < va_top) { +dev_dbg (&dev->pdev->dev, +"va_address 0x%LX is in reserved area 0x%LX\n" , + args->va_address, adev->vm_manager.reserved_vm_size); +return -EINVAL ; + }if (args->va_address >=AMDGPU_GMC_HOLE_START && args->va_address <AMDGPU_GMC_HOLE_END ) {
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +1 -2
@@ -702,7 +702,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.ids_flags |=AMDGPU_IDS_FLAGS_PREEMPTION ; vm_size = adev->vm_manager.max_pfn *AMDGPU_GPU_PAGE_SIZE ; - vm_size -=AMDGPU_VA_RESERVED_SIZE ; + vm_size -= adev->vm_manager.reserved_vm_size;/* Older VCE FW versions are buggy and can handle only 40bits */ if (adev->vce.fw_version &&
@@ -977,7 +977,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto error_vm; } -if (amdgpu_sriov_vf (adev)) {uint64_t csa_addr =amdgpu_csa_vaddr (adev,1 ) &AMDGPU_GMC_HOLE_MASK ; r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +1 -0
@@ -2901,6 +2901,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, } adev->vm_manager.max_pfn = (uint64_t )vm_size <<18 ; + adev->vm_manager.reserved_vm_size =amdgpu_get_reserved_csa_size (adev); tmp =roundup_pow_of_two (adev->vm_manager.max_pfn);if (amdgpu_vm_block_size !=-1 )
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +1 -0
@@ -260,6 +260,7 @@ struct amdgpu_vm_manager {unsigned seqno[AMDGPU_MAX_RINGS ];uint64_t max_pfn; +uint64_t reserved_vm_size;uint32_t num_level;uint32_t block_size;uint32_t fragment_size;
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +1 -1
@@ -471,7 +471,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)if (enable) {uint32_t low =AMDGPU_VA_RESERVED_SIZE >>AMDGPU_GPU_PAGE_SHIFT ;uint32_t high = adev->vm_manager.max_pfn - - (AMDGPU_VA_RESERVED_SIZE >>AMDGPU_GPU_PAGE_SHIFT ); + (adev->vm_manager.reserved_vm_size >>AMDGPU_GPU_PAGE_SHIFT );WREG32 (mmVM_PRT_APERTURE0_LOW_ADDR, low);WREG32 (mmVM_PRT_APERTURE1_LOW_ADDR, low);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +1 -1
@@ -568,7 +568,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)if (enable) {uint32_t low =AMDGPU_VA_RESERVED_SIZE >>AMDGPU_GPU_PAGE_SHIFT ;uint32_t high = adev->vm_manager.max_pfn - - (AMDGPU_VA_RESERVED_SIZE >>AMDGPU_GPU_PAGE_SHIFT ); + (adev->vm_manager.reserved_vm_size >>AMDGPU_GPU_PAGE_SHIFT );WREG32 (mmVM_PRT_APERTURE0_LOW_ADDR, low);WREG32 (mmVM_PRT_APERTURE1_LOW_ADDR, low);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +1 -1
@@ -772,7 +772,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)if (enable) {uint32_t low =AMDGPU_VA_RESERVED_SIZE >>AMDGPU_GPU_PAGE_SHIFT ;uint32_t high = adev->vm_manager.max_pfn - - (AMDGPU_VA_RESERVED_SIZE >>AMDGPU_GPU_PAGE_SHIFT ); + (adev->vm_manager.reserved_vm_size >>AMDGPU_GPU_PAGE_SHIFT );WREG32 (mmVM_PRT_APERTURE0_LOW_ADDR, low);WREG32 (mmVM_PRT_APERTURE1_LOW_ADDR, low);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 4/9 drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr
In reply to a message not in the archiveused to manager the reserverd vm space.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 ++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++++- 3 files changed, 14 insertions(+), 4 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +6 -2
@@ -529,10 +529,14 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,return 0 ; } -void amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr) +int amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr) {mutex_init (&mgr->lock);idr_init (&mgr->ctx_handles); + mgr->resv_vm_bitmap =kzalloc (DIV_ROUND_UP (AMDGPU_VM_MAX_NUM_CTX ,BITS_PER_BYTE ),GFP_KERNEL ); +if (unlikely (!mgr->resv_vm_bitmap)) +return -ENOMEM ; +return 0 ; }void amdgpu_ctx_mgr_entity_flush (struct amdgpu_ctx_mgr *mgr)
@@ -601,7 +605,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)if (kref_put (&ctx->refcount, amdgpu_ctx_fini) !=1 )DRM_ERROR ("ctx %p is still alive\n" , ctx); } - +kfree (mgr->resv_vm_bitmap);idr_destroy (&mgr->ctx_handles);mutex_destroy (&mgr->lock); }
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +3 -1
@@ -38,6 +38,7 @@ struct amdgpu_ctx_entity {struct amdgpu_ctx {struct kref refcount;struct amdgpu_device *adev; +unsigned reset_counter;unsigned reset_counter_query;uint32_t vram_lost_counter;
@@ -56,6 +57,7 @@ struct amdgpu_ctx_mgr {struct mutex lock;/* protected by lock */ struct idr ctx_handles; +unsigned long *resv_vm_bitmap; };extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM ];
@@ -80,7 +82,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,int amdgpu_ctx_wait_prev_fence (struct amdgpu_ctx *ctx,struct drm_sched_entity *entity); -void amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr); +int amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr);void amdgpu_ctx_mgr_entity_fini (struct amdgpu_ctx_mgr *mgr);void amdgpu_ctx_mgr_entity_flush (struct amdgpu_ctx_mgr *mgr);void amdgpu_ctx_mgr_fini (struct amdgpu_ctx_mgr *mgr);
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +5 -1
@@ -988,11 +988,15 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)mutex_init (&fpriv->bo_list_lock);idr_init (&fpriv->bo_list_handles); -amdgpu_ctx_mgr_init (&fpriv->ctx_mgr); +if (amdgpu_ctx_mgr_init (&fpriv->ctx_mgr)) + goto error_ctx_mgr; file_priv->driver_priv = fpriv; goto out_suspend; +error_ctx_mgr: +idr_destroy (&fpriv->bo_list_handles); +mutex_destroy (&fpriv->bo_list_lock); error_vm:amdgpu_vm_fini (adev, &fpriv->vm);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): 1544095957-21101-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org
Re: [PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr
Quoted 14 lines · Rex Zhu
used to manager the reserverd vm space.
Signed-off-by Rex Zhu <[email protected]>--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 ++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++++- 3 files changed, 14 insertions(+), 4 deletions(-)drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +0
-0
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, · line 536
Quoted 9 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +2
-1@@ -529,10 +529,14 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,return 0 ; } -void amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr) +int amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr) {mutex_init (&mgr->lock);idr_init (&mgr->ctx_handles); + mgr->resv_vm_bitmap =kzalloc (DIV_ROUND_UP (AMDGPU_VM_MAX_NUM_CTX ,BITS_PER_BYTE ),GFP_KERNEL );
The bitmap is in (unsigned long) units. So you should round to multiples of (unsigned long), not multiples of byte. Something like this:
mgr->resv_vm_bitmap = kzalloc(DIV_ROUND_UP(AMDGPU_VM_MAX_NUM_CTX, BITS_PER_BYTE * sizeof(unsigned long)) * sizeof(unsigned long), GFP_KERNEL);
Regards,
Felix
Quoted 55 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +4
-1+if (unlikely (!mgr->resv_vm_bitmap)) +return -ENOMEM ; +return 0 ; }void amdgpu_ctx_mgr_entity_flush (struct amdgpu_ctx_mgr *mgr)@@ -601,7 +605,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)if (kref_put (&ctx->refcount, amdgpu_ctx_fini) !=1 )DRM_ERROR ("ctx %p is still alive\n" , ctx); } - +kfree (mgr->resv_vm_bitmap);idr_destroy (&mgr->ctx_handles);mutex_destroy (&mgr->lock); }drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +3
-1@@ -38,6 +38,7 @@ struct amdgpu_ctx_entity {struct amdgpu_ctx {struct kref refcount;struct amdgpu_device *adev; +unsigned reset_counter;unsigned reset_counter_query;uint32_t vram_lost_counter;@@ -56,6 +57,7 @@ struct amdgpu_ctx_mgr {struct mutex lock;/* protected by lock */ struct idr ctx_handles; +unsigned long *resv_vm_bitmap; };extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM ];@@ -80,7 +82,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,int amdgpu_ctx_wait_prev_fence (struct amdgpu_ctx *ctx,struct drm_sched_entity *entity); -void amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr); +int amdgpu_ctx_mgr_init (struct amdgpu_ctx_mgr *mgr);void amdgpu_ctx_mgr_entity_fini (struct amdgpu_ctx_mgr *mgr);void amdgpu_ctx_mgr_entity_flush (struct amdgpu_ctx_mgr *mgr);void amdgpu_ctx_mgr_fini (struct amdgpu_ctx_mgr *mgr);drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +2
-1@@ -988,11 +988,15 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)mutex_init (&fpriv->bo_list_lock);idr_init (&fpriv->bo_list_handles); -amdgpu_ctx_mgr_init (&fpriv->ctx_mgr); +if (amdgpu_ctx_mgr_init (&fpriv->ctx_mgr)) + goto error_ctx_mgr;
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) · line 1002
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +3
-0file_priv->driver_priv = fpriv; goto out_suspend; +error_ctx_mgr: +idr_destroy (&fpriv->bo_list_handles); +mutex_destroy (&fpriv->bo_list_lock); error_vm:amdgpu_vm_fini (adev, &fpriv->vm);
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PATCH 5/9 drm/amdgpu: Delay map sriov csa addr to ctx init
In reply to a message not in the archive1. meet kfd request
2. align with baremetal, in baremetal, driver map csa per ctx.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 -------- 2 files changed, 18 insertions(+), 9 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +18 -1
@@ -68,11 +68,13 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp, }static int amdgpu_ctx_init (struct amdgpu_device *adev, +struct amdgpu_fpriv *fpriv,enum drm_sched_priority priority,struct drm_file *filp,struct amdgpu_ctx *ctx) {unsigned num_entities =amdgput_ctx_total_num_entities (); +uint64_t csa_addr;unsigned i, j;int r;
@@ -86,6 +88,21 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,memset (ctx,0 ,sizeof (*ctx)); ctx->adev = adev; +if (amdgpu_sriov_vf (adev)) { +if (!fpriv->csa_va) { + csa_addr =amdgpu_csa_vaddr (adev,1 ) &AMDGPU_GMC_HOLE_MASK ; + r =amdgpu_map_static_csa (adev, &fpriv->vm, + adev->virt.csa_obj, + &fpriv->csa_va, + csa_addr, +AMDGPU_CSA_SIZE ); +if (r) { +amdgpu_free_static_csa (&adev->virt.csa_obj); +return -EINVAL ; + } + } + } + ctx->fences =kcalloc (amdgpu_sched_jobs * num_entities,sizeof (struct dma_fence *),GFP_KERNEL );if (!ctx->fences)
@@ -255,7 +272,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev, } *id = (uint32_t )r; - r =amdgpu_ctx_init (adev, priority, filp, ctx); + r =amdgpu_ctx_init (adev, fpriv, priority, filp, ctx);if (r) {idr_remove (&mgr->ctx_handles, *id); *id =0 ;
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +0 -8
@@ -977,14 +977,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto error_vm; } -if (amdgpu_sriov_vf (adev)) { -uint64_t csa_addr =amdgpu_csa_vaddr (adev,1 ) &AMDGPU_GMC_HOLE_MASK ; - r =amdgpu_map_static_csa (adev, &fpriv->vm, adev->virt.csa_obj, - &fpriv->csa_va, csa_addr,AMDGPU_CSA_SIZE ); -if (r) - goto error_vm; - } -mutex_init (&fpriv->bo_list_lock);idr_init (&fpriv->bo_list_handles);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 6/9 drm/amdgpu: Create csa per ctx
In reply to a message not in the archivecreate and map csa for gfx/sdma engine to save the middle command buffer when gpu preemption triggered.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 55 ++++++++++++++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++ 3 files changed, 56 insertions(+), 12 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +5 -4
@@ -824,8 +824,9 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)struct amdgpu_device *adev = p->adev;struct amdgpu_vm *vm = &fpriv->vm;struct amdgpu_bo_list_entry *e; -struct amdgpu_bo_va *bo_va; +struct amdgpu_bo_va *bo_va =NULL ;struct amdgpu_bo *bo; +struct amdgpu_ctx *ctx = p->ctx;int r;/* Only for UVD/VCE VM emulation */
@@ -906,11 +907,11 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)if (r)return r; -if (amdgpu_sriov_vf (adev)) { + bo_va =amdgpu_sriov_vf (adev) ? fpriv->csa_va : ctx->csa_va; + +if (bo_va) {struct dma_fence *f; - bo_va = fpriv->csa_va; -BUG_ON (!bo_va); r =amdgpu_vm_bo_update (adev, bo_va, false);if (r)return r;
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +47 -8
100 lines not on this page · raw message
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +4 -0
@@ -38,6 +38,9 @@ struct amdgpu_ctx_entity {struct amdgpu_ctx {struct kref refcount;struct amdgpu_device *adev; +struct amdgpu_ctx_mgr *ctx_mgr; +struct amdgpu_bo *csa_bo; +struct amdgpu_bo_va *csa_va;unsigned reset_counter;unsigned reset_counter_query;
@@ -50,6 +53,7 @@ struct amdgpu_ctx {enum drm_sched_priority override_priority;struct mutex lock;atomic_t guilty; +u32 resv_space_id; };struct amdgpu_ctx_mgr {
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 7/9 drm/amdgpu: Add csa mc address into job structure
In reply to a message not in the archivesave csa mc address in the job, so can patch the address to pm4 when emit_ib even the ctx was freed.
suggested by Christian.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -0
@@ -230,6 +230,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs goto free_all_kdata; } + p->job->csa_mc_addr =amdgpu_csa_vaddr (p->adev, p->ctx->resv_space_id) &AMDGPU_GMC_HOLE_MASK ; +if (p->uf_entry.tv.bo) p->job->uf_addr = uf_offset;kfree (chunk_array);
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +3 -1
@@ -34,6 +34,7 @@ container_of((sched_job), struct amdgpu_job, base)#define AMDGPU_JOB_GET_VMID (job) ((job) ? (job)->vmid : 0) +#define AMDGPU_JOB_GET_CSA_MC_ADDR (job) ((job) ? (job)->csa_mc_addr : 0)struct amdgpu_fence ;
@@ -56,10 +57,11 @@ struct amdgpu_job {uint32_t oa_base, oa_size;uint32_t vram_lost_counter; +/* csa buffer mc address */ +uint64_t csa_mc_addr;/* user fence handling */ uint64_t uf_addr;uint64_t uf_sequence; - }; int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 8/9 drm/amdgpu: Add a argument in emit_cntxcntl interface
In reply to a message not in the archiveadd a point of struct amdgpu_job in emit_cntxcntl interface in order to get the csa mc address per ctx when emit ce metadata in baremetal.
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 +++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 +++- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 20 ++++++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 ++++++++++------ 6 files changed, 31 insertions(+), 19 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +1 -1
@@ -208,7 +208,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, status |=AMDGPU_HAVE_CTX_SWITCH ; status |= job->preamble_status; -amdgpu_ring_emit_cntxcntl (ring, status); +amdgpu_ring_emit_cntxcntl (ring, job, status); }for (i =0 ; i < num_ibs; ++i) {
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +2 -2
@@ -157,7 +157,7 @@ struct amdgpu_ring_funcs {void (*begin_use)(struct amdgpu_ring *ring);void (*end_use)(struct amdgpu_ring *ring);void (*emit_switch_buffer) (struct amdgpu_ring *ring); -void (*emit_cntxcntl) (struct amdgpu_ring *ring,uint32_t flags); +void (*emit_cntxcntl) (struct amdgpu_ring *ring,struct amdgpu_job *job,uint32_t flags);void (*emit_rreg)(struct amdgpu_ring *ring,uint32_t reg);void (*emit_wreg)(struct amdgpu_ring *ring,uint32_t reg,uint32_t val); void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
@@ -236,7 +236,7 @@ struct amdgpu_ring {#define amdgpu_ring_emit_gds_switch (r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))#define amdgpu_ring_emit_hdp_flush (r) (r)->funcs->emit_hdp_flush((r))#define amdgpu_ring_emit_switch_buffer (r) (r)->funcs->emit_switch_buffer((r)) -#define amdgpu_ring_emit_cntxcntl (r, d) (r)->funcs->emit_cntxcntl((r), (d)) +#define amdgpu_ring_emit_cntxcntl (r, job, d) (r)->funcs->emit_cntxcntl((r), (job), (d))#define amdgpu_ring_emit_rreg (r, d) (r)->funcs->emit_rreg((r), (d))#define amdgpu_ring_emit_wreg (r, d, v) (r)->funcs->emit_wreg((r), (d), (v))#define amdgpu_ring_emit_reg_wait (r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +3 -1
@@ -2976,7 +2976,9 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)return clock; } -static void gfx_v6_ring_emit_cntxcntl (struct amdgpu_ring *ring,uint32_t flags) +static void gfx_v6_ring_emit_cntxcntl (struct amdgpu_ring *ring, +struct amdgpu_job *job, +uint32_t flags) {if (flags &AMDGPU_HAVE_CTX_SWITCH )gfx_v6_0_ring_emit_vgt_flush (ring);
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +3 -1
@@ -2275,7 +2275,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,amdgpu_ring_write (ring, control); } -static void gfx_v7_ring_emit_cntxcntl (struct amdgpu_ring *ring,uint32_t flags) +static void gfx_v7_ring_emit_cntxcntl (struct amdgpu_ring *ring, +struct amdgpu_job *job, +uint32_t flags) {uint32_t dw2 =0 ;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +12 -8
@@ -723,8 +723,8 @@ enum {static void gfx_v8_0_set_rlc_funcs (struct amdgpu_device *adev);static u32 gfx_v8_0_get_csb_size (struct amdgpu_device *adev);static void gfx_v8_0_get_cu_info (struct amdgpu_device *adev); -static void gfx_v8_0_ring_emit_ce_meta (struct amdgpu_ring *ring); -static void gfx_v8_0_ring_emit_de_meta (struct amdgpu_ring *ring); +static void gfx_v8_0_ring_emit_ce_meta (struct amdgpu_ring *ring,struct amdgpu_job *job); +static void gfx_v8_0_ring_emit_de_meta (struct amdgpu_ring *ring,struct amdgpu_job *job);static void gfx_v8_0_init_golden_registers (struct amdgpu_device *adev) {
@@ -6127,7 +6127,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, control |=INDIRECT_BUFFER_PRE_ENB (1 );if (!(ib->flags &AMDGPU_IB_FLAG_CE )) -gfx_v8_0_ring_emit_de_meta (ring); +gfx_v8_0_ring_emit_de_meta (ring, job); }amdgpu_ring_write (ring, header);
@@ -6386,12 +6386,14 @@ static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)amdgpu_ring_write (ring,0 ); } -static void gfx_v8_ring_emit_cntxcntl (struct amdgpu_ring *ring,uint32_t flags) +static void gfx_v8_ring_emit_cntxcntl (struct amdgpu_ring *ring, +struct amdgpu_job *job, +uint32_t flags) {uint32_t dw2 =0 ;if (amdgpu_sriov_vf (ring->adev)) -gfx_v8_0_ring_emit_ce_meta (ring); +gfx_v8_0_ring_emit_ce_meta (ring, job); dw2 |=0x80000000 ;/* set load_enable otherwise this package is just NOPs */ if (flags &AMDGPU_HAVE_CTX_SWITCH ) {
@@ -7182,7 +7184,8 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) .funcs = &gfx_v8_0_ip_funcs, }; -static void gfx_v8_0_ring_emit_ce_meta (struct amdgpu_ring *ring) +static void gfx_v8_0_ring_emit_ce_meta (struct amdgpu_ring *ring, +struct amdgpu_job *job) {uint64_t ce_payload_addr;int cnt_ce;
@@ -7196,7 +7199,7 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring) offsetof(struct vi_gfx_meta_data_chained_ib , ce_payload); cnt_ce = (sizeof (ce_payload.chained) >>2 ) +4 -2 ; }else { - ce_payload_addr =amdgpu_csa_vaddr (ring->adev,1 ) + + ce_payload_addr =AMDGPU_JOB_GET_CSA_MC_ADDR (job) + offsetof(struct vi_gfx_meta_data , ce_payload); cnt_ce = (sizeof (ce_payload.regular) >>2 ) +4 -2 ; }
@@ -7211,7 +7214,8 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)amdgpu_ring_write_multiple (ring, (void *)&ce_payload, cnt_ce -2 ); } -static void gfx_v8_0_ring_emit_de_meta (struct amdgpu_ring *ring) +static void gfx_v8_0_ring_emit_de_meta (struct amdgpu_ring *ring, +struct amdgpu_job *job) {uint64_t de_payload_addr, gds_addr, csa_addr;int cnt_de;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +10 -6
@@ -297,7 +297,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info);static uint64_t gfx_v9_0_get_gpu_clock_counter (struct amdgpu_device *adev);static void gfx_v9_0_select_se_sh (struct amdgpu_device *adev,u32 se_num,u32 sh_num,u32 instance); -static void gfx_v9_0_ring_emit_de_meta (struct amdgpu_ring *ring); +static void gfx_v9_0_ring_emit_de_meta (struct amdgpu_ring *ring,struct amdgpu_job *job);static void gfx_v9_0_init_golden_registers (struct amdgpu_device *adev) {
@@ -4067,7 +4067,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, control |=INDIRECT_BUFFER_PRE_ENB (1 );if (!(ib->flags &AMDGPU_IB_FLAG_CE )) -gfx_v9_0_ring_emit_de_meta (ring); +gfx_v9_0_ring_emit_de_meta (ring, job); }amdgpu_ring_write (ring, header);
@@ -4320,7 +4320,8 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)amdgpu_ring_write (ring,0 ); } -static void gfx_v9_0_ring_emit_ce_meta (struct amdgpu_ring *ring) +static void gfx_v9_0_ring_emit_ce_meta (struct amdgpu_ring *ring, +struct amdgpu_job *job) {struct v9_ce_ib_state ce_payload = {0 };uint64_t csa_addr;
@@ -4339,7 +4340,8 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)amdgpu_ring_write_multiple (ring, (void *)&ce_payload,sizeof (ce_payload) >>2 ); } -static void gfx_v9_0_ring_emit_de_meta (struct amdgpu_ring *ring) +static void gfx_v9_0_ring_emit_de_meta (struct amdgpu_ring *ring, +struct amdgpu_job *job) {struct v9_de_ib_state de_payload = {0 };uint64_t csa_addr, gds_addr;
@@ -4367,12 +4369,14 @@ static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)amdgpu_ring_write (ring,FRAME_CMD (start ?0 :1 ));/* frame_end */ } -static void gfx_v9_ring_emit_cntxcntl (struct amdgpu_ring *ring,uint32_t flags) +static void gfx_v9_ring_emit_cntxcntl (struct amdgpu_ring *ring, +struct amdgpu_job *job, +uint32_t flags) {uint32_t dw2 =0 ;if (amdgpu_sriov_vf (ring->adev)) -gfx_v9_0_ring_emit_ce_meta (ring); +gfx_v9_0_ring_emit_ce_meta (ring, job);gfx_v9_0_ring_emit_tmz (ring, true);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 9/9 drm/amdgpu: Remove sriov check when insert ce/de meta_data
In reply to a message not in the archiveto support cp gfx mid-command buffer preemption in baremetal
Signed-off-by Rex Zhu <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 15 ++++++++++----- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 ++++++++++----- 2 files changed, 20 insertions(+), 10 deletions(-)
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +10 -5
@@ -6123,7 +6123,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, control |= ib->length_dw | (vmid <<24 ); -if (amdgpu_sriov_vf (ring->adev) && (ib->flags &AMDGPU_IB_FLAG_PREEMPT )) { +if (ib->flags &AMDGPU_IB_FLAG_PREEMPT ) { control |=INDIRECT_BUFFER_PRE_ENB (1 );if (!(ib->flags &AMDGPU_IB_FLAG_CE ))
@@ -6392,8 +6392,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, {uint32_t dw2 =0 ; -if (amdgpu_sriov_vf (ring->adev)) -gfx_v8_0_ring_emit_ce_meta (ring, job); +gfx_v8_0_ring_emit_ce_meta (ring, job); dw2 |=0x80000000 ;/* set load_enable otherwise this package is just NOPs */ if (flags &AMDGPU_HAVE_CTX_SWITCH ) {
@@ -7194,8 +7193,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring,struct vi_ce_ib_state_chained_ib chained; } ce_payload = {}; +if (!job) +return ; +if (ring->adev->virt.chained_ib_support) { - ce_payload_addr =amdgpu_csa_vaddr (ring->adev,1 ) + + ce_payload_addr =AMDGPU_JOB_GET_CSA_MC_ADDR (job) + offsetof(struct vi_gfx_meta_data_chained_ib , ce_payload); cnt_ce = (sizeof (ce_payload.chained) >>2 ) +4 -2 ; }else {
@@ -7224,7 +7226,10 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring,struct vi_de_ib_state_chained_ib chained; } de_payload = {}; - csa_addr =amdgpu_csa_vaddr (ring->adev,1 ); +if (!job) +return ; + + csa_addr =AMDGPU_JOB_GET_CSA_MC_ADDR (job); gds_addr = csa_addr +4096 ;if (ring->adev->virt.chained_ib_support) { de_payload.chained.gds_backup_addrlo =lower_32_bits (gds_addr);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +10 -5
@@ -4063,7 +4063,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, control |= ib->length_dw | (vmid <<24 ); -if (amdgpu_sriov_vf (ring->adev) && (ib->flags &AMDGPU_IB_FLAG_PREEMPT )) { +if (ib->flags &AMDGPU_IB_FLAG_PREEMPT ) { control |=INDIRECT_BUFFER_PRE_ENB (1 );if (!(ib->flags &AMDGPU_IB_FLAG_CE ))
@@ -4327,8 +4327,11 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring,uint64_t csa_addr;int cnt; +if (!job) +return ; + cnt = (sizeof (ce_payload) >>2 ) +4 -2 ; - csa_addr =amdgpu_csa_vaddr (ring->adev,1 ); + csa_addr =AMDGPU_JOB_GET_CSA_MC_ADDR (job);amdgpu_ring_write (ring,PACKET3 (PACKET3_WRITE_DATA , cnt)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4347,7 +4350,10 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring,uint64_t csa_addr, gds_addr;int cnt; - csa_addr =amdgpu_csa_vaddr (ring->adev,1 ); +if (!job) +return ; + + csa_addr =AMDGPU_JOB_GET_CSA_MC_ADDR (job); gds_addr = csa_addr +4096 ; de_payload.gds_backup_addrlo =lower_32_bits (gds_addr); de_payload.gds_backup_addrhi =upper_32_bits (gds_addr);
@@ -4375,8 +4381,7 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, {uint32_t dw2 =0 ; -if (amdgpu_sriov_vf (ring->adev)) -gfx_v9_0_ring_emit_ce_meta (ring, job); +gfx_v9_0_ring_emit_ce_meta (ring, job);gfx_v9_0_ring_emit_tmz (ring, true);
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1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx