Stratix10 FPGA reconfiguration support

PATCH Superseded chee.hong.ang at intel.com 3 participants 11 messages Nov 29, 2018 – Dec 17, 2018

Subsystems (4)

Arm (32-bit) Arm sub-architectures FPGA manager framework Arm/socfpga architecture

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chee.hong.ang at intel.com

author

2018-11-29 09:40 UTC #0 lore raw

v5 cover Stratix10 FPGA reconfiguration support

From: "Ang, Chee Hong" <[email protected]>

Summary of v5 changes:
- Patch 1/4, 2/4 and 4/4 are unchanged
- Patch 3/4:
- add arch/arm/mach-socfpga/fpga_device.c for Cyclone/Stratix platforms
- remove weak socfpga_fpga_add()

v4 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/347962.html

Ang, Chee Hong (4):
arm: socfpga: stratix10: Add macros for mailbox's arguments
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

 arch/arm/mach-socfpga/Makefile                   |   4 +
 arch/arm/mach-socfpga/fpga_device.c              |  59 +++++
 arch/arm/mach-socfpga/include/mach/fpga_device.h |  15 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |   6 +
 arch/arm/mach-socfpga/include/mach/misc.h        |   6 -
 arch/arm/mach-socfpga/misc.c                     |  31 ---
 arch/arm/mach-socfpga/misc_arria10.c             |   1 +
 arch/arm/mach-socfpga/misc_gen5.c                |   1 +
 arch/arm/mach-socfpga/misc_s10.c                 |   3 +
 configs/socfpga_stratix10_defconfig              |   1 +
 drivers/fpga/Kconfig                             |  11 +
 drivers/fpga/Makefile                            |   1 +
 drivers/fpga/altera.c                            |   6 +
 drivers/fpga/stratix10.c                         | 288 +++++++++++++++++++++++
 include/altera.h                                 |   8 +
 15 files changed, 404 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/fpga_device.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_device.h
 create mode 100644 drivers/fpga/stratix10.c

Signature · 1 line

2.7.4

chee.hong.ang at intel.com

author

2018-11-29 09:40 UTC #1 lore raw

PATCH v5 1/4 arm: socfpga: stratix10: Add macros for mailbox's arguments

From: "Ang, Chee Hong" <[email protected]>

Add macros for specifying number of arguments in mailbox command.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/mach-socfpga/include/mach/mailbox_s10.h +6 -0

index 660df35..ae728a5 100644
@@ -107,6 +107,12 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define RECONFIG_STATUS_PIN_STATUS			2
 #define RECONFIG_STATUS_SOFTFUNC_STATUS			3
 
+/* Macros for specifying number of arguments in mailbox command */
+#define MBOX_NUM_ARGS(n, b)				(((n) & 0xFF) << (b))
+#define MBOX_DIRECT_COUNT(n)				MBOX_NUM_ARGS((n), 0)
+#define MBOX_ARG_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 8)
+#define MBOX_RESP_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 16)
+
 #define MBOX_CFGSTAT_STATE_IDLE				0x00000000
 #define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
 #define MBOX_CFGSTAT_STATE_FAILACK			0x08000000

Signature · 1 line

2.7.4

chee.hong.ang at intel.com

author

2018-11-29 09:40 UTC #2 lore raw

PATCH v5 2/4 arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

In reply to chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable FPGA reconfiguration support for Stratix 10 SoC.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 drivers/fpga/Kconfig     |  11 ++
 drivers/fpga/Makefile    |   1 +
 drivers/fpga/stratix10.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++
 include/altera.h         |   4 +
 4 files changed, 304 insertions(+)
 create mode 100644 drivers/fpga/stratix10.c

drivers/fpga/Kconfig +11 -0

index 50e9019..8f59193 100644
@@ -31,6 +31,17 @@ config FPGA_CYCLON2
 	  Enable FPGA driver for loading bitstream in BIT and BIN format
 	  on Altera Cyclone II device.
 
+config FPGA_STRATIX10
+	bool "Enable Altera FPGA driver for Stratix 10"
+	depends on TARGET_SOCFPGA_STRATIX10
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Altera Stratix 10 FPGA specific driver
+
+	  This provides common functionality for Altera Stratix 10 devices.
+	  Enable FPGA driver for writing bitstream into Altera Stratix10
+	  device.
+
 config FPGA_XILINX
 	bool "Enable Xilinx FPGA drivers"
 	select FPGA

drivers/fpga/Makefile +1 -0

index 97d7d5d..5a778c1 100644
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
 obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
+obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o

drivers/fpga/stratix10.c new file +288 -0

288 lines not on this page · raw message

include/altera.h +4 -0

index ead5d3d..233b467 100644
@@ -116,4 +116,8 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
 int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
 #endif
 
+#ifdef CONFIG_FPGA_STRATIX10
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
 #endif /* _ALTERA_H_ */

Signature · 1 line

2.7.4

chee.hong.ang at intel.com

author

2018-11-29 09:40 UTC #3 lore raw

PATCH v5 3/4 arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

In reply to chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                   |  4 ++
 arch/arm/mach-socfpga/fpga_device.c              | 59 ++++++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++++++
 arch/arm/mach-socfpga/include/mach/misc.h        |  6 ---
 arch/arm/mach-socfpga/misc.c                     | 31 -------------
 arch/arm/mach-socfpga/misc_arria10.c             |  1 +
 arch/arm/mach-socfpga/misc_gen5.c                |  1 +
 arch/arm/mach-socfpga/misc_s10.c                 |  3 ++
 drivers/fpga/altera.c                            |  6 +++
 include/altera.h                                 |  4 ++
 10 files changed, 93 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/fpga_device.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_device.h

arch/arm/mach-socfpga/Makefile +4 -0

index e667204..2ff1b3f 100644
@@ -10,6 +10,10 @@ obj-y	+= clock_manager.o
 obj-y	+= misc.o
 obj-y	+= reset_manager.o
 
+ifdef CONFIG_FPGA
+obj-y	+= fpga_device.o
+endif
+
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= clock_manager_gen5.o
 obj-y	+= misc_gen5.o

arch/arm/mach-socfpga/fpga_device.c new file +59 -0

59 lines not on this page · raw message

arch/arm/mach-socfpga/include/mach/fpga_device.h new file +15 -0

new file mode 100644
index 0000000..fc80cbd
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _FPGA_DEVICE_H_
+#define _FPGA_DEVICE_H_
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#endif /* _FPGA_DEVICE_H_ */

arch/arm/mach-socfpga/include/mach/misc.h +0 -6

index 4fc9570..cb0eb3b 100644
@@ -15,12 +15,6 @@ struct bsel {
 
 extern struct bsel bsel_str[];
 
-#ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
-#else
-static inline void socfpga_fpga_add(void) {}
-#endif
-
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
 void socfpga_sdram_remap_zero(void);
 #endif

arch/arm/mach-socfpga/misc.c +0 ~~-31~~

index a4f6d5c..f493da0 100644
@@ -87,37 +87,6 @@ int overwrite_console(void)
 }
 #endif
 
-#ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
-	{
-		/* Family */
-		Altera_SoCFPGA,
-		/* Interface type */
-		fast_passive_parallel,
-		/* No limitation as additional data will be ignored */
-		-1,
-		/* No device function table */
-		NULL,
-		/* Base interface address specified in driver */
-		NULL,
-		/* No cookie implementation */
-		0
-	},
-};
-
-/* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
-{
-	int i;
-	fpga_init();
-	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
-		fpga_add(fpga_altera, &altera_fpga[i]);
-}
-#endif
-
 int arch_cpu_init(void)
 {
 #ifdef CONFIG_HW_WATCHDOG

arch/arm/mach-socfpga/misc_arria10.c +1 -0

index f347ae8..6c4eb31 100644
@@ -17,6 +17,7 @@
 #include <asm/arch/reset_manager_arria10.h>
 #include <asm/arch/sdram_arria10.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_device.h>
 #include <asm/arch/nic301.h>
 #include <asm/io.h>
 #include <asm/pl310.h>

arch/arm/mach-socfpga/misc_gen5.c +1 -0

index 429c3d6..9e0eeb7 100644
@@ -17,6 +17,7 @@
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_device.h>
 #include <asm/arch/nic301.h>
 #include <asm/arch/scu.h>
 #include <asm/pl310.h>

arch/arm/mach-socfpga/misc_s10.c +3 -0

index e599362..fce9077 100644
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_device.h>
 #include <asm/arch/misc.h>
 #include <asm/pl310.h>
 #include <linux/libfdt.h>

@@ -125,6 +126,8 @@ int arch_misc_init(void)
 
 int arch_early_init_r(void)
 {
+	socfpga_fpga_add();
+
 	return 0;
 }

drivers/fpga/altera.c +6 -0

index 9605554..7c8f518 100644
@@ -39,6 +39,9 @@ static const struct altera_fpga {
 #if defined(CONFIG_FPGA_STRATIX_V)
 	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
 #endif
+#if defined(CONFIG_FPGA_STRATIX10)
+	{ Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
+#endif
 #if defined(CONFIG_FPGA_SOCFPGA)
 	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
 #endif

@@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc)
 	case fast_passive_parallel_security:
 		printf("Fast Passive Parallel with Security (FPPS)\n");
 		break;
+	case secure_device_manager_mailbox:
+		puts("Secure Device Manager (SDM) Mailbox\n");
+		break;
 		/* Add new interface types here */
 	default:
 		printf("Unsupported interface type, %d\n", desc->iface);

include/altera.h +4 -0

index 233b467..22d55cf 100644
@@ -39,6 +39,8 @@ enum altera_iface {
 	fast_passive_parallel,
 	/* fast passive parallel with security (FPPS) */
 	fast_passive_parallel_security,
+	/* secure device manager (SDM) mailbox */
+	secure_device_manager_mailbox,
 	/* insert all new types before this */
 	max_altera_iface_type,
 };

@@ -54,6 +56,8 @@ enum altera_family {
 	Altera_StratixII,
 	/* StratixV Family */
 	Altera_StratixV,
+	/* Stratix10 Family */
+	Intel_FPGA_Stratix10,
 	/* SoCFPGA Family */
 	Altera_SoCFPGA,

Signature · 1 line

2.7.4

Marek Vasut

2018-11-29 11:28 UTC #4 lore raw

PATCH v5 3/4 arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

Quoted 90 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                   |  4 ++
 arch/arm/mach-socfpga/fpga_device.c              | 59 ++++++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++++++
 arch/arm/mach-socfpga/include/mach/misc.h        |  6 ---
 arch/arm/mach-socfpga/misc.c                     | 31 -------------
 arch/arm/mach-socfpga/misc_arria10.c             |  1 +
 arch/arm/mach-socfpga/misc_gen5.c                |  1 +
 arch/arm/mach-socfpga/misc_s10.c                 |  3 ++
 drivers/fpga/altera.c                            |  6 +++
 include/altera.h                                 |  4 ++
 10 files changed, 93 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/fpga_device.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_device.h

arch/arm/mach-socfpga/Makefile +4 -0

index e667204..2ff1b3f 100644
@@ -10,6 +10,10 @@ obj-y	+= clock_manager.o
 obj-y	+= misc.o
 obj-y	+= reset_manager.o
 
+ifdef CONFIG_FPGA
+obj-y	+= fpga_device.o
+endif
+
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= clock_manager_gen5.o
 obj-y	+= misc_gen5.o

arch/arm/mach-socfpga/fpga_device.c new file +48 -0

new file mode 100644
index 0000000..97b27eb
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <altera.h>
+
+#ifdef CONFIG_FPGA_STRATIX10
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_Stratix10,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+#else
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};

arch/arm/mach-socfpga/fpga_device.c line 58

Quoted 10 lines

arch/arm/mach-socfpga/fpga_device.c new file +10 -0

+#endif
+
+/* add device descriptor to FPGA device table */
+void socfpga_fpga_add(void)
+{
+	int i;
+
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);

Why do we need this loop if there's only one entry in the array ?

btw this function could stay in misc.c , the altera_fpga tables could be in misc_s10.c resp. something for Gen5 IMO, so you won't need another new file.

Signature · 2 lines

Best regards,
Marek Vasut

Ang

2018-12-17 06:38 UTC #5 lore raw

PATCH v5 3/4 arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

Quoted 102 lines · Marek Vasut

Quoted 101 lines · chee.hong.ang at intel.com
From: "Ang, Chee Hong" <[email protected]>
Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC.
Signed-off-by Ang, Chee Hong <[email protected]>
---
arch/arm/mach-socfpga/Makefile                   |  4 ++ arch/arm/mach-socfpga/fpga_device.c              | 59
++++++++++++++++++++++++
arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++++++ arch/arm/mach-socfpga/include/mach/misc.h        |  6 --- arch/arm/mach-socfpga/misc.c                     | 31 ------------ -
arch/arm/mach-socfpga/misc_arria10.c             |  1 + arch/arm/mach-socfpga/misc_gen5.c                |  1 + arch/arm/mach-socfpga/misc_s10.c                 |  3 ++ drivers/fpga/altera.c                            |  6 +++ include/altera.h                                 |  4 ++
 10 files changed, 93 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/mach-socfpga/fpga_device.c create mode 100644 arch/arm/mach- socfpga/include/mach/fpga_device.h
arch/arm/mach- renamed from arch/arm/mach-socfpga/Makefile +0 -0
socfpga/Makefile
index e667204..2ff1b3f 100644
arch/arm/mach-socfpga/Makefile +0 -0
@@ -10,6 +10,10 @@ obj-y	+= clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
arch/arm/mach-socfpga/Makefile +4 -0
+ifdef CONFIG_FPGA
+obj-y	+= fpga_device.o
+endif
+
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
obj-y += misc_gen5.o
arch/arm/mach- renamed from arch/arm/mach-socfpga/fpga_device.c +0 -0
socfpga/fpga_device.c
new file mode 100644
index 0000000..97b27eb
arch/arm/mach-socfpga/fpga_device.c new file +19 -0
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <altera.h>
+
+#ifdef CONFIG_FPGA_STRATIX10
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_Stratix10,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be
ignored */
arch/arm/mach-socfpga/fpga_device.c new file +20 -0
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+#else
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be
ignored */
arch/arm/mach-socfpga/fpga_device.c new file +12 -0
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+#endif
+
+/* add device descriptor to FPGA device table */

Quoted 8 lines

arch/arm/mach-socfpga/fpga_device.c line 58
Quoted 7 lines
arch/arm/mach-socfpga/fpga_device.c new file +7 -0
+void socfpga_fpga_add(void)
+{
+	int i;
+
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);
Why do we need this loop if there's only one entry in the array ?

This ensure we have support for future platforms which might have more than 1 FPGA devices on the platform.

Quoted 4 lines

btw this function could stay in misc.c , the altera_fpga tables could be
in misc_s10.c resp. something for Gen5 IMO, so you won't need another new file.

Yes. This will be addressed in v6 patchsets.

Marek Vasut

2018-12-17 13:04 UTC #6 lore raw

PATCH v5 3/4 arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

Quoted 111 lines · Chee Hong

Quoted 102 lines · Marek Vasut
Quoted 101 lines · chee.hong.ang at intel.com
From: "Ang, Chee Hong" <[email protected]>
Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC.
Signed-off-by Ang, Chee Hong <[email protected]>
---
arch/arm/mach-socfpga/Makefile                   |  4 ++ arch/arm/mach-socfpga/fpga_device.c              | 59
++++++++++++++++++++++++
arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++++++ arch/arm/mach-socfpga/include/mach/misc.h        |  6 --- arch/arm/mach-socfpga/misc.c                     | 31 ------------ -
arch/arm/mach-socfpga/misc_arria10.c             |  1 + arch/arm/mach-socfpga/misc_gen5.c                |  1 + arch/arm/mach-socfpga/misc_s10.c                 |  3 ++ drivers/fpga/altera.c                            |  6 +++ include/altera.h                                 |  4 ++
 10 files changed, 93 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/mach-socfpga/fpga_device.c create mode 100644 arch/arm/mach- socfpga/include/mach/fpga_device.h
arch/arm/mach- renamed from arch/arm/mach-socfpga/Makefile +0 -0
socfpga/Makefile
index e667204..2ff1b3f 100644
arch/arm/mach-socfpga/Makefile +0 -0
@@ -10,6 +10,10 @@ obj-y	+= clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
arch/arm/mach-socfpga/Makefile +4 -0
+ifdef CONFIG_FPGA
+obj-y	+= fpga_device.o
+endif
+
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
obj-y += misc_gen5.o
arch/arm/mach- renamed from arch/arm/mach-socfpga/fpga_device.c +0 -0
socfpga/fpga_device.c
new file mode 100644
index 0000000..97b27eb
arch/arm/mach-socfpga/fpga_device.c new file +19 -0
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <altera.h>
+
+#ifdef CONFIG_FPGA_STRATIX10
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_Stratix10,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be
ignored */
arch/arm/mach-socfpga/fpga_device.c new file +20 -0
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+#else
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be
ignored */
arch/arm/mach-socfpga/fpga_device.c new file +12 -0
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+#endif
+
+/* add device descriptor to FPGA device table */
Quoted 8 lines
arch/arm/mach-socfpga/fpga_device.c line 58
Quoted 7 lines
arch/arm/mach-socfpga/fpga_device.c new file +7 -0
+void socfpga_fpga_add(void)
+{
+	int i;
+
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);
Why do we need this loop if there's only one entry in the array ?

Quoted 2 lines

This ensure we have support for future platforms which might have more than 1 FPGA devices on the platform.

Please add it in the future, _when_ such a setup exists.

Quoted 6 lines

Quoted 4 lines
btw this function could stay in misc.c , the altera_fpga tables could be
in misc_s10.c resp. something for Gen5 IMO, so you won't need another new file.
Yes. This will be addressed in v6 patchsets.

Signature · 2 lines

Best regards,
Marek Vasut

chee.hong.ang at intel.com

author

2018-11-29 09:40 UTC #7 lore raw

PATCH v5 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

In reply to chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 configs/socfpga_stratix10_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/socfpga_stratix10_defconfig +1 -0

index 5f3d733..155c406 100644
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set

Signature · 1 line

2.7.4

Marek Vasut

2018-11-29 11:25 UTC #8 lore raw

v5 cover Stratix10 FPGA reconfiguration support

In reply to chee.hong.ang at intel.com

Quoted 28 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>
Summary of v5 changes:
- Patch 1/4, 2/4 and 4/4 are unchanged
- Patch 3/4:
- add arch/arm/mach-socfpga/fpga_device.c for Cyclone/Stratix platforms
- remove weak socfpga_fpga_add()
v4 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/347962.html
Ang, Chee Hong (4):
arm: socfpga: stratix10: Add macros for mailbox's arguments
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
 arch/arm/mach-socfpga/Makefile                   |   4 +
 arch/arm/mach-socfpga/fpga_device.c              |  59 +++++
 arch/arm/mach-socfpga/include/mach/fpga_device.h |  15 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |   6 +
 arch/arm/mach-socfpga/include/mach/misc.h        |   6 -
 arch/arm/mach-socfpga/misc.c                     |  31 ---
 arch/arm/mach-socfpga/misc_arria10.c             |   1 +
 arch/arm/mach-socfpga/misc_gen5.c                |   1 +
 arch/arm/mach-socfpga/misc_s10.c                 |   3 +
 configs/socfpga_stratix10_defconfig              |   1 +
 drivers/fpga/Kconfig                             |  11 +

Quoted 9 lines

 drivers/fpga/Makefile                            |   1 +
 drivers/fpga/altera.c                            |   6 +
 drivers/fpga/stratix10.c                         | 288 +++++++++++++++++++++++
 include/altera.h                                 |   8 +
 15 files changed, 404 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/fpga_device.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_device.h
 create mode 100644 drivers/fpga/stratix10.c

Is this fixing the build errors I reported recently ?

Signature · 2 lines

Best regards,
Marek Vasut

Ang

2018-12-17 06:36 UTC #9 lore raw

v5 cover Stratix10 FPGA reconfiguration support

Quoted 44 lines · Marek Vasut

Quoted 37 lines · chee.hong.ang at intel.com
From: "Ang, Chee Hong" <[email protected]>
Summary of v5 changes:
- Patch 1/4, 2/4 and 4/4 are unchanged
- Patch 3/4:
- add arch/arm/mach-socfpga/fpga_device.c for Cyclone/Stratix platforms
- remove weak socfpga_fpga_add()
v4 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/347962.html
Ang, Chee Hong (4):
arm: socfpga: stratix10: Add macros for mailbox's arguments
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/fpga_device.c | 59 +++++ arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++ arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 + arch/arm/mach-socfpga/include/mach/misc.h | 6 - arch/arm/mach-socfpga/misc.c | 31 --- arch/arm/mach-socfpga/misc_arria10.c | 1 + arch/arm/mach-socfpga/misc_gen5.c | 1 + arch/arm/mach-socfpga/misc_s10.c | 3 + configs/socfpga_stratix10_defconfig | 1 + drivers/fpga/Kconfig | 11 + drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 6 + drivers/fpga/stratix10.c | 288
+++++++++++++++++++++++
include/altera.h | 8 +
Quoted 6 lines
 15 files changed, 404 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/mach-socfpga/fpga_device.c create mode 100644 arch/arm/mach- socfpga/include/mach/fpga_device.h
create mode 100644 drivers/fpga/stratix10.c

Quoted 1 line

Is this fixing the build errors I reported recently ?

This patchsets only address the coding styles/structures of FPGA configurations for all Intel/Altera FPGA platforms. What sort of build errors you encountered recently ?

Marek Vasut

2018-12-17 13:12 UTC #10 lore raw

v5 cover Stratix10 FPGA reconfiguration support

Quoted 45 lines · Chee Hong

Quoted 44 lines · Marek Vasut
Quoted 43 lines · chee.hong.ang at intel.com
From: "Ang, Chee Hong" <[email protected]>
Summary of v5 changes:
- Patch 1/4, 2/4 and 4/4 are unchanged
- Patch 3/4:
- add arch/arm/mach-socfpga/fpga_device.c for Cyclone/Stratix platforms
- remove weak socfpga_fpga_add()
v4 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/347962.html
Ang, Chee Hong (4):
arm: socfpga: stratix10: Add macros for mailbox's arguments
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/fpga_device.c | 59 +++++ arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++ arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 + arch/arm/mach-socfpga/include/mach/misc.h | 6 - arch/arm/mach-socfpga/misc.c | 31 --- arch/arm/mach-socfpga/misc_arria10.c | 1 + arch/arm/mach-socfpga/misc_gen5.c | 1 + arch/arm/mach-socfpga/misc_s10.c | 3 + configs/socfpga_stratix10_defconfig | 1 + drivers/fpga/Kconfig | 11 + drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 6 + drivers/fpga/stratix10.c | 288
+++++++++++++++++++++++
include/altera.h | 8 +
 15 files changed, 404 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/mach-socfpga/fpga_device.c create mode 100644 arch/arm/mach- socfpga/include/mach/fpga_device.h
create mode 100644 drivers/fpga/stratix10.c

Quoted 4 lines

Quoted 1 line
Is this fixing the build errors I reported recently ?
This patchsets only address the coding styles/structures of FPGA configurations for all Intel/Altera FPGA platforms. What sort of build errors you encountered recently ?

https://travis-ci.org/marex/u-boot-socfpga/jobs/449838082#L1079

Signature · 2 lines

Best regards,
Marek Vasut