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Stratix10 FPGA reconfiguration support

PATCH Superseded chee.hong.ang at intel.com 3 participants 13 messages Dec 18, 2018 – Dec 19, 2018

Subsystems (4)
Arm (32-bit) Arm sub-architectures FPGA manager framework Arm/socfpga architecture

v6 of 8 Superseded Latest is v8 →

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chee.hong.ang at intel.com

author
#0 lore raw

v6 cover Stratix10 FPGA reconfiguration support

From: "Ang, Chee Hong" <[email protected]>

Summary of v6 changes:
- Patch 1/4 and 4/4 are unchanged
- Patch 2/4:
- fixed compilation warnings in drivers/fpga/stratix10.c
- Patch 3/4:
- socfpga_fpga_add() in misc.c
- define fpga descriptor structure in misc_arria10.c, misc_gen5.c & misc_s10.c respectively
- removed for-loop in socfpga_fpga_add() (only 1 FPGA device added)

v5 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/349670.html

Ang, Chee Hong (4):
arm: socfpga: stratix10: Add macros for mailbox's arguments
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |   6 +
 arch/arm/mach-socfpga/include/mach/misc.h        |   4 +-
 arch/arm/mach-socfpga/misc.c                     |  26 +-
 arch/arm/mach-socfpga/misc_arria10.c             |  22 +-
 arch/arm/mach-socfpga/misc_gen5.c                |  22 +-
 arch/arm/mach-socfpga/misc_s10.c                 |  22 ++
 configs/socfpga_stratix10_defconfig              |   1 +
 drivers/fpga/Kconfig                             |  11 +
 drivers/fpga/Makefile                            |   1 +
 drivers/fpga/altera.c                            |   6 +
 drivers/fpga/stratix10.c                         | 288 +++++++++++++++++++++++
 include/altera.h                                 |   8 +
 12 files changed, 389 insertions(+), 28 deletions(-)
 create mode 100644 drivers/fpga/stratix10.c
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH v6 1/4 arm: socfpga: stratix10: Add macros for mailbox's arguments

From: "Ang, Chee Hong" <[email protected]>

Add macros for specifying number of arguments in mailbox command.

Signed-off-by Ang, Chee Hong <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/mach-socfpga/include/mach/mailbox_s10.h +6 -0
index 660df35..ae728a5 100644
@@ -107,6 +107,12 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define RECONFIG_STATUS_PIN_STATUS			2
 #define RECONFIG_STATUS_SOFTFUNC_STATUS			3
 
+/* Macros for specifying number of arguments in mailbox command */
+#define MBOX_NUM_ARGS(n, b)				(((n) & 0xFF) << (b))
+#define MBOX_DIRECT_COUNT(n)				MBOX_NUM_ARGS((n), 0)
+#define MBOX_ARG_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 8)
+#define MBOX_RESP_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 16)
+
 #define MBOX_CFGSTAT_STATE_IDLE				0x00000000
 #define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
 #define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
Signature · 1 line
2.7.4
author
#2 lore raw

PATCH v6 2/4 arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

In reply to chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable FPGA reconfiguration support for Stratix 10 SoC.

Signed-off-by Ang, Chee Hong <[email protected]>
---
 drivers/fpga/Kconfig     |  11 ++
 drivers/fpga/Makefile    |   1 +
 drivers/fpga/stratix10.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++
 include/altera.h         |   4 +
 4 files changed, 304 insertions(+)
 create mode 100644 drivers/fpga/stratix10.c
drivers/fpga/Kconfig +11 -0
index 50e9019..8f59193 100644
@@ -31,6 +31,17 @@ config FPGA_CYCLON2
 	  Enable FPGA driver for loading bitstream in BIT and BIN format
 	  on Altera Cyclone II device.
 
+config FPGA_STRATIX10
+	bool "Enable Altera FPGA driver for Stratix 10"
+	depends on TARGET_SOCFPGA_STRATIX10
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Altera Stratix 10 FPGA specific driver
+
+	  This provides common functionality for Altera Stratix 10 devices.
+	  Enable FPGA driver for writing bitstream into Altera Stratix10
+	  device.
+
 config FPGA_XILINX
 	bool "Enable Xilinx FPGA drivers"
 	select FPGA
drivers/fpga/Makefile +1 -0
index 97d7d5d..5a778c1 100644
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
 obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
+obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
drivers/fpga/stratix10.c new file +288 -0

288 lines not on this page · raw message

include/altera.h +4 -0
index ead5d3d..233b467 100644
@@ -116,4 +116,8 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
 int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
 #endif
 
+#ifdef CONFIG_FPGA_STRATIX10
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
 #endif /* _ALTERA_H_ */
Signature · 1 line
2.7.4
author
#3 lore raw

PATCH v6 3/4 arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

In reply to chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC.

Signed-off-by Ang, Chee Hong <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/misc.h |  4 ++--
 arch/arm/mach-socfpga/misc.c              | 26 ++------------------------
 arch/arm/mach-socfpga/misc_arria10.c      | 22 +++++++++++++++++++++-
 arch/arm/mach-socfpga/misc_gen5.c         | 22 +++++++++++++++++++++-
 arch/arm/mach-socfpga/misc_s10.c          | 22 ++++++++++++++++++++++
 drivers/fpga/altera.c                     |  6 ++++++
 include/altera.h                          |  4 ++++
 7 files changed, 78 insertions(+), 28 deletions(-)
arch/arm/mach-socfpga/include/mach/misc.h +2 -2
index 4fc9570..3964831 100644
@@ -16,9 +16,9 @@ struct bsel {
 extern struct bsel bsel_str[];
 
 #ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
+void socfpga_fpga_add(void *fpga_desc);
 #else
-static inline void socfpga_fpga_add(void) {}
+inline void socfpga_fpga_add(void *fpga_desc) {}
 #endif
 
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
arch/arm/mach-socfpga/misc.c +2 -24
index a4f6d5c..78fbe28 100644
@@ -88,33 +88,11 @@ int overwrite_console(void)
 #endif
 
 #ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
-	{
-		/* Family */
-		Altera_SoCFPGA,
-		/* Interface type */
-		fast_passive_parallel,
-		/* No limitation as additional data will be ignored */
-		-1,
-		/* No device function table */
-		NULL,
-		/* Base interface address specified in driver */
-		NULL,
-		/* No cookie implementation */
-		0
-	},
-};
-
 /* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
+void socfpga_fpga_add(void *fpga_desc)
 {
-	int i;
 	fpga_init();
-	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
-		fpga_add(fpga_altera, &altera_fpga[i]);
+	fpga_add(fpga_altera, fpga_desc);
 }
 #endif
arch/arm/mach-socfpga/misc_arria10.c +21 -1
index f347ae8..430e2b4 100644
@@ -37,6 +37,26 @@ static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
 	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
 
 /*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+/*
 + * This function initializes security policies to be consistent across
 + * all logic units in the Arria 10.
 + *

@@ -73,7 +93,7 @@ void socfpga_sdram_remap_zero(void)
 int arch_early_init_r(void)
 {
 	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
+	socfpga_fpga_add(&altera_fpga[0]);
 
 	return 0;
 }
arch/arm/mach-socfpga/misc_gen5.c +21 -1
index 429c3d6..21f5ac3 100644
@@ -35,6 +35,26 @@ static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
 /*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+/*
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE

@@ -214,7 +234,7 @@ int arch_early_init_r(void)
 	socfpga_sdram_remap_zero();
 
 	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
+	socfpga_fpga_add(&altera_fpga[0]);
 
 #ifdef CONFIG_DESIGNWARE_SPI
 	/* Get Designware SPI controller out of reset */
arch/arm/mach-socfpga/misc_s10.c +22 -0
index e599362..113eace 100644
@@ -25,6 +25,26 @@ static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_Stratix10,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+/*
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE

@@ -125,6 +145,8 @@ int arch_misc_init(void)
 
 int arch_early_init_r(void)
 {
+	socfpga_fpga_add(&altera_fpga[0]);
+
 	return 0;
 }
drivers/fpga/altera.c +6 -0
index 9605554..7c8f518 100644
@@ -39,6 +39,9 @@ static const struct altera_fpga {
 #if defined(CONFIG_FPGA_STRATIX_V)
 	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
 #endif
+#if defined(CONFIG_FPGA_STRATIX10)
+	{ Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
+#endif
 #if defined(CONFIG_FPGA_SOCFPGA)
 	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
 #endif

@@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc)
 	case fast_passive_parallel_security:
 		printf("Fast Passive Parallel with Security (FPPS)\n");
 		break;
+	case secure_device_manager_mailbox:
+		puts("Secure Device Manager (SDM) Mailbox\n");
+		break;
 		/* Add new interface types here */
 	default:
 		printf("Unsupported interface type, %d\n", desc->iface);
include/altera.h +4 -0
index 233b467..22d55cf 100644
@@ -39,6 +39,8 @@ enum altera_iface {
 	fast_passive_parallel,
 	/* fast passive parallel with security (FPPS) */
 	fast_passive_parallel_security,
+	/* secure device manager (SDM) mailbox */
+	secure_device_manager_mailbox,
 	/* insert all new types before this */
 	max_altera_iface_type,
 };

@@ -54,6 +56,8 @@ enum altera_family {
 	Altera_StratixII,
 	/* StratixV Family */
 	Altera_StratixV,
+	/* Stratix10 Family */
+	Intel_FPGA_Stratix10,
 	/* SoCFPGA Family */
 	Altera_SoCFPGA,
Signature · 1 line
2.7.4
author
#4 lore raw

PATCH v6 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

In reply to chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>
---
 configs/socfpga_stratix10_defconfig | 1 +
 1 file changed, 1 insertion(+)
configs/socfpga_stratix10_defconfig +1 -0
index 5f3d733..155c406 100644
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
Signature · 1 line
2.7.4
#5 lore raw

PATCH v6 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Quoted 15 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>
---
 configs/socfpga_stratix10_defconfig | 1 +
 1 file changed, 1 insertion(+)
configs/socfpga_stratix10_defconfig +0 -0
index 5f3d733..155c406 100644

configs/socfpga_stratix10_defconfig CONFIG_NR_DRAM_BANKS=1 · line 16

Quoted 7 lines
configs/socfpga_stratix10_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set

Can you send a subsequent patch which uses Kconfig imply to select FPGA_STRATIX10 on S10 instead of adding it in defconfig ?

Signature · 2 lines
Best regards,
Marek Vasut
#6 lore raw

PATCH v6 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Quoted 11 lines · Marek Vasut
Quoted 10 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 configs/socfpga_stratix10_defconfig | 1 +

 1 file changed, 1 insertion(+)
Quoted 16 lines
Quoted 6 lines
configs/socfpga_stratix10_defconfig +0 -0
index 5f3d733..155c406 100644
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
Quoted 8 lines

 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set

Can you send a subsequent patch which uses Kconfig imply to select FPGA_STRATIX10 on S10 instead of adding it in defconfig ?

Noted. Will address this in next patchsets.

#7 lore raw

PATCH v6 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Quoted 28 lines · Chee Hong
Quoted 11 lines · Marek Vasut
Quoted 10 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 configs/socfpga_stratix10_defconfig | 1 +

 1 file changed, 1 insertion(+)
Quoted 16 lines
Quoted 6 lines
configs/socfpga_stratix10_defconfig +0 -0
index 5f3d733..155c406 100644
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
Quoted 8 lines

 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set

Can you send a subsequent patch which uses Kconfig imply to select FPGA_STRATIX10 on S10 instead of adding it in defconfig ?

Quoted 1 line

Noted. Will address this in next patchsets.

I asked you for an incremental patch, not for reposting the whole patchset (also, please track changelog with new versions of patches).

But travis would seem to indicate, again, that the patches break some other target [1]. Can you please at least build test the next version of patches on all systems before posting them ?

You can very well just set up the travis CI with your github repo/fork of u-boot repo, push a branch there and wait for travis to build that branch on all supported systems and tell you what the situation is. It saves me time, which I otherwise spend on applying, rejecting and dropping of your patches after they fail to build.

[1] https://travis-ci.org/marex/u-boot-socfpga/jobs/469629378#L1142

Signature · 2 lines
Best regards,
Marek Vasut
#8 lore raw

PATCH v6 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Quoted 50 lines · Marek Vasut
Quoted 32 lines · Chee Hong
Quoted 22 lines · Marek Vasut
Quoted 20 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 configs/socfpga_stratix10_defconfig | 1 +

 1 file changed, 1 insertion(+)
configs/socfpga_stratix10_defconfig +0 -0
index 5f3d733..155c406 100644
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1

 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y

Quoted 8 lines
Quoted 5 lines

+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set

Can you send a subsequent patch which uses Kconfig imply to select
FPGA_STRATIX10 on S10 instead of adding it in defconfig ?

Quoted 1 line

Noted. Will address this in next patchsets.

I asked you for an incremental patch, not for reposting the whole patchset (also, please track changelog with new versions of patches).

But travis would seem to indicate, again, that the patches break some other target [1]. Can you please at least build test the next version of
patches on all systems before posting them ?

You can very well just set up the travis CI with your github repo/fork
of u-boot repo, push a branch there and wait for travis to build that branch on all supported systems and tell you what the situation is. It
saves me time, which I otherwise spend on applying, rejecting and dropping of your patches after they fail to build.

Quoted 1 line

[1] https://travis-ci.org/marex/u-boot-socfpga/jobs/469629378#L1142

Ok. I only test the build for current (S10) target. Some of the code are not tested with other build target. I will setup the travis CI and test it on my side before submitting new patchsets.
But 1 of the build error is due to your code base missing the following patch:
http://u-boot.10912.n7.nabble.com/PATCH-v2-Add-generic-FPGA-reconfig-ma
ilbox-API-for-S10-td343559.html#a343560
All current patch has dependency on the patch mentioned above. You will get build errors without this patch applied before current patchsets.

Quoted 1 line
#9 lore raw

PATCH v6 4/4 arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Quoted 53 lines · Chee Hong
Quoted 50 lines · Marek Vasut
Quoted 32 lines · Chee Hong
Quoted 22 lines · Marek Vasut
Quoted 20 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Enable Stratix10 FPGA reconfiguration support in defconfig.

Signed-off-by Ang, Chee Hong <[email protected]>

---
 configs/socfpga_stratix10_defconfig | 1 +

 1 file changed, 1 insertion(+)
configs/socfpga_stratix10_defconfig +0 -0
index 5f3d733..155c406 100644
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1

 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y

Quoted 8 lines
Quoted 5 lines

+CONFIG_FPGA_STRATIX10=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set

Can you send a subsequent patch which uses Kconfig imply to select
FPGA_STRATIX10 on S10 instead of adding it in defconfig ?

Quoted 1 line

Noted. Will address this in next patchsets.

I asked you for an incremental patch, not for reposting the whole patchset (also, please track changelog with new versions of patches).

But travis would seem to indicate, again, that the patches break some other target [1]. Can you please at least build test the next version of
patches on all systems before posting them ?

You can very well just set up the travis CI with your github repo/fork
of u-boot repo, push a branch there and wait for travis to build that branch on all supported systems and tell you what the situation is. It
saves me time, which I otherwise spend on applying, rejecting and dropping of your patches after they fail to build.

Quoted 1 line

[1] https://travis-ci.org/marex/u-boot-socfpga/jobs/469629378#L1142

Quoted 10 lines

Ok. I only test the build for current (S10) target. Some of the code are not tested with other build target. I will setup the travis CI and test it on my side before submitting new patchsets.
But 1 of the build error is due to your code base missing the following patch:
http://u-boot.10912.n7.nabble.com/PATCH-v2-Add-generic-FPGA-reconfig-ma
ilbox-API-for-S10-td343559.html#a343560
All current patch has dependency on the patch mentioned above. You will get build errors without this patch applied before current patchsets.

Then please submit the complete series, the dependency is not mentioned anywhere. And yes, please do keep testing.

Signature · 2 lines
Best regards,
Marek Vasut
#10 lore raw

v6 cover Stratix10 FPGA reconfiguration support

In reply to chee.hong.ang at intel.com
Quoted 21 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Summary of v6 changes:
- Patch 1/4 and 4/4 are unchanged
- Patch 2/4:
- fixed compilation warnings in drivers/fpga/stratix10.c
- Patch 3/4:
- socfpga_fpga_add() in misc.c
- define fpga descriptor structure in misc_arria10.c, misc_gen5.c & misc_s10.c respectively
- removed for-loop in socfpga_fpga_add() (only 1 FPGA device added)

v5 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/349670.html

Ang, Chee Hong (4):
arm: socfpga: stratix10: Add macros for mailbox's arguments
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Quoted 14 lines
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |   6 +
 arch/arm/mach-socfpga/include/mach/misc.h        |   4 +-
 arch/arm/mach-socfpga/misc.c                     |  26 +-
 arch/arm/mach-socfpga/misc_arria10.c             |  22 +-
 arch/arm/mach-socfpga/misc_gen5.c                |  22 +-
 arch/arm/mach-socfpga/misc_s10.c                 |  22 ++
 configs/socfpga_stratix10_defconfig              |   1 +
 drivers/fpga/Kconfig                             |  11 +
 drivers/fpga/Makefile                            |   1 +
 drivers/fpga/altera.c                            |   6 +
 drivers/fpga/stratix10.c                         | 288 +++++++++++++++++++++++
 include/altera.h                                 |   8 +
 12 files changed, 389 insertions(+), 28 deletions(-)
 create mode 100644 drivers/fpga/stratix10.c

I take it this fixes the previous stratix 10 build breakage, right ? let's see what travis says.

Signature · 2 lines
Best regards,
Marek Vasut
#11 lore raw

v6 cover Stratix10 FPGA reconfiguration support

Quoted 42 lines · Marek Vasut
Quoted 39 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Summary of v6 changes:
- Patch 1/4 and 4/4 are unchanged
- Patch 2/4:
  - fixed compilation warnings in drivers/fpga/stratix10.c
- Patch 3/4:
  - socfpga_fpga_add() in misc.c
  - define fpga descriptor structure in misc_arria10.c, misc_gen5.c &
    misc_s10.c respectively
  - removed for-loop in socfpga_fpga_add() (only 1 FPGA device added)

v5 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/349670.html

Ang, Chee Hong (4):
  arm: socfpga: stratix10: Add macros for mailbox's arguments
  arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
  arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
  arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |   6 + arch/arm/mach-socfpga/include/mach/misc.h        |   4 +- arch/arm/mach-socfpga/misc.c                     |  26 +- arch/arm/mach-socfpga/misc_arria10.c             |  22 +- arch/arm/mach-socfpga/misc_gen5.c                |  22 +- arch/arm/mach-socfpga/misc_s10.c                 |  22 ++ configs/socfpga_stratix10_defconfig              |   1 + drivers/fpga/Kconfig                             |  11 + drivers/fpga/Makefile                            |   1 + drivers/fpga/altera.c                            |   6 + drivers/fpga/stratix10.c                         | 288
+++++++++++++++++++++++
 include/altera.h                                 |   8 +

Quoted 2 lines
 12 files changed, 389 insertions(+), 28 deletions(-)

 create mode 100644 drivers/fpga/stratix10.c

Quoted 2 lines

I take it this fixes the previous stratix 10 build breakage, right ? let's see what travis says.

Yes. Actually they are just compilation warnings to me. Your travis's build settings treat all warning as error. Please let me know about the travis report. Thanks.

Quoted 1 line
#12 lore raw

v6 cover Stratix10 FPGA reconfiguration support

Quoted 43 lines · Chee Hong
Quoted 42 lines · Marek Vasut
Quoted 41 lines · chee.hong.ang at intel.com

From: "Ang, Chee Hong" <[email protected]>

Summary of v6 changes:
- Patch 1/4 and 4/4 are unchanged
- Patch 2/4:
  - fixed compilation warnings in drivers/fpga/stratix10.c
- Patch 3/4:
  - socfpga_fpga_add() in misc.c
  - define fpga descriptor structure in misc_arria10.c, misc_gen5.c &
    misc_s10.c respectively
  - removed for-loop in socfpga_fpga_add() (only 1 FPGA device added)

v5 patchsets:
https://lists.denx.de/pipermail/u-boot/2018-November/349670.html

Ang, Chee Hong (4):
  arm: socfpga: stratix10: Add macros for mailbox's arguments
  arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
  arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
  arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |   6 + arch/arm/mach-socfpga/include/mach/misc.h        |   4 +- arch/arm/mach-socfpga/misc.c                     |  26 +- arch/arm/mach-socfpga/misc_arria10.c             |  22 +- arch/arm/mach-socfpga/misc_gen5.c                |  22 +- arch/arm/mach-socfpga/misc_s10.c                 |  22 ++ configs/socfpga_stratix10_defconfig              |   1 + drivers/fpga/Kconfig                             |  11 + drivers/fpga/Makefile                            |   1 + drivers/fpga/altera.c                            |   6 + drivers/fpga/stratix10.c                         | 288
+++++++++++++++++++++++
 include/altera.h                                 |   8 +

 12 files changed, 389 insertions(+), 28 deletions(-)

 create mode 100644 drivers/fpga/stratix10.c

Quoted 5 lines
Quoted 2 lines

I take it this fixes the previous stratix 10 build breakage, right ? let's see what travis says.

Yes. Actually they are just compilation warnings to me. Your travis's build settings treat all warning as error. Please let me know about the travis report. Thanks.

+drivers/fpga/stratix10.c: In function 'reconfig_status_polling_resp':
+drivers/fpga/stratix10.c:102:9: error: implicit declaration of function 'mbox_get_fpga_config_status' [-Werror=implicit-function-declaration]
+ ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
+ ^~~~~~~~~~~~~~~~~~~~~~~~~~~
+cc1: all warnings being treated as errors
+make[3]: *** [drivers/fpga/stratix10.o] Error 1
+make[2]: *** [drivers/fpga] Error 2
+make[1]: *** [drivers] Error 2
+make: *** [sub-make] Error 2

Seems like a compile error to me. Please at least build the patches before posting them. See my other email.

Signature · 2 lines
Best regards,
Marek Vasut