irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

PATCH Superseded Guennadi Liakhovetski 4 participants 9 messages Apr 8, 2013 – Apr 10, 2013

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Device tree bindings SuperH irqchip drivers

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Guennadi Liakhovetski

author

2013-04-08 08:08 UTC #0 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---

v3: move the code to a common location, where device configuration parameters are retrieved

 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt

Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +13 -0

new file mode 100644
index 0000000..c6f09b7
@@ -0,0 +1,13 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and any standard
+  resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+  if different from the default 4 bits

drivers/irqchip/irq-renesas-intc-irqpin.c +4 -0

index 5a68e5a..4aca1b2 100644
@@ -18,6 +18,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>

@@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device *pdev)
 	/* deal with driver instance configuration */
 	if (pdata)
 		memcpy(&p->config, pdata, sizeof(*pdata));
+	else
+		of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
+				     &p->config.sense_bitfield_width);
 	if (!p->config.sense_bitfield_width)
 		p->config.sense_bitfield_width = 4; /* default to 4 bits */

Signature · 1 line

1.7.2.5

Laurent Pinchart

2013-04-08 09:56 UTC #1 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Hi Guennadi,

Thanks for the patch.

Quoted 37 lines · On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:

Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by Guennadi Liakhovetski <[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved
 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin. txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi n.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi n.txt new file mode 100644
index 0000000..c6f09b7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi n.txt @@ -0,0 +1,13 @@
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +10 -0
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and any

Quoted 5 lines

standard
+ resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits

Wouldn't it be better to define per-SoC compatible strings, and infer the sense bitfield width from that ?

Quoted 21 lines

(quoted diff) +0 -0

b/drivers/irqchip/irq-renesas-intc-irqpin.c index 5a68e5a..4aca1b2 100644

drivers/irqchip/irq-renesas-intc-irqpin.c +4 -0

@@ -18,6 +18,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>

@@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device
 *pdev) /* deal with driver instance configuration */
 	if (pdata)
 		memcpy(&p->config, pdata, sizeof(*pdata));
+	else
+		of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
+				     &p->config.sense_bitfield_width);
 	if (!p->config.sense_bitfield_width)
 		p->config.sense_bitfield_width = 4; /* default to 4 bits */

Signature · 3 lines

Regards,

Laurent Pinchart

Guennadi Liakhovetski

author

2013-04-08 11:25 UTC #2 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Quoted 42 lines · Laurent Pinchart

Hi Guennadi,
Thanks for the patch.
Quoted 37 lines · On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by Guennadi Liakhovetski <[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved
 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin. txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi n.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi n.txt new file mode 100644
index 0000000..c6f09b7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi n.txt @@ -0,0 +1,13 @@
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +10 -0
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and any

Quoted 8 lines

Quoted 5 lines
standard
+ resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits
Wouldn't it be better to define per-SoC compatible strings, and infer the sense bitfield width from that ?

This is not a boolean, it is an integer, I don't think defining compatibility strings for 1, 2, 3, 4, 5,... bits is better than having one integer property.

Thanks
Guennadi

Quoted 8 lines

Quoted 8 lines
(quoted diff) +0 -0
b/drivers/irqchip/irq-renesas-intc-irqpin.c index 5a68e5a..4aca1b2 100644
drivers/irqchip/irq-renesas-intc-irqpin.c +0 -0
@@ -18,6 +18,7 @@
  */
 

Quoted 19 lines

Quoted 14 lines

drivers/irqchip/irq-renesas-intc-irqpin.c +4 -0

 #include <linux/init.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>

@@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device
 *pdev) /* deal with driver instance configuration */
 	if (pdata)
 		memcpy(&p->config, pdata, sizeof(*pdata));
+	else
+		of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
+				     &p->config.sense_bitfield_width);
 	if (!p->config.sense_bitfield_width)
 		p->config.sense_bitfield_width = 4; /* default to 4 bits */

Signature · 3 lines

Regards,

Laurent Pinchart

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

Laurent Pinchart

2013-04-08 11:37 UTC #3 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Hi Guennadi,

Quoted 49 lines · On Monday 08 April 2013 13:25:46 Guennadi Liakhovetski wrote:

Quoted 39 lines · Laurent Pinchart
Quoted 38 lines · On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by Guennadi Liakhovetski <[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved
 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
(quoted diff) +0 -0
controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
new file mode 100644
index 0000000..c6f09b7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +10 -0
@@ -0,0 +1,13 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and any
Quoted 8 lines
Quoted 5 lines
standard
+ resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits
Wouldn't it be better to define per-SoC compatible strings, and infer the sense bitfield width from that ?

Quoted 3 lines

This is not a boolean, it is an integer, I don't think defining compatibility strings for 1, 2, 3, 4, 5,... bits is better than having one integer property.

I'm not advocating for compatibility strings for a given number of bits, but for per-SoC compatibility strings from which to infer the width.

For instance, if the r8a7779 has a 6-bit sense field, you would use

compatible = "r8a7779,intc-irqpin";

and map that to 6 in the irqpin driver.

Quoted 6 lines

Quoted 6 lines
drivers/irqchip/irq-renesas-intc-irqpin.c
Quoted 6 lines
(quoted diff) +0 -0
b/drivers/irqchip/irq-renesas-intc-irqpin.c index 5a68e5a..4aca1b2 100644
drivers/irqchip/irq-renesas-intc-irqpin.c +0 -0
@@ -18,6 +18,7 @@

	> > >   */

Quoted 17 lines

drivers/irqchip/irq-renesas-intc-irqpin.c +4 -0

 #include <linux/init.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>

@@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device
 *pdev) /* deal with driver instance configuration */
 	if (pdata)
 		memcpy(&p->config, pdata, sizeof(*pdata));
+	else
+		of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
+				     &p->config.sense_bitfield_width);
 
 	if (!p->config.sense_bitfield_width)
 		p->config.sense_bitfield_width = 4; /* default to 4 bits */

Signature · 3 lines

Regards,

Laurent Pinchart

Guennadi Liakhovetski

author

2013-04-08 12:15 UTC #4 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Quoted 56 lines · Laurent Pinchart

Hi Guennadi,
Quoted 49 lines · On Monday 08 April 2013 13:25:46 Guennadi Liakhovetski wrote:
Quoted 39 lines · Laurent Pinchart
Quoted 38 lines · On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by Guennadi Liakhovetski <[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved
 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
(quoted diff) +0 -0
controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
new file mode 100644
index 0000000..c6f09b7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +10 -0
@@ -0,0 +1,13 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and any
Quoted 8 lines
Quoted 5 lines
standard
+ resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits
Wouldn't it be better to define per-SoC compatible strings, and infer the sense bitfield width from that ?
Quoted 3 lines
This is not a boolean, it is an integer, I don't think defining compatibility strings for 1, 2, 3, 4, 5,... bits is better than having one integer property.

Quoted 8 lines

I'm not advocating for compatibility strings for a given number of bits, but for per-SoC compatibility strings from which to infer the width.
For instance, if the r8a7779 has a 6-bit sense field, you would use
compatible = "r8a7779,intc-irqpin";
and map that to 6 in the irqpin driver.

I understand what you mean, still I don't think mapping N SoC-compatibility strings to various values of a single integer is better than having a single property.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

Laurent Pinchart

2013-04-08 23:22 UTC #5 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Hi Guennadi,

Quoted 62 lines · On Monday 08 April 2013 14:15:39 Guennadi Liakhovetski wrote:

Quoted 61 lines · Laurent Pinchart
Quoted 51 lines · On Monday 08 April 2013 13:25:46 Guennadi Liakhovetski wrote:
Quoted 41 lines · Laurent Pinchart
Quoted 40 lines · On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by: Guennadi Liakhovetski
<[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved
 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
(quoted diff) +0 -0
controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/ renesas,intc-irqpin.txt
new file mode 100644
index 0000000..c6f09b7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,int c-
irqpin.txt
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +10 -0
@@ -0,0 +1,13 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and
Quoted 8 lines
Quoted 5 lines
any standard
+ resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits
Wouldn't it be better to define per-SoC compatible strings, and infer the sense bitfield width from that ?
Quoted 3 lines
This is not a boolean, it is an integer, I don't think defining compatibility strings for 1, 2, 3, 4, 5,... bits is better than having one integer property.
I'm not advocating for compatibility strings for a given number of bits, but for per-SoC compatibility strings from which to infer the width.
For instance, if the r8a7779 has a 6-bit sense field, you would use

Quoted 7 lines

Quoted 3 lines
compatible = "r8a7779,intc-irqpin";
and map that to 6 in the irqpin driver.
I understand what you mean, still I don't think mapping N SoC-compatibility strings to various values of a single integer is better than having a single property.

The way I understand (or maybe rather feel) the DT bindings philosophy is that hardware information for on-SoC IP cores that depend on the IP core version should be conveyed through the compatible property. I might be wrong though.

Signature · 3 lines

Regards,

Laurent Pinchart

Simon Horman

2013-04-09 08:44 UTC #6 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Quoted 69 lines · Laurent Pinchart

Hi Guennadi,
Quoted 66 lines · On Monday 08 April 2013 14:15:39 Guennadi Liakhovetski wrote:
Quoted 64 lines · Laurent Pinchart
Quoted 51 lines · On Monday 08 April 2013 13:25:46 Guennadi Liakhovetski wrote:
Quoted 41 lines · Laurent Pinchart
Quoted 40 lines · On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by: Guennadi Liakhovetski
<[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved
 .../interrupt-controller/renesas,intc-irqpin.txt   |   13 +++++++++
 drivers/irqchip/irq-renesas-intc-irqpin.c          |    4 ++++
 2 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,intc- irqpin.txt
(quoted diff) +0 -0
controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/ renesas,intc-irqpin.txt
new file mode 100644
index 0000000..c6f09b7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,int c-
irqpin.txt
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file +10 -0
@@ -0,0 +1,13 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>
+
+Optional properties:
+
+- any properties, listed in interrupts.txt in this directory, and
Quoted 8 lines
Quoted 5 lines
any standard
+ resource allocation properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits
Wouldn't it be better to define per-SoC compatible strings, and infer the sense bitfield width from that ?
Quoted 3 lines
This is not a boolean, it is an integer, I don't think defining compatibility strings for 1, 2, 3, 4, 5,... bits is better than having one integer property.
I'm not advocating for compatibility strings for a given number of bits, but for per-SoC compatibility strings from which to infer the width.
For instance, if the r8a7779 has a 6-bit sense field, you would use
compatible = "r8a7779,intc-irqpin";
and map that to 6 in the irqpin driver.

Quoted 7 lines

Quoted 3 lines
I understand what you mean, still I don't think mapping N SoC-compatibility strings to various values of a single integer is better than having a single property.
The way I understand (or maybe rather feel) the DT bindings philosophy is that hardware information for on-SoC IP cores that depend on the IP core version should be conveyed through the compatible property. I might be wrong though.

That is also my understanding.

Magnus Damm

2013-04-09 22:23 UTC #7 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

In reply to Guennadi Liakhovetski

Hi Guennadi,

Quoted 9 lines · Guennadi Liakhovetski

Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by Guennadi Liakhovetski <[email protected]>
---
v3: move the code to a common location, where device configuration parameters are retrieved

Thanks for rearranging the code, this looks good to me.

Acked-by Magnus Damm <[email protected]>

To be clear, I prefer your approach over a per-SoC compatible string.

In general I think a per-SoC compatible string is nice in theory, but I don't think it is correct to use it to describe a change in a IP block that just happens to included in the SoC. Instead the version of the IP block shall be used with the compatible value. In some cases it may not be easy to retrieve such a version.

The per-SoC compatible string may look good but they come with at least two drawbacks. Either
1) the driver has to be updated for each new SoC even though the device IP the driver is handling hasn't changed which leads to 1.1) more need for pointless per-SoC compatible string patches to be merged and tracked and back ported
and
1.2) less chance of running a standard distro lacking per-SoC compatible string but has actual code for support
or
2) to ship soon the per-SoC DT will use SoC compatible strings matching other SoC names which works but is even more confusing.

For the INTC irqpin case I believe this approach with a single property is the best.

Thanks,

/ magnus

Simon Horman

2013-04-10 00:48 UTC #8 lore raw

PATCH v3 1/1 irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Quoted 11 lines · Magnus Damm

Hi Guennadi,
Quoted 7 lines · Guennadi Liakhovetski
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values.
Signed-off-by Guennadi Liakhovetski <[email protected]>
---

Quoted 6 lines

Quoted 2 lines
v3: move the code to a common location, where device configuration parameters are retrieved
Thanks for rearranging the code, this looks good to me.
Acked-by Magnus Damm <[email protected]>

Thanks, queued-up in the renesas-intc-irqpin branch.

Quoted 28 lines

To be clear, I prefer your approach over a per-SoC compatible string.
In general I think a per-SoC compatible string is nice in theory, but I don't think it is correct to use it to describe a change in a IP block that just happens to included in the SoC. Instead the version of the IP block shall be used with the compatible value. In some cases it may not be easy to retrieve such a version.
The per-SoC compatible string may look good but they come with at least two drawbacks. Either
1) the driver has to be updated for each new SoC even though the device IP the driver is handling hasn't changed which leads to 1.1) more need for pointless per-SoC compatible string patches to be merged and tracked and back ported
and
1.2) less chance of running a standard distro lacking per-SoC compatible string but has actual code for support
or
2) to ship soon the per-SoC DT will use SoC compatible strings matching other SoC names which works but is even more confusing.
For the INTC irqpin case I believe this approach with a single property is the best.
Thanks,
/ magnus