clk: rockchip: add initcall to set clk defaults after syscons are available
Subsystems (2)
Heiko Stübner
maintainerPATCH 1/1 clk: rockchip: add initcall to set clk defaults after syscons are available
PLLs on Rockchip platforms report their locking state in an external register situated in the "General Register Files" which is provided through a syscon device.
When the initial clk init runs, this syscon is of course not yet available, making it impossible to set PLLs to other frequencies through the assigned-rate property of the clock-controller node.
Syscon devices are initialized through a postcore initcall, so add an arch_initcall to rerun the rockchip specific clock initalization when the GRF is available.
As the clock init already runs two times (through of_clk_add_provider and of_clk_init), a third time shouldn't hurt to much and in the best case wouldn't change any settings at all.
--- drivers/clk/rockchip/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
drivers/clk/rockchip/clk.c +13 -0
@@ -23,6 +23,7 @@#include <linux/slab.h> #include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/clk/clk-conf.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "clk.h"
@@ -126,6 +127,18 @@ void __init rockchip_clk_init(struct device_node *np, void __iomem *base,of_clk_add_provider (np, of_clk_src_onecell_get, &clk_data); } +/** +* Set clock-defaults again, after grf regmap is available for PLLs. +*/ +static int __init rockchip_clk_set_defaults (void ) +{ +if (cru_node) +return of_clk_set_defaults (cru_node, true); + +return 0 ; +} +arch_initcall (rockchip_clk_set_defaults); +struct regmap *rockchip_clk_get_grf (void ) {if (IS_ERR (grf))
Signature · 1 line
2.0.1
Heiko,
Quoted 42 lines · Heiko St?bner
PLLs on Rockchip platforms report their locking state in an external register situated in the "General Register Files" which is provided through a syscon device.
When the initial clk init runs, this syscon is of course not yet available, making it impossible to set PLLs to other frequencies through the assigned-rate property of the clock-controller node.
Syscon devices are initialized through a postcore initcall, so add an
arch_initcallto rerun the rockchip specific clock initalization when the GRF is available.As the clock init already runs two times (through
of_clk_add_providerandof_clk_init), a third time shouldn't hurt to much and in the best case wouldn't change any settings at all.Signed-off-by Heiko Stuebner <[email protected]>--- drivers/clk/rockchip/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)drivers/clk/rockchip/clk.c +6
-0@@ -23,6 +23,7 @@#include <linux/slab.h> #include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/clk/clk-conf.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "clk.h" @@ -126,6 +127,18 @@ void __init rockchip_clk_init(struct device_node *np, void __iomem *base,of_clk_add_provider (np, of_clk_src_onecell_get, &clk_data); } +/** +* Set clock-defaults again, after grf regmap is available for PLLs. +*/ +static int __init rockchip_clk_set_defaults (void ) +{
drivers/clk/rockchip/clk.c void __init rockchip_clk_init(struct device_node *np, void __iomem *base, · line 144
Quoted 10 lines
drivers/clk/rockchip/clk.c +7
-0+if (cru_node) +return of_clk_set_defaults (cru_node, true); + +return 0 ; +} +arch_initcall (rockchip_clk_set_defaults); +struct regmap *rockchip_clk_get_grf (void ) {if (IS_ERR (grf))
This patch works on my rk3288 evb, so,
Hi,
Quoted 12 lines · Heiko St?bner
PLLs on Rockchip platforms report their locking state in an external register situated in the "General Register Files" which is provided through a syscon device.
When the initial clk init runs, this syscon is of course not yet available, making it impossible to set PLLs to other frequencies through the assigned-rate property of the clock-controller node.
Syscon devices are initialized through a postcore initcall, so add an
arch_initcallto rerun the rockchip specific clock initalization when the GRF is available.
Quoted 8 lines
As the clock init already runs two times (through
of_clk_add_providerandof_clk_init), a third time shouldn't hurt to much and in the best case wouldn't change any settings at all.Signed-off-by Heiko Stuebner <[email protected]>--- drivers/clk/rockchip/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
My current understanding is that this patch is on hold pending
<https://patchwork.kernel.org/patch/4945531/> (AKA mfd: syscon:
Decouple syscon interface from platform devices). If that patch lands then we can drop this one.
-Doug
Heiko Stübner
maintainerAm Mittwoch, 24. September 2014, 13:21:57 schrieb Doug Anderson:
Quoted 22 lines
Hi,
Quoted 19 lines · Heiko St?bner
PLLs on Rockchip platforms report their locking state in an external register situated in the "General Register Files" which is provided through a syscon device.
When the initial clk init runs, this syscon is of course not yet available, making it impossible to set PLLs to other frequencies through the assigned-rate property of the clock-controller node.
Syscon devices are initialized through a postcore initcall, so add an
arch_initcallto rerun the rockchip specific clock initalization when the GRF is available.As the clock init already runs two times (through
of_clk_add_providerandof_clk_init), a third time shouldn't hurt to much and in the best case wouldn't change any settings at all.Signed-off-by Heiko Stuebner <[email protected]>---
Quoted 7 lines
Quoted 2 lines
drivers/clk/rockchip/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)My current understanding is that this patch is on hold pending
<https://patchwork.kernel.org/patch/4945531/> (AKA mfd: syscon:
Decouple syscon interface from platform devices). If that patch lands then we can drop this one.
correct.
I've tested v5 this evening and apart from the debugfs issue I reported there, the whole assigned-clocks init worked really nice.
Heiko