PEBS enabling in KVM guest

Intel new hardware introduces a mechanism to direct PEBS records output into the Intel PT buffer that can be used for enabling PEBS in KVM guest. This patch implements the registers read and write emulation when PEBS is supported in KVM guest.

KMM needs to reprogram the counters when the value of these MSRs be changed that to make sure it can take effect in hardware.

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/include/asm/kvm_host.h  |  4 +++
 arch/x86/include/asm/msr-index.h |  6 ++++
 arch/x86/kvm/vmx/capabilities.h  | 15 ++++++++++
 arch/x86/kvm/vmx/pmu_intel.c     | 63 ++++++++++++++++++++++++++++++++++++++--
 4 files changed, 86 insertions(+), 2 deletions(-)

arch/x86/include/asm/msr-index.h +4 -0

index 20ce682..d22f8d9 100644
@@ -131,9 +131,13 @@
 #define LBR_INFO_ABORT			BIT_ULL(61)
 #define LBR_INFO_CYCLES			0xffff
 
+#define MSR_IA32_PEBS_PMI_AFTER_REC	BIT_ULL(60)
+#define MSR_IA32_PEBS_OUTPUT_PT		BIT_ULL(61)
+#define MSR_IA32_PEBS_OUTPUT_MASK	(3ULL << 61)
 #define MSR_IA32_PEBS_ENABLE		0x000003f1
 #define MSR_PEBS_DATA_CFG		0x000003f2
 #define MSR_IA32_DS_AREA		0x00000600
+#define MSR_IA32_PERF_CAP_PEBS_OUTPUT_PT	BIT_ULL(16)
 #define MSR_IA32_PERF_CAPABILITIES	0x00000345
 #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
 

Quoted 35 lines

Intel new hardware introduces a mechanism to direct PEBS records output into the Intel PT buffer that can be used for enabling PEBS in KVM guest. This patch implements the registers read and write emulation when PEBS is supported in KVM guest.

KMM needs to reprogram the counters when the value of these MSRs be changed that to make sure it can take effect in hardware.

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/include/asm/kvm_host.h  |  4 +++
arch/x86/include/asm/msr-index.h |  6 ++++
arch/x86/kvm/vmx/capabilities.h  | 15 ++++++++++
 arch/x86/kvm/vmx/pmu_intel.c     | 63 ++++++++++++++++++++++++++++++++++++++--
 4 files changed, 86 insertions(+), 2 deletions(-)

arch/x86/include/asm/msr-index.h +4 -0

index 20ce682..d22f8d9 100644
@@ -131,9 +131,13 @@
 #define LBR_INFO_ABORT			BIT_ULL(61)
 #define LBR_INFO_CYCLES			0xffff
 
+#define MSR_IA32_PEBS_PMI_AFTER_REC	BIT_ULL(60)
+#define MSR_IA32_PEBS_OUTPUT_PT		BIT_ULL(61)
+#define MSR_IA32_PEBS_OUTPUT_MASK	(3ULL << 61)
 #define MSR_IA32_PEBS_ENABLE		0x000003f1
 #define MSR_PEBS_DATA_CFG		0x000003f2
 #define MSR_IA32_DS_AREA		0x00000600
+#define MSR_IA32_PERF_CAP_PEBS_OUTPUT_PT	BIT_ULL(16)
 #define MSR_IA32_PERF_CAPABILITIES	0x00000345
 #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
 

arch/x86/include/asm/msr-index.h line 676

Quoted 9 lines

arch/x86/include/asm/msr-index.h +2 -0

@@ -665,6 +669,8 @@
 #define MSR_IA32_MISC_ENABLE_FERR			(1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT		10
 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX		(1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
+#define MSR_IA32_MISC_ENABLE_PEBS_BIT			12
+#define MSR_IA32_MISC_ENABLE_PEBS			(1ULL << MSR_IA32_MISC_ENABLE_PEBS_BIT)
 #define MSR_IA32_MISC_ENABLE_TM2_BIT			13
 #define MSR_IA32_MISC_ENABLE_TM2			(1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT	19

Some of these already exist but are local to perf. Don't blindly introduce more without unifying.

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

Quoted 8 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 6 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Quoted 8 lines

Quoted 8 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

Quoted 8 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 6 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.

Quoted 17 lines

Quoted 16 lines

Quoted 9 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 5 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Quoted 2 lines

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.

attr.aux_output==1 means your group leader should be an intel_pt event for this to succeed. Luckily for this instance, perf_event_create_kernel_counter() doesn't actually check the attr.aux_output.

Also, does 'bool pebs' mean PEBS-via-PT or just a PEBS counter? Or does it mean that in kvm it's the same thing?

Regards,
--
Alex

Quoted 20 lines

Quoted 19 lines

Quoted 8 lines

Quoted 8 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

Quoted 8 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 6 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.

Quoted 4 lines

attr.aux_output==1 means your group leader should be an intel_pt event for this to succeed. Luckily for this instance, perf_event_create_kernel_counter() doesn't actually check the attr.aux_output.

Also, does 'bool pebs' mean PEBS-via-PT or just a PEBS counter? Or does it mean that in kvm it's the same thing?

It is the same thing. Allocate a counter for PEBS event and use PEBS-via-PT.

Quoted 17 lines · Luwei

Quoted 8 lines

Quoted 8 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

Quoted 8 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 6 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Quoted 2 lines

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.

attr.aux_output==1 means your group leader should be an intel_pt event for this to succeed. Luckily for this instance, perf_event_create_kernel_counter() doesn't actually check the attr.aux_output.

Also, does 'bool pebs' mean PEBS-via-PT or just a PEBS counter? Or does it mean that in kvm it's the same thing?

Quoted 8 lines

Quoted 8 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

Quoted 8 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 6 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.
For precise_ip, it is the precise level in perf and set by perf command line in KVM guest, this may not reflect the accurate value (can be 0~3) here. Here set to 1 is used to allocate a counter for PEBS event and set the MSR_IA32_PEBS_ENABLE register. For PMU virtualization, KVM will trap the guest's write operation to PMU registers and allocate/free event counter from host if a counter enable/disable in guest. We can't always deduce the exact parameter of perf command line from the value of the guest writers to the register.

Quoted 17 lines · Luwei

Quoted 16 lines

Quoted 9 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 5 lines

arch/x86/kvm/pmu.c +2 -0

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Quoted 3 lines

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.
For precise_ip, it is the precise level in perf and set by perf command line in KVM guest, this may not reflect the accurate value (can be 0~3) here. Here set to 1 is used to allocate a counter for PEBS event and set the MSR_IA32_PEBS_ENABLE register. For PMU virtualization, KVM will trap the guest's write operation to PMU registers and allocate/free event counter from host if a counter enable/disable in guest. We can't always deduce the exact parameter of perf command line from the value of the guest writers to the register.

Please, teach your MUA to wrap on 78 chars.

The thing I really fell over is the gratuitous 'bool ? 1 : 0'. But yes,

Quoted 9 lines

Quoted 9 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc,

Quoted 9 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = {

@@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc,

u32 type,

Quoted 10 lines

Quoted 7 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 5 lines

arch/x86/kvm/pmu.c +2 -0

 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1 when the guest wants to

enabled PEBS by Intel PT.

Quoted 1 line

For precise_ip, it is the precise level in perf and set by perf command line in KVM

guest, this may not reflect the accurate value (can be 0~3) here. Here set to 1 is used to allocate a counter for PEBS event and set the MSR_IA32_PEBS_ENABLE register. For PMU virtualization, KVM will trap the guest's write operation to PMU registers and allocate/free event counter from host if a counter enable/disable in guest. We can't always deduce the exact parameter of perf command line from the value of the guest writers to the register.

Please, teach your MUA to wrap on 78 chars.

The thing I really fell over is the gratuitous 'bool ? 1 : 0'. But yes, the aux_output without a group leader is dead wrong. We'll go fix
perf_event_create_kernel_counter() to refuse that.

Quoted 22 lines

Quoted 9 lines

Quoted 9 lines

Quoted 9 lines

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

arch/x86/kvm/pmu.c +1 -1

 				  unsigned config, bool exclude_user,
 				  bool exclude_kernel, bool intr,
-				  bool in_tx, bool in_tx_cp)
+				  bool in_tx, bool in_tx_cp, bool pebs)
 {
 	struct perf_event *event;
 	struct perf_event_attr attr = { @@ -111,9 +111,12 @@ static

void pmc_reprogram_counter(struct kvm_pmc *pmc,

u32 type,

Quoted 11 lines

Quoted 7 lines

arch/x86/kvm/pmu.c static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, · line 115

Quoted 5 lines

arch/x86/kvm/pmu.c +2 -0

 		.exclude_user = exclude_user,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
+		.precise_ip = pebs ? 1 : 0,
+		.aux_output = pebs ? 1 : 0,

srsly?

Hi Peter,
Thanks for review. For aux_output, I think it should be set 1
when the guest wants to

enabled PEBS by Intel PT.

Quoted 8 lines

Quoted 2 lines

For precise_ip, it is the precise level in perf and set by perf
command line in KVM

guest, this may not reflect the accurate value (can be 0~3) here. Here set to 1 is used to allocate a counter for PEBS event and set the MSR_IA32_PEBS_ENABLE register. For PMU virtualization, KVM will trap the guest's write operation to PMU registers and allocate/free event counter from host if a counter enable/disable in guest. We can't always deduce the exact parameter of perf command line from the value of the guest

writers to the register.

Quoted 6 lines

Please, teach your MUA to wrap on 78 chars.

The thing I really fell over is the gratuitous 'bool ? 1 : 0'. But yes, the aux_output without a group leader is dead wrong. We'll go fix perf_event_create_kernel_counter() to refuse that.

Yes, I also think it is a little gratuitous here. But it is a little hard to reconstruct the guest perf parameters from the register value, especially the "precise_ip". Do you have any advice?

About refuse the perf_event_create_kernel_counter() request w/o aux_ouput, I think I need to allocate the PT event as group leader here, is that right?

This patch introduce a parameter that avoid clear the PEBS event counter while running in the guest. The performance counter which use for PEBS event can be enabled through VM-entry when PEBS is enabled in guest by PEBS output to Intel PT.

Quoted 4 lines

This patch introduce a parameter that avoid clear the PEBS event counter while running in the guest. The performance counter which use for PEBS event can be enabled through VM-entry when PEBS is enabled in guest by PEBS output to Intel PT.

Please write coherent Changelogs. I have no clue what you're trying to say.

Also, maybe this attrocious coding style is accepted in KVM, but I'm not having it. Pretty much all your linebreaks and subsequent indenting is against style.

Expose PEBS feature to guest by IA32_MISC_ENABLE[bit12]. IA32_MISC_ENABLE[bit12] is Processor Event Based Sampling (PEBS) Unavailable (RO) flag:
1 = PEBS is not supported; 0 = PEBS is supported.

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/include/asm/kvm_host.h |  1 +
 arch/x86/kvm/svm.c              |  6 ++++++
 arch/x86/kvm/vmx/vmx.c          |  1 +
 arch/x86/kvm/x86.c              | 22 +++++++++++++++++-----
 4 files changed, 25 insertions(+), 5 deletions(-)

arch/x86/include/asm/kvm_host.h +1 -0

index 24a0ab9..76f5fa5 100644
@@ -1127,6 +1127,7 @@ struct kvm_x86_ops {
 	bool (*xsaves_supported)(void);
 	bool (*umip_emulated)(void);
 	bool (*pt_supported)(void);
+	bool (*pebs_supported)(void);
 	bool (*pdcm_supported)(void);
 
 	int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr);

arch/x86/kvm/svm.c +6 -0

index 7e0a7b3..3a1bbb3 100644
@@ -5975,6 +5975,11 @@ static bool svm_pt_supported(void)
 	return false;
 }
 
+static bool svm_pebs_supported(void)
+{
+	return false;
+}
+
 static bool svm_pdcm_supported(void)
 {
 	return false;

@@ -7277,6 +7282,7 @@ static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
 	.xsaves_supported = svm_xsaves_supported,
 	.umip_emulated = svm_umip_emulated,
 	.pt_supported = svm_pt_supported,
+	.pebs_supported = svm_pebs_supported,
 	.pdcm_supported = svm_pdcm_supported,
 
 	.set_supported_cpuid = svm_set_supported_cpuid,

arch/x86/kvm/vmx/vmx.c +1 -0

index 5c4dd05..3c370a3 100644
@@ -7879,6 +7879,7 @@ static __exit void hardware_unsetup(void)
 	.xsaves_supported = vmx_xsaves_supported,
 	.umip_emulated = vmx_umip_emulated,
 	.pt_supported = vmx_pt_supported,
+	.pebs_supported = vmx_pebs_supported,
 	.pdcm_supported = vmx_pdcm_supported,
 
 	.request_immediate_exit = vmx_request_immediate_exit,

arch/x86/kvm/x86.c +1 -0

index 661e2bf..5f59073 100644
@@ -2591,6 +2591,7 @@ static void record_steal_time(struct kvm_vcpu *vcpu)
 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 {
 	bool pr = false;
+	bool update_cpuid = false;
 	u32 msr = msr_info->index;
 	u64 data = msr_info->data;
 

@@ -2671,11 +2672,17 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		    ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
 			if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))

arch/x86/kvm/x86.c +6 -0

+		else
+			data |= MSR_IA32_MISC_ENABLE_PEBS;
+
+		vcpu->arch.ia32_misc_enable_msr = data;
+		if (update_cpuid)
+			kvm_update_cpuid(vcpu);
 		break;
 	case MSR_IA32_SMBASE:
 		if (!msr_info->host_initiated)

arch/x86/kvm/x86.c +0 -0

 		break;
 	case MSR_IA32_SMBASE:
 		if (!msr_info->host_initiated)

Signature · 1 line

1.8.3.1

Quoted 4 lines

Expose PEBS feature to guest by IA32_MISC_ENABLE[bit12]. IA32_MISC_ENABLE[bit12] is Processor Event Based Sampling (PEBS) Unavailable (RO) flag:
1 = PEBS is not supported; 0 = PEBS is supported.

Why does it make sense to expose this on SVM?

Quoted 69 lines

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/include/asm/kvm_host.h |  1 +
 arch/x86/kvm/svm.c              |  6 ++++++
 arch/x86/kvm/vmx/vmx.c          |  1 +
 arch/x86/kvm/x86.c              | 22 +++++++++++++++++-----
 4 files changed, 25 insertions(+), 5 deletions(-)

(quoted diff) +0 -0

b/arch/x86/include/asm/kvm_host.h index 24a0ab9..76f5fa5 100644

arch/x86/include/asm/kvm_host.h +1 -0

@@ -1127,6 +1127,7 @@ struct kvm_x86_ops {
 	bool (*xsaves_supported)(void);
 	bool (*umip_emulated)(void);
 	bool (*pt_supported)(void);
+	bool (*pebs_supported)(void);
 	bool (*pdcm_supported)(void);
 
 	int (*check_nested_events)(struct kvm_vcpu *vcpu, bool

external_intr); diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 7e0a7b3..3a1bbb3 100644

arch/x86/kvm/svm.c +6 -0

@@ -5975,6 +5975,11 @@ static bool svm_pt_supported(void)
 	return false;
 }
 
+static bool svm_pebs_supported(void)
+{
+	return false;
+}
+
 static bool svm_pdcm_supported(void)
 {
 	return false;

@@ -7277,6 +7282,7 @@ static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
 	.xsaves_supported = svm_xsaves_supported,
 	.umip_emulated = svm_umip_emulated,
 	.pt_supported = svm_pt_supported,
+	.pebs_supported = svm_pebs_supported,
 	.pdcm_supported = svm_pdcm_supported,
 
 	.set_supported_cpuid = svm_set_supported_cpuid, diff --git

a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 5c4dd05..3c370a3 100644

arch/x86/kvm/vmx/vmx.c +1 -0

@@ -7879,6 +7879,7 @@ static __exit void hardware_unsetup(void)
 	.xsaves_supported = vmx_xsaves_supported,
 	.umip_emulated = vmx_umip_emulated,
 	.pt_supported = vmx_pt_supported,
+	.pebs_supported = vmx_pebs_supported,
 	.pdcm_supported = vmx_pdcm_supported,
 
 	.request_immediate_exit = vmx_request_immediate_exit, diff --git

a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 661e2bf..5f59073 100644

arch/x86/kvm/x86.c +1 -0

@@ -2591,6 +2591,7 @@ static void record_steal_time(struct kvm_vcpu
 *vcpu)  int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data
 *msr_info)  {
 	bool pr = false;
+	bool update_cpuid = false;
 	u32 msr = msr_info->index;
 	u64 data = msr_info->data;
 

arch/x86/kvm/x86.c int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · line 2679

Quoted 13 lines

arch/x86/kvm/x86.c +4 -4

@@ -2671,11 +2672,17 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		    ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
 			if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
 				return 1;
-			vcpu->arch.ia32_misc_enable_msr = data;
-			kvm_update_cpuid(vcpu);
-		} else {
-			vcpu->arch.ia32_misc_enable_msr = data;
+			update_cpuid = true;
 		}
+
+		if (kvm_x86_ops->pebs_supported())
+			data &=  ~MSR_IA32_MISC_ENABLE_PEBS;

whitespace damage

Quoted 11 lines

arch/x86/kvm/x86.c +6 -0

+		else
+			data |= MSR_IA32_MISC_ENABLE_PEBS;
+
+		vcpu->arch.ia32_misc_enable_msr = data;
+		if (update_cpuid)
+			kvm_update_cpuid(vcpu);
 		break;
 	case MSR_IA32_SMBASE:
 		if (!msr_info->host_initiated)

arch/x86/kvm/x86.c int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · line 2986

Quoted 10 lines

arch/x86/kvm/x86.c +6 -1

@@ -2971,7 +2978,12 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
 		break;
 	case MSR_IA32_MISC_ENABLE:
-		msr_info->data = vcpu->arch.ia32_misc_enable_msr;
+		if (kvm_x86_ops->pebs_supported())
+			msr_info->data = (vcpu->arch.ia32_misc_enable_msr &
+						~MSR_IA32_MISC_ENABLE_PEBS);
+		else
+			msr_info->data = (vcpu->arch.ia32_misc_enable_msr |
+						MSR_IA32_MISC_ENABLE_PEBS);

Coding style violation.

Quoted 6 lines

arch/x86/kvm/x86.c +0 -1

 		break;
 	case MSR_IA32_SMBASE:
 		if (!msr_info->host_initiated)
--

1.8.3.1

Quoted 6 lines

Quoted 4 lines

Expose PEBS feature to guest by IA32_MISC_ENABLE[bit12]. IA32_MISC_ENABLE[bit12] is Processor Event Based Sampling (PEBS) Unavailable (RO) flag:
1 = PEBS is not supported; 0 = PEBS is supported.

Why does it make sense to expose this on SVM?

Thanks for the review. This patch won't expose the pebs feature to SVM and return not supported.

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

Expose PEBS feature to guest by IA32_MISC_ENABLE[bit12]. IA32_MISC_ENABLE[bit12] is Processor Event Based Sampling (PEBS) Unavailable (RO) flag:
1 = PEBS is not supported; 0 = PEBS is supported.

Why does it make sense to expose this on SVM?

Thanks for the review. This patch won't expose the pebs feature to SVM and return not supported.

AFAICT it exposes/emulates an Intel MSR on AMD, which is just weird.

For PEBS output to Intel PT, a Intel PT event should be the group leader of an PEBS counter event in host. For Intel PT virtualization enabling in KVM guest, the PT facilities will be passthrough to guest and do not allocate PT event from host perf event framework. This is different with PMU virtualization.

Intel new hardware feature that can make PEBS enabled in KVM guest by output PEBS records to Intel PT buffer. KVM need to allocate a event counter for this PEBS event without Intel PT event leader.

This patch add event owner check for PEBS output to PT event that only non-kernel event need group leader(PT).

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/events/core.c     | 3 ++-
 include/linux/perf_event.h | 1 +
 kernel/events/core.c       | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

arch/x86/events/core.c +0 -0

index 7b21455..214041a 100644

arch/x86/events/core.c +0 -0

 			return -EINVAL;
 
 		/*

Quoted 25 lines

For PEBS output to Intel PT, a Intel PT event should be the group leader of an PEBS counter event in host. For Intel PT virtualization enabling in KVM guest, the PT facilities will be passthrough to guest and do not allocate PT event from host perf event framework. This is different with PMU virtualization.

Intel new hardware feature that can make PEBS enabled in KVM guest by output PEBS records to Intel PT buffer. KVM need to allocate a event counter for this PEBS event without Intel PT event leader.

This patch add event owner check for PEBS output to PT event that only non-kernel event need group leader(PT).

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/events/core.c     | 3 ++-
 include/linux/perf_event.h | 1 +
 kernel/events/core.c       | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

arch/x86/events/core.c index renamed from arch/x86/events/core.c +0 -0

7b21455..214041a 100644

arch/x86/events/core.c static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, · line 1018

Quoted 6 lines

arch/x86/events/core.c +2 -1

@@ -1014,7 +1014,8 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader,
 		 * away, the group was broken down and this singleton event
 		 * can't schedule any more.
 		 */
-		if (is_pebs_pt(leader) && !leader->aux_event)
+		if (is_pebs_pt(leader) && !leader->aux_event &&
+					!is_kernel_event(leader))

indent fail, but also, I'm not sure I buy this.

Surely pt-on-kvm has a perf event to claim PT for the vCPU context?

Even if not, this is not strictly correct. Not even now is KVM the sole user of perf_event_create_kernel_counter(), so saying any kernel event is excempt from this scheduling constraint is jsut wrong.

Quoted 4 lines

arch/x86/events/core.c +0 -0

 			return -EINVAL;
 
 		/*

Quoted 34 lines

Quoted 25 lines

For PEBS output to Intel PT, a Intel PT event should be the group leader of an PEBS counter event in host. For Intel PT virtualization enabling in KVM guest, the PT facilities will be passthrough to guest and do not allocate PT event from host perf event framework. This is different with PMU virtualization.

Intel new hardware feature that can make PEBS enabled in KVM guest by output PEBS records to Intel PT buffer. KVM need to allocate a event counter for this PEBS event without Intel PT event leader.

This patch add event owner check for PEBS output to PT event that only non-kernel event need group leader(PT).

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/events/core.c     | 3 ++-
 include/linux/perf_event.h | 1 +
 kernel/events/core.c       | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

arch/x86/events/core.c index renamed from arch/x86/events/core.c +0 -0

7b21455..214041a 100644

arch/x86/events/core.c static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, · line 1018

Quoted 6 lines

arch/x86/events/core.c +2 -1

@@ -1014,7 +1014,8 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader,
 		 * away, the group was broken down and this singleton event
 		 * can't schedule any more.
 		 */
-		if (is_pebs_pt(leader) && !leader->aux_event)
+		if (is_pebs_pt(leader) && !leader->aux_event &&
+					!is_kernel_event(leader))

indent fail, but also, I'm not sure I buy this.

Quoted 1 line

Surely pt-on-kvm has a perf event to claim PT for the vCPU context?

Hi Peter,
PT on KVM will not allocate perf events from host (this is different from performance counter). The guest PT MSRs value will be load to hardware directly before VM-entry. A PT event is needed by PEBS event as the event group leader in native. In virtualization, we can allocate a counter for PEBS but can't assign a PT event as the leader of this PEBS event.

Quoted 34 lines

Quoted 34 lines

Quoted 25 lines

For PEBS output to Intel PT, a Intel PT event should be the group leader of an PEBS counter event in host. For Intel PT virtualization enabling in KVM guest, the PT facilities will be passthrough to guest and do not allocate PT event from host perf event framework. This is different with PMU virtualization.

Intel new hardware feature that can make PEBS enabled in KVM guest by output PEBS records to Intel PT buffer. KVM need to allocate a event counter for this PEBS event without Intel PT event leader.

This patch add event owner check for PEBS output to PT event that only non-kernel event need group leader(PT).

Signed-off-by Luwei Kang <[email protected]>

---
 arch/x86/events/core.c     | 3 ++-
 include/linux/perf_event.h | 1 +
 kernel/events/core.c       | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

arch/x86/events/core.c index renamed from arch/x86/events/core.c +0 -0

7b21455..214041a 100644

arch/x86/events/core.c static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, · line 1018

Quoted 6 lines

arch/x86/events/core.c +2 -1

@@ -1014,7 +1014,8 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader,
 		 * away, the group was broken down and this singleton event
 		 * can't schedule any more.
 		 */
-		if (is_pebs_pt(leader) && !leader->aux_event)
+		if (is_pebs_pt(leader) && !leader->aux_event &&
+					!is_kernel_event(leader))

indent fail, but also, I'm not sure I buy this.

Quoted 4 lines

Quoted 1 line

Surely pt-on-kvm has a perf event to claim PT for the vCPU context?

Hi Peter,
PT on KVM will not allocate perf events from host (this is different from performance counter). The guest PT MSRs value will be

load to hardware directly before VM-entry.

Quoted 1 line

A PT event is needed by PEBS event as the event group leader in native. In virtualization, we can allocate a counter for PEBS but

can't assign a PT event as the leader of this PEBS event.

Please, fix your MUA already.

Then how does KVM deal with the host using PT? You can't just steal PT.

Quoted 1 line

Then how does KVM deal with the host using PT? You can't just steal PT.

Intel PT in virtualization can work in system and host_guest mode.
In system mode (default), the trace produced by host and guest will be saved in host PT buffer. Intel PT will not be exposed to guest in this mode.
In host_guest mode, Intel PT will be exposed to guest and guest can use PT like native. The value of host PT register will be saved and guest PT register value will be restored during VM-entry. Both trace of host and guest are exported to their respective PT buffer. The host PT buffer not include guest trace in this mode.

Quoted 4 lines

Quoted 1 line

Then how does KVM deal with the host using PT? You can't just steal PT.

Intel PT in virtualization can work in system and host_guest mode.
In system mode (default), the trace produced by host and guest will be saved in host PT buffer. Intel PT will not be exposed to guest

in this mode.

Quoted 1 line

In host_guest mode, Intel PT will be exposed to guest and guest can use PT like native. The value of host PT register will be saved

and guest PT register value will be restored during VM-entry. Both trace of host and guest are exported to their respective PT buffer. The host PT buffer not include guest trace in this mode.

IOW, it will steal PT from the host.

Regards,
--
Alex