Add USB DWC3 support for SC7180

Add compatible for SC7180 SOC in USB DWC3 driver

Signed-off-by Sandeep Maheswaram <[email protected]>

---
 drivers/usb/dwc3/dwc3-qcom.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/usb/dwc3/dwc3-qcom.c +1 -1

index 261af9e..1df2372 100644
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  *
  * Inspired by dwc3-of-simple.c
  */

Hi,

Quoted 19 lines · Sandeep Maheswaram

Add compatible for SC7180 SOC in USB DWC3 driver

Signed-off-by Sandeep Maheswaram <[email protected]>

---
  drivers/usb/dwc3/dwc3-qcom.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

drivers/usb/dwc3/dwc3-qcom.c +1 -1

index 261af9e..1df2372 100644
@@ -1,5 +1,5 @@
  // SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
   *
   * Inspired by dwc3-of-simple.c
   */

drivers/usb/dwc3/dwc3-qcom.c static const struct of_device_id dwc3_qcom_of_match[] = { · line 757

Quoted 5 lines

drivers/usb/dwc3/dwc3-qcom.c +1 -0

@@ -753,6 +753,7 @@ static const struct of_device_id dwc3_qcom_of_match[] = {
         { .compatible = "qcom,dwc3" },
         { .compatible = "qcom,msm8996-dwc3" },
         { .compatible = "qcom,msm8998-dwc3" },
+       { .compatible = "qcom,sc7180-dwc3" },
         { .compatible = "qcom,sdm845-dwc3" },

It is, of course, up to Felipe. ...but in my opinion this is the wrong change and instead we should be deleting the SoC-specific strings (msm8996, msm8998, sdm845) from this file because they don't buy us anything. To explain how it works:

1. Device tree should have both the "SoC-specific" and generic "qcom,dwc3" strings. Only the "qcom,dwc3" will actually be used but the SoC-specific string is there so if we find a case later where we need to handle a SoC-specific quirk then it'll already be there.

2. Bindings should have both the "SoC-specific" and generic "qcom,dwc3" strings. The binding is describing what's in the device tree.

3. Until we have a SoC-specific quirk to handle, we _don't_ need to add the SoC-specific string to the driver itself.

-Doug

Hi,

Quoted 41 lines · Doug Anderson

Hi,

Quoted 19 lines · Sandeep Maheswaram

Add compatible for SC7180 SOC in USB DWC3 driver

Signed-off-by Sandeep Maheswaram <[email protected]>

---
  drivers/usb/dwc3/dwc3-qcom.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

drivers/usb/dwc3/dwc3-qcom.c +1 -1

index 261af9e..1df2372 100644
@@ -1,5 +1,5 @@
  // SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
   *
   * Inspired by dwc3-of-simple.c
   */

drivers/usb/dwc3/dwc3-qcom.c static const struct of_device_id dwc3_qcom_of_match[] = { · line 757

Quoted 5 lines

drivers/usb/dwc3/dwc3-qcom.c +1 -0

@@ -753,6 +753,7 @@ static const struct of_device_id dwc3_qcom_of_match[] = {
         { .compatible = "qcom,dwc3" },
         { .compatible = "qcom,msm8996-dwc3" },
         { .compatible = "qcom,msm8998-dwc3" },
+       { .compatible = "qcom,sc7180-dwc3" },
         { .compatible = "qcom,sdm845-dwc3" },

It is, of course, up to Felipe. ...but in my opinion this is the wrong change and instead we should be deleting the SoC-specific strings (msm8996, msm8998, sdm845) from this file because they don't buy us anything. To explain how it works:

1. Device tree should have both the "SoC-specific" and generic "qcom,dwc3" strings. Only the "qcom,dwc3" will actually be used but the SoC-specific string is there so if we find a case later where we need to handle a SoC-specific quirk then it'll already be there.

2. Bindings should have both the "SoC-specific" and generic "qcom,dwc3" strings. The binding is describing what's in the device tree.

Quoted 6 lines

3. Until we have a SoC-specific quirk to handle, we _don't_ need to add the SoC-specific string to the driver itself.

-Doug

Can i remove this patch { .compatible = "qcom,sc7180-dwc3" }, in the next version of this series ?

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +0 -0

new file mode 100644
index 0000000..48ff9c5

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +12 -0

+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,msm8996-dwc3
+          - qcom,msm8998-dwc3
+          - qcom,sdm845-dwc3
+      - const: qcom,dwc3
+
+  reg:
+    description: Offset and length of register set for QSCRATCH wrapper
+    maxItems: 1

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +6 -0

+
+            interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
+            interrupt-names = "hs_phy_irq", "ss_phy_irq",
+                    "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+            clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,

Convert USB DWC3 bindings to DT schema format using json-schema.

Signed-off-by Sandeep Maheswaram <[email protected]>

---
 .../devicetree/bindings/usb/qcom,dwc3.txt          | 104 --------------
 .../devicetree/bindings/usb/qcom,dwc3.yaml         | 155 +++++++++++++++++++++
 2 files changed, 155 insertions(+), 104 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
 create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

Documentation/devicetree/bindings/usb/qcom,dwc3.txt deleted +0 -104

deleted file mode 100644
index cb695aa..0000000
@@ -1,104 +0,0 @@
-Qualcomm SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible:          Compatible list, contains
-                       "qcom,dwc3"
-                       "qcom,msm8996-dwc3" for msm8996 SOC.
-                       "qcom,msm8998-dwc3" for msm8998 SOC.
-                       "qcom,sdm845-dwc3" for sdm845 SOC.
-- reg:                 Offset and length of register set for QSCRATCH wrapper
-- power-domains:       specifies a phandle to PM domain provider node
-- clocks:              A list of phandle + clock-specifier pairs for the
-                               clocks listed in clock-names
-- clock-names:         Should contain the following:
-  "core"               Master/Core clock, have to be >= 125 MHz for SS
-                               operation and >= 60MHz for HS operation
-  "mock_utmi"          Mock utmi clock needed for ITP/SOF generation in
-                               host mode. Its frequency should be 19.2MHz.
-  "sleep"              Sleep clock, used for wakeup when USB3 core goes
-                               into low power mode (U3).
-
-Optional clocks:
-  "iface"              System bus AXI clock.
-                       Not present on "qcom,msm8996-dwc3" compatible.
-  "cfg_noc"            System Config NOC clock.
-                       Not present on "qcom,msm8996-dwc3" compatible.
-- assigned-clocks:     Should be:
-                               MOCK_UTMI_CLK
-                               MASTER_CLK
-- assigned-clock-rates: Should be:
-                                19.2Mhz (192000000) for MOCK_UTMI_CLK
-                                >=125Mhz (125000000) for MASTER_CLK in SS mode
-                                >=60Mhz (60000000) for MASTER_CLK in HS mode
-
-Optional properties:
-- resets:              Phandle to reset control that resets core and wrapper.
-- interrupts:          specifies interrupts from controller wrapper used
-                       to wakeup from low power/susepnd state. Must contain
-                       one or more entry for interrupt-names property
-- interrupt-names:     Must include the following entries:
-                       - "hs_phy_irq": The interrupt that is asserted when a
-                          wakeup event is received on USB2 bus
-                       - "ss_phy_irq": The interrupt that is asserted when a
-                          wakeup event is received on USB3 bus
-                       - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate
-                          interrupts for any wakeup event on DM and DP lines
-- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement.
-                               Used when dwc3 operates without SSPHY and only
-                               HS/FS/LS modes are supported.
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt   - USB3 QMP PHY
-Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
-
-Example device nodes:
-
-               hs_phy: phy@100f8800 {
-                       compatible = "qcom,qusb2-v2-phy";
-                       ...
-               };
-
-               ss_phy: phy@100f8830 {
-                       compatible = "qcom,qmp-v3-usb3-phy";
-                       ...
-               };
-
-               usb3_0: usb30@a6f8800 {
-                       compatible = "qcom,dwc3";
-                       reg = <0xa6f8800 0x400>;
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       ranges;
-
-                       interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
-                       interrupt-names = "hs_phy_irq", "ss_phy_irq",
-                                 "dm_hs_phy_irq", "dp_hs_phy_irq";
-
-                       clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
-                               <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
-                               <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
-                       clock-names = "core", "mock_utmi", "sleep";
-
-                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
-                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
-                       assigned-clock-rates = <19200000>, <133000000>;
-
-                       resets = <&gcc GCC_USB30_PRIM_BCR>;
-                       reset-names = "core_reset";
-                       power-domains = <&gcc USB30_PRIM_GDSC>;
-                       qcom,select-utmi-as-pipe-clk;
-
-                       dwc3@10000000 {
-                               compatible = "snps,dwc3";
-                               reg = <0x10000000 0xcd00>;
-                               interrupts = <0 205 0x4>;
-                               phys = <&hs_phy>, <&ss_phy>;
-                               phy-names = "usb2-phy", "usb3-phy";
-                               dr_mode = "host";
-                       };
-               };
-

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +155 -1

new file mode 100644
index 0000000..48ff9c5
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+  - Manu Gautam <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,msm8996-dwc3
+          - qcom,msm8998-dwc3
+          - qcom,sdm845-dwc3
+      - const: qcom,dwc3
+
+  reg:
+    description: Offset and length of register set for QSCRATCH wrapper
+    maxItems: 1
+
+  power-domains:
+    description: specifies a phandle to PM domain provider node
+    maxItems: 1
+
+  clocks:
+    description:
+      A list of phandle and clock-specifier pairs for the clocks
+      listed in clock-names.
+    maxItems: 5
+
+  clock-names:
+    maxItems: 5
+    items:
+    #Master/Core clock, have to be >= 125 MHz for SS operation
+    # and >= 60MHz for HS operation
+      - const: core
+    #Mock utmi clock needed for ITP/SOF generation in host mode.
+    #Its frequency should be 19.2MHz.
+      - const: mock_utmi
+    #Sleep clock, used for wakeup when USB3 core goes into low power mode (U3).
+      - const: sleep
+    #Optional:System bus AXI clock.Not present on "qcom,msm8996-dwc3" compatible.
+      - const: iface
+    #Optional:System Config NOC clock.Not present on "qcom,msm8996-dwc3" compatible.
+      - const: cfg_noc
+
+  assigned-clocks:
+    description:
+      Should be MOCK_UTMI_CLK and MASTER_CLK
+    maxItems: 2
+
+  assigned-clock-rates:
+    description:
+      Should be 19.2Mhz (192000000) for MOCK_UTMI_CLK
+      >=125Mhz (125000000) for MASTER_CLK in SS mode
+      >=60Mhz (60000000) for MASTER_CLK in HS mode
+    maxItems: 2
+
+  resets:
+    maxItems: 1
+    description: Phandle to reset control that resets core and wrapper.
+
+  interrupts:
+    description:
+      specifies interrupts from controller wrapper used
+      to wakeup from low power/suspend state.Must contain
+      one or more entry for interrupt-names property
+
+  interrupt-names:
+    $ref: /schemas/types.yaml#/definitions/string-array
+    items:
+      #The interrupt that is asserted when a wakeup event
+      #is received on USB2 bus
+      - const: hs_phy_irq
+      #The interrupt that is asserted when a wakeup event
+      #is received on USB3 bus
+      - const: ss_phy_irq
+      #Separate interrupts for any wakeup event on DM and DP lines
+      - const: dm_hs_phy_irq
+      - const: dp_hs_phy_irq
+
+  qcom,select-utmi-as-pipe-clk:
+    description:
+      if present, disable USB3 pipe_clk requirement.
+      Used when dwc3 operates without SSPHY and only
+      HS/FS/LS modes are supported.
+    type: boolean
+
+#Required child node:
+#A child node must exist to represent the core DWC3 IP block. The name of
+#the node is not important. The content of the node is defined in dwc3.txt.
+
+#Phy documentation is provided in the following places:
+#Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt   - USB3 QMP PHY
+#Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - clock-names
+  - assigned-clocks
+  - assigned-clock-rates
+
+examples:
+  - |
+    hs_phy: phy@100f8800 {
+            compatible = "qcom,qusb2-v2-phy";
+            ...
+        };
+
+        ss_phy: phy@100f8830 {
+            compatible = "qcom,qmp-v3-usb3-phy";
+            ...
+        };
+
+        usb3_0: usb30@a6f8800 {
+            compatible = "qcom,dwc3";
+            reg = <0xa6f8800 0x400>;
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
+
+            interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
+            interrupt-names = "hs_phy_irq", "ss_phy_irq",
+                    "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+            clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+            clock-names = "core", "mock_utmi", "sleep";
+
+            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                              <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+            assigned-clock-rates = <19200000>, <133000000>;
+
+            resets = <&gcc GCC_USB30_PRIM_BCR>;
+            reset-names = "core_reset";
+            power-domains = <&gcc USB30_PRIM_GDSC>;
+            qcom,select-utmi-as-pipe-clk;
+
+            dwc3@10000000 {
+                compatible = "snps,dwc3";
+                reg = <0x10000000 0xcd00>;
+                interrupts = <0 205 0x4>;
+                phys = <&hs_phy>, <&ss_phy>;
+                phy-names = "usb2-phy", "usb3-phy";
+                dr_mode = "host";
+            };
+        };
--

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Hi,

This is my first time reviewing a yaml conversion, so if I say something that seems wrong it might very well be. That being said...

Quoted 7 lines · Sandeep Maheswaram

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +0 -0

new file mode 100644
index 0000000..48ff9c5

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 10

Quoted 10 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10 -0

@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+  - Manu Gautam <[email protected]>

Really weird that you list him as the maintainer but don't CC him on this email. Is he still the maintainer?

Quoted 12 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +12 -0

+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,msm8996-dwc3
+          - qcom,msm8998-dwc3
+          - qcom,sdm845-dwc3
+      - const: qcom,dwc3
+
+  reg:
+    description: Offset and length of register set for QSCRATCH wrapper
+    maxItems: 1

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 33

Quoted 10 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10 -0

+
+  power-domains:
+    description: specifies a phandle to PM domain provider node
+    maxItems: 1
+
+  clocks:
+    description:
+      A list of phandle and clock-specifier pairs for the clocks
+      listed in clock-names.
+    maxItems: 5

Add: "minItems: 3"

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 36

Quoted 2 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +2 -0

+  clock-names:
+    maxItems: 5

Remove "maxItems: 5". Having maxItems exactly equal to the number of items listed is the default.

Add "minItems: 3"

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 39

Quoted 3 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +3 -0

+    items:
+    #Master/Core clock, have to be >= 125 MHz for SS operation
+    # and >= 60MHz for HS operation

Rather than add these as comments, I think you can add them as descriptions up under the "clocks" section. Look at "Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml" as an example. Then you can also get rid of "maxItems: 5" in the "clocks" section".

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 46

Quoted 7 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +7 -0

+      - const: core
+    #Mock utmi clock needed for ITP/SOF generation in host mode.
+    #Its frequency should be 19.2MHz.
+      - const: mock_utmi
+    #Sleep clock, used for wakeup when USB3 core goes into low power mode (U3).
+      - const: sleep
+    #Optional:System bus AXI clock.Not present on "qcom,msm8996-dwc3" compatible.

spaces after a period. Also: once you move this up to be in the "description" of the clock node you can get rid of "Optional:" since it will be implied by "minItems: 3".

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 54

Quoted 8 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +8 -0

+      - const: iface
+    #Optional:System Config NOC clock.Not present on "qcom,msm8996-dwc3" compatible.
+      - const: cfg_noc
+
+  assigned-clocks:
+    description:
+      Should be MOCK_UTMI_CLK and MASTER_CLK
+    maxItems: 2

Instead, maybe:

assigned-clocks:
items:
- description: Phandle to MOCK_UTMI_CLK.
- description: Phandle to MASTER_CLK

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 61

Quoted 6 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +6 -0

+  assigned-clock-rates:
+    description:
+      Should be 19.2Mhz (192000000) for MOCK_UTMI_CLK
+      >=125Mhz (125000000) for MASTER_CLK in SS mode
+      >=60Mhz (60000000) for MASTER_CLK in HS mode
+    maxItems: 2

not new for your patch, but nit that "Mhz" should be "MHz". Also, maybe the above can be expressed by:

assigned-clock-rates:
items:
- const: 192000000
$ref: "/schemas/types.yaml#/definitions/uint32"

- oneOf:
# If SS mode
- minimum: 125000000
$ref: "/schemas/types.yaml#/definitions/uint32"
# If HS mode
- minimum: 60000000
$ref: "/schemas/types.yaml#/definitions/uint32"

...it's a little silly to specify that a number has to be either >= 60 MHz or >= 125 MHz but I'm not sure how to express it otherwise...

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 65

Quoted 4 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +3 -0

+  resets:
+    maxItems: 1
+    description: Phandle to reset control that resets core and wrapper.

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 71

Quoted 6 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +6 -0

+
+  interrupts:
+    description:
+      specifies interrupts from controller wrapper used
+      to wakeup from low power/suspend state.Must contain
+      one or more entry for interrupt-names property

Make the description proper sentences: start with a capital letter, include a space after your period, and end with a period.

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 74

Quoted 4 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +2 -0

+  interrupt-names:
+    $ref: /schemas/types.yaml#/definitions/string-array

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 77

Quoted 3 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +3 -0

+    items:
+      #The interrupt that is asserted when a wakeup event
+      #is received on USB2 bus

Like "clocks", I think these comments can be moved as "description" in the "interrupts" section.

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 90

Quoted 13 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +13 -0

+      - const: hs_phy_irq
+      #The interrupt that is asserted when a wakeup event
+      #is received on USB3 bus
+      - const: ss_phy_irq
+      #Separate interrupts for any wakeup event on DM and DP lines
+      - const: dm_hs_phy_irq
+      - const: dp_hs_phy_irq
+
+  qcom,select-utmi-as-pipe-clk:
+    description:
+      if present, disable USB3 pipe_clk requirement.
+      Used when dwc3 operates without SSPHY and only
+      HS/FS/LS modes are supported.

Start description with a capital letter?

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 95

Quoted 5 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +5 -0

+    type: boolean
+
+#Required child node:
+#A child node must exist to represent the core DWC3 IP block. The name of
+#the node is not important. The content of the node is defined in dwc3.txt.

Probably we should pick a name and list it as a real thing, not just a comment. I think you have "type: object". So maybe:

patternProperties:
"^dwc3@[0-9a-f]+$":
type: object
description:
A child node must exist to represent the core DWC3 IP block The content of the node is defined in dwc3.txt.

Eventually maybe we can include the "dwc3.yaml" file once it's created?

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 99

Quoted 5 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +3 -0

+#Phy documentation is provided in the following places:
+#Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt   - USB3 QMP PHY
+#Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY

Comments usually have a space after the "#". See example-schema.yaml. I wonder if this even needs to be here, though.

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 108

Quoted 8 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +8 -0

+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - clock-names
+  - assigned-clocks
+  - assigned-clock-rates

If I'm reading the old bindings properly "assigned-clocks" and "assigned-clock-rates" were previously not "required".

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 114

Quoted 6 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +6 -0

+
+examples:
+  - |
+    hs_phy: phy@100f8800 {
+            compatible = "qcom,qusb2-v2-phy";
+            ...

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 108

Quoted 1 line

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +1 -0

+        };

Your indentation for this whole example is off. The braces don't line up properly.

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 127

Quoted 12 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +12 -0

+
+        ss_phy: phy@100f8830 {
+            compatible = "qcom,qmp-v3-usb3-phy";
+            ...
+        };
+
+        usb3_0: usb30@a6f8800 {
+            compatible = "qcom,dwc3";
+            reg = <0xa6f8800 0x400>;
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;

#address-cells, #size-cells, and ranges are not documented in the schema. Do they need to be?

Quoted 7 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +6 -0

+
+            interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
+            interrupt-names = "hs_phy_irq", "ss_phy_irq",
+                    "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+            clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 143

Quoted 10 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10 -0

+                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+            clock-names = "core", "mock_utmi", "sleep";
+
+            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                              <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+            assigned-clock-rates = <19200000>, <133000000>;
+
+            resets = <&gcc GCC_USB30_PRIM_BCR>;
+            reset-names = "core_reset";

The 'reset-names' property is not in the schema and it doesn't appear to be removed. Remove from the example.

Quoted 12 lines

Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +12 -0

+            power-domains = <&gcc USB30_PRIM_GDSC>;
+            qcom,select-utmi-as-pipe-clk;
+
+            dwc3@10000000 {
+                compatible = "snps,dwc3";
+                reg = <0x10000000 0xcd00>;
+                interrupts = <0 205 0x4>;
+                phys = <&hs_phy>, <&ss_phy>;
+                phy-names = "usb2-phy", "usb3-phy";
+                dr_mode = "host";
+            };
+        };

Add compatible for SC7180 in usb dwc3 bindings.

Signed-off-by Sandeep Maheswaram <[email protected]>

---
 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
 1 file changed, 1 insertion(+)

Add compatible for SC7180 in usb dwc3 bindings.

Signed-off-by Sandeep Maheswaram <[email protected]>

---
 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
 1 file changed, 1 insertion(+)