FAILED: patch "[PATCH] PCI: rcar: Fix missing MACCTLR register setting in" failed to apply to 4.19-stable tree

The patch below does not apply to the 4.19-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 7c7e53e1c93df14690bd12c1f84730fef927a6f1 Mon Sep 17 00:00:00 2001
From: Yoshihiro Shimoda <[email protected]>
Date: Tue, 5 Nov 2019 19:51:29 +0900
Subject: [PATCH] PCI: rcar: Fix missing MACCTLR register setting in
initialization sequence

The R-Car Gen2/3 manual - available at:

https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg1m.html#documents

"RZ/G Series User's Manual: Hardware" section

strictly enforces the MACCTLR inizialization value - 39.3.1 - "Initial Setting of PCI Express":

"Be sure to write the initial value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT".

To avoid unexpected behavior and to match the SW initialization sequence guidelines, this patch programs the MACCTLR with the correct value.

Note that the MACCTLR.SPCHG bit in the MACCTLR register description reports that "Only writing 1 is valid and writing 0 is invalid" but this "invalid" has to be interpreted as a write-ignore aka "ignored", not "prohibited".

Reported-by Eugeniu Rosca <[email protected]>

Fixes c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")

Fixes be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")

Signed-off-by Yoshihiro Shimoda <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

Reviewed-by Geert Uytterhoeven <[email protected]>

Cc <[email protected]> # v5.2+

drivers/pci/controller/pcie-rcar.c +6 -0

index 40d8c54a17d1..94ba4fe21923 100644
@@ -91,8 +91,11 @@
 #define  LINK_SPEED_2_5GTS     (1 << 16)
 #define  LINK_SPEED_5_0GTS     (2 << 16)
 #define MACCTLR                        0x011058
+#define  MACCTLR_NFTS_MASK     GENMASK(23, 16) /* The name is from SH7786 */
 #define  SPEED_CHANGE          BIT(24)
 #define  SCRAMBLE_DISABLE      BIT(27)
+#define  LTSMDIS               BIT(31)
+#define  MACCTLR_INIT_VAL      (LTSMDIS | MACCTLR_NFTS_MASK)
 #define PMSR                   0x01105c
 #define MACS2R                 0x011078
 #define MACCGSPSETR            0x011084

@@ -613,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
        if (IS_ENABLED(CONFIG_PCI_MSI))
                rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
 
+       rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
+
        /* Finish initialization - establish a PCI Express link */
        rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
 

@@ -1235,6 +1240,7 @@ static int rcar_pcie_resume_noirq(struct device *dev)
                return 0;
 
        /* Re-establish the PCIe link */
+       rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
        rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
        return rcar_pcie_wait_for_dl(pcie);
 }