Add A618 GPU nodes
Subsystems (4)
PATCH v3 1/1 Add A618 GPU nodes
I used this branch qcom/arm64-for-5.6-to-be-rebased as suggested by Matthias. This patch needs the clock patches and the clock patches have not yet landed, so please apply the following series and patches in order
a) All patches from https://patchwork.kernel.org/project/linux-clk/list/?series=203517&state=%2a&archive=both
b) Patches 1 and 2 from https://patchwork.kernel.org/project/linux-clk/list/?series=203527&archive=both&state=%2a
c) All patches from https://patchwork.kernel.org/project/linux-clk/list/?series=221739&archive=both&state=%2a
d) https://lore.kernel.org/linux-arm-msm/20200124144154.v2.10.I1a4b93fb005791e29a9dcf288fc8bd459a555a59%40changeid/raw
e) This patch "arm64: dts: qcom: sc7180: Add A618 gpu dt blob"
v3: Addressed review comments from previous submits. Also removed the interconnect bindings from this patch and I will submit as a new patch with its dependencies listed. Also I will be sending a new patch for updating the bindings documentation.
Sharat Masetty (1):
arm64: dts: qcom: sc7180: Add A618 gpu dt blob
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+)
--
1.9.1
PATCH v3 1/1 arm64: dts: qcom: sc7180: Add A618 gpu dt blob
This patch adds the required dt nodes and properties to enabled A618 GPU.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +102 -0
@@ -1043,6 +1043,108 @@ }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk"; + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>; + power-domain-names = "cx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sc7180-gpucc"; reg = <0 0x05090000 0 0x9000>;
Signature · 1 line
1.9.1
Re: [PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Hi,
Quoted 11 lines · Sharat Masetty
arch/arm64/boot/dts/qcom/sc7180.dtsi +10
-0+ adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
arch/arm64/boot/dts/qcom/sc7180.dtsi line 1116
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +10
-0+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk";
Repeated comment from v2 feedback:
Please send a patch to:
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
...adding 'qcom,sc7180-smmu-v2'. If you do this it will point out that you've added a new clock: "mem_iface_clk". Is this truly a new clock in sc7180 compared to previous IOMMUs? ...or is it not really needed?
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
arch/arm64/boot/dts/qcom/sc7180.dtsi line 1134
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +10
-0+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>; + power-domain-names = "cx";
As per continued comments on v2, please see if this works for you:
power-domains = <&gpucc CX_GDSC>, <0>; power-domain-names = "cx", "gx";
...and work to get something more real for "gx" ASAP. It did seem to boot for me and (unless someone disagrees) it seems better than totally leaving it out / violating the bindings?
-Doug
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Re: [PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Quoted 38 lines · Doug Anderson
Hi,
Quoted 27 lines · Sharat Masetty
(quoted diff) +2
-0+ adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2","qcom,smmu-v2";
arch/arm64/boot/dts/qcom/sc7180.dtsi +4
-0+ reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229
IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI231IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI364IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI365IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI366IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI367IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI368IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI369IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI370IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI371IRQ_TYPE_EDGE_RISING>;arch/arm64/boot/dts/qcom/sc7180.dtsi line 1116
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk";Repeated comment from v2 feedback:
Quoted 8 lines
Please send a patch to:
Documentation/devicetree/bindings/iommu/arm,smmu.yaml...adding 'qcom,sc7180-smmu-v2'. If you do this it will point out that you've added a new clock: "
mem_iface_clk". Is this truly a new clock in sc7180 compared to previous IOMMUs? ...or is it not really needed?
I can confirm that this clock is needed for SC7180. I will send out a new patch to update the documentation this week.
Quoted 26 lines
Quoted 11 lines
(quoted diff) +2
-0+ gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0","qcom,adreno-gmu";
+ reg = <00x0506a00000x31000>, <00x0b290000
00x10000>,arch/arm64/boot/dts/qcom/sc7180.dtsi +3
-0+ <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = <GIC_SPI 304
IRQ_TYPE_LEVEL_HIGH>,arch/arm64/boot/dts/qcom/sc7180.dtsi line 1134
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +9
-0+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>; + power-domain-names = "cx";As per continued comments on v2, please see if this works for you:
power-domains = <&gpucc CX_GDSC>, <0>; power-domain-names = "cx", "gx";
Quoted 6 lines
...and work to get something more real for "gx" ASAP. It did seem to boot for me and (unless someone disagrees) it seems better than totally leaving it out / violating the bindings?
-Doug
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https://lists.freedesktop.org/mailman/listinfo/dri-devel