msm/gpu/a6xx: use the DMA-API for GMU memory allocations

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.

Signed-off-by Jordan Crouse <[email protected]>

---

 .../devicetree/bindings/display/msm/gmu.txt        | 116 -------------------

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -12

-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"

Hi Jordan.

Quoted 19 lines · Jordan Crouse

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.

Signed-off-by Jordan Crouse <[email protected]>

---

 .../devicetree/bindings/display/msm/gmu.txt        | 116 -------------------

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -12

-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"

Documentation/devicetree/bindings/display/msm/gmu.txt line 26

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -10

-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"

The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong.

Documentation/devicetree/bindings/display/msm/gmu.txt line 36

Quoted 10 lines

-- power-domains: should be:

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -9

-	<&clock_gpucc GPU_CX_GDSC>
-	<&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

This property is not included in the new binding.

Everything else looked fine to me.
With sram added - or expalined in commit why it is dropped:

Acked-by Sam Ravnborg <[email protected]>

Sam
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Quoted 35 lines · Sam Ravnborg

Hi Jordan.

Quoted 19 lines · Jordan Crouse

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.

Signed-off-by Jordan Crouse <[email protected]>

---

 .../devicetree/bindings/display/msm/gmu.txt        | 116 -------------------

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -12

-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"

Documentation/devicetree/bindings/display/msm/gmu.txt line 26

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -10

-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"

The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong.

Quoted 11 lines

Documentation/devicetree/bindings/display/msm/gmu.txt line 36

Quoted 10 lines

-- power-domains: should be:

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -9

-   <&clock_gpucc GPU_CX_GDSC>
-   <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

This property is not included in the new binding.

Yeah, that guy shouldn't be here. I'm not sure how it got there in the first place but I'll update the commit log. Thanks for the poke.

Jordan

Quoted 9 lines

Everything else looked fine to me.
With sram added - or expalined in commit why it is dropped:

Acked-by Sam Ravnborg <[email protected]>

Sam
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Quoted 49 lines · Jordan Crouse

Quoted 46 lines · Sam Ravnborg

Hi Jordan.

Quoted 19 lines · Jordan Crouse

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.

Signed-off-by Jordan Crouse <[email protected]>

---

 .../devicetree/bindings/display/msm/gmu.txt        | 116 -------------------

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -12

-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"

Documentation/devicetree/bindings/display/msm/gmu.txt line 26

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -10

-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"

The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong.

Documentation/devicetree/bindings/display/msm/gmu.txt line 36

Quoted 10 lines

-- power-domains: should be:

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -9

-   <&clock_gpucc GPU_CX_GDSC>
-   <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

This property is not included in the new binding.

Quoted 2 lines

Yeah, that guy shouldn't be here. I'm not sure how it got there in the first place but I'll update the commit log. Thanks for the poke.

I thought this was something Brian M added for older targets (A4XX?). Perhaps he should chime in?

Quoted 50 lines · Jeffrey Hugo

Quoted 49 lines · Jordan Crouse

Quoted 46 lines · Sam Ravnborg

Hi Jordan.

Quoted 19 lines · Jordan Crouse

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.

Signed-off-by Jordan Crouse <[email protected]>

---

 .../devicetree/bindings/display/msm/gmu.txt        | 116 -------------------

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -12

-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"

Documentation/devicetree/bindings/display/msm/gmu.txt line 26

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -10

-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"

The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong.

Documentation/devicetree/bindings/display/msm/gmu.txt line 36

Quoted 10 lines

-- power-domains: should be:

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -9

-   <&clock_gpucc GPU_CX_GDSC>
-   <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

This property is not included in the new binding.

Quoted 5 lines

Quoted 2 lines

Yeah, that guy shouldn't be here. I'm not sure how it got there in the first place but I'll update the commit log. Thanks for the poke.

I thought this was something Brian M added for older targets (A4XX?). Perhaps he should chime in?

Yes, this is needed for older systems with a3xx and a4xx GPUs.

Brian

Quoted 57 lines · Brian Masney

Quoted 55 lines · Jeffrey Hugo

Quoted 49 lines · Jordan Crouse

Quoted 35 lines · Sam Ravnborg

Hi Jordan.

Quoted 19 lines · Jordan Crouse

Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.

Signed-off-by Jordan Crouse <[email protected]>

---

 .../devicetree/bindings/display/msm/gmu.txt        | 116 -------------------

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -12

-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"

Documentation/devicetree/bindings/display/msm/gmu.txt line 26

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -10

-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"

The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong.

Quoted 11 lines

Documentation/devicetree/bindings/display/msm/gmu.txt line 36

Quoted 10 lines

-- power-domains: should be:

Documentation/devicetree/bindings/display/msm/gmu.txt deleted +0 -9

-   <&clock_gpucc GPU_CX_GDSC>
-   <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

This property is not included in the new binding.

Quoted 2 lines

Yeah, that guy shouldn't be here. I'm not sure how it got there in the first place but I'll update the commit log. Thanks for the poke.

I thought this was something Brian M added for older targets (A4XX?). Perhaps he should chime in?

Quoted 1 line

Yes, this is needed for older systems with a3xx and a4xx GPUs.

Okay, this got added to the wrong place. The GMU is a specific entity only valid for a6xx targets. From the looks of the example the sram should be in the GPU definition. Do you want to submit a patch to move it or should I (and lets hope Rob doesn't insist on converting GPU to YAML).

-----Original Message-----
From: dri-devel <[email protected]> On Behalf Of Jordan Crouse
Sent: Monday, March 2, 2020 1:24 PM
To: [email protected]
Cc: David Airlie <[email protected]>; [email protected]; [email protected]; [email protected]; dri- [email protected]; Douglas Anderson <[email protected]>; Sean Paul <[email protected]>
Subject: [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

The GMU has very few memory allocations and uses a flat memory space so there is no good reason to go out of our way to bypass the DMA APIs which were basically designed for this exact scenario.

v3: Set the dma mask correctly and use dma_addr_t for the iova type

v2: Pass force_dma false to of_dma_configure to require that the DMA region be set up and return error from of_dma_configure to fail probe.

Signed-off-by Jordan Crouse <[email protected]>

---

drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ++++---------------------------
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 +--

2 files changed, 15 insertions(+), 107 deletions(-)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -0

index 748cd37..854ba30 100644
@@ -2,6 +2,7 @@
 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
 
 #include <linux/clk.h>
+#include <linux/dma-mapping.h>
 #include <linux/interconnect.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_opp.h>

@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
 

static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)
{

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -3

-	int count, i;
-	u64 iova;
-

	if (IS_ERR_OR_NULL(bo))
		return;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -9

-	count = bo->size >> PAGE_SHIFT;
-	iova = bo->iova;
-
-	for (i = 0; i < count; i++, iova += PAGE_SIZE) {
-		iommu_unmap(gmu->domain, iova, PAGE_SIZE);
-		__free_pages(bo->pages[i], 0);
-	}
-
-	kfree(bo->pages);
+	dma_free_attrs(gmu->dev, bo->size, bo->virt, bo->iova, bo->attrs);

	kfree(bo);
}

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -1

@@ -942,94 +932,23 @@ static struct a6xx_gmu_bo
 *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
 		size_t size)
 {
 	struct a6xx_gmu_bo *bo;
-	int ret, count, i;
 
 	bo = kzalloc(sizeof(*bo), GFP_KERNEL);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -73

-	bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
-	if (!bo->pages) {
+	if (!bo->virt) {
 		kfree(bo);
 		return ERR_PTR(-ENOMEM);
 	}
 
-	for (i = 0; i < count; i++) {
-		bo->pages[i] = alloc_page(GFP_KERNEL);
-		if (!bo->pages[i])
-			goto err;
-	}
-
-	bo->iova = gmu->uncached_iova_base;
-
-	for (i = 0; i < count; i++) {
-		ret = iommu_map(gmu->domain,
-			bo->iova + (PAGE_SIZE * i),
-			page_to_phys(bo->pages[i]), PAGE_SIZE,
-			IOMMU_READ | IOMMU_WRITE);
-
-		if (ret) {
-			DRM_DEV_ERROR(gmu->dev, "Unable to map GMU
 buffer object\n");
-
-			for (i = i - 1 ; i >= 0; i--)
-				iommu_unmap(gmu->domain,
-					bo->iova + (PAGE_SIZE * i),
-					PAGE_SIZE);
-
-			goto err;
-		}
-	}
-
-	bo->virt = vmap(bo->pages, count, VM_IOREMAP,
-		pgprot_writecombine(PAGE_KERNEL));
-	if (!bo->virt)
-		goto err;
-
-	/* Align future IOVA addresses on 1MB boundaries */
-	gmu->uncached_iova_base += ALIGN(size, SZ_1M);
-
 	return bo;
-
-err:
-	for (i = 0; i < count; i++) {
-		if (bo->pages[i])
-			__free_pages(bo->pages[i], 0);
-	}
-
-	kfree(bo->pages);
-	kfree(bo);
-
-	return ERR_PTR(-ENOMEM);
-}
-
-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
-{
-	int ret;
-
-	/*
-	 * The GMU address space is hardcoded to treat the range
-	 * 0x60000000 - 0x80000000 as un-cached memory. All buffers shared
-	 * between the GMU and the CPU will live in this space
-	 */
-	gmu->uncached_iova_base = 0x60000000;
-
-
-	gmu->domain = iommu_domain_alloc(&platform_bus_type);
-	if (!gmu->domain)
-		return -ENODEV;
-
-	ret = iommu_attach_device(gmu->domain, gmu->dev);
-
-	if (ret) {
-		iommu_domain_free(gmu->domain);
-		gmu->domain = NULL;
-	}
-
-	return ret;
 }

/* Return the 'arc-level' for the given frequency */

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +7 -5

@@ -1289,10 +1208,6 @@ void a6xx_gmu_remove(struct a6xx_gpu
 *a6xx_gpu)
 
 	a6xx_gmu_memory_free(gmu, gmu->hfi);
 
-	iommu_detach_device(gmu->domain, gmu->dev);
-
-	iommu_domain_free(gmu->domain);
-
 	free_irq(gmu->gmu_irq, gmu);
 	free_irq(gmu->hfi_irq, gmu);

@@ -1313,7 +1228,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
 struct device_node *node)
 
 	gmu->dev = &pdev->dev;
 
-	of_dma_configure(gmu->dev, node, true);
+	/* Pass force_dma false to require the DT to set the dma region */
+	ret = of_dma_configure(gmu->dev, node, false);
+	if (ret)
+		return ret;
+
+	/* Set the mask after the of_dma_configure() */
+	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(31));
 
 	/* Fow now, don't do anything fancy until we get our feet under us */

	gmu->idle_level = GMU_IDLE_STATE_ACTIVE;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -5

@@ -1325,11 +1246,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
 struct device_node *node)
 	if (ret)
 		goto err_put_device;
 
-	/* Set up the IOMMU context bank */
-	ret = a6xx_gmu_memory_probe(gmu);
-	if (ret)
-		goto err_put_device;
-
 	/* Allocate memory for for the HFI queues */
 	gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K);

	if (IS_ERR(gmu->hfi))

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -0

@@ -1375,11 +1291,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
 struct device_node *node)

err_memory:

	a6xx_gmu_memory_free(gmu, gmu->hfi);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -5

-	if (gmu->domain) {
-		iommu_detach_device(gmu->domain, gmu->dev);
-
-		iommu_domain_free(gmu->domain);
-	}

	ret = -ENODEV;

err_put_device:

drivers/gpu/drm/msm/adreno/a6xx_gmu.h +2 -6

index 2af91ed..d10cddd 100644
@@ -12,8 +12,8 @@
 struct a6xx_gmu_bo {
 	void *virt;
 	size_t size;
-	u64 iova;
-	struct page **pages;
+	dma_addr_t iova;
+	unsigned long attrs;
 };
 
 /*

@@ -49,9 +49,6 @@ struct a6xx_gmu {
 	int hfi_irq;
 	int gmu_irq;
 
-	struct iommu_domain *domain;
-	u64 uncached_iova_base;
-
 	struct device *gxpd;
 
 	int idle_level;
--

2.7.4
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Quoted 74 lines

-----Original Message-----
From: dri-devel <[email protected]> On Behalf Of Jordan Crouse
Sent: Monday, March 2, 2020 1:24 PM
To: [email protected]
Cc: David Airlie <[email protected]>; [email protected]; [email protected]; [email protected]; dri- [email protected]; Douglas Anderson <[email protected]>; Sean Paul <[email protected]>
Subject: [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

The GMU has very few memory allocations and uses a flat memory space so there is no good reason to go out of our way to bypass the DMA APIs which were basically designed for this exact scenario.

v3: Set the dma mask correctly and use dma_addr_t for the iova type

v2: Pass force_dma false to of_dma_configure to require that the DMA region be set up and return error from of_dma_configure to fail probe.

Signed-off-by Jordan Crouse <[email protected]>

---

drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ++++---------------------------
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 +--

2 files changed, 15 insertions(+), 107 deletions(-)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -0

index 748cd37..854ba30 100644
@@ -2,6 +2,7 @@
 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
 
 #include <linux/clk.h>
+#include <linux/dma-mapping.h>
 #include <linux/interconnect.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_opp.h>

@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
 

static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)
{

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -3

-	int count, i;
-	u64 iova;
-

	if (IS_ERR_OR_NULL(bo))
		return;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -9

-	count = bo->size >> PAGE_SHIFT;
-	iova = bo->iova;
-
-	for (i = 0; i < count; i++, iova += PAGE_SIZE) {
-		iommu_unmap(gmu->domain, iova, PAGE_SIZE);
-		__free_pages(bo->pages[i], 0);
-	}
-
-	kfree(bo->pages);
+	dma_free_attrs(gmu->dev, bo->size, bo->virt, bo->iova, bo->attrs);

	kfree(bo);
}

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -1

@@ -942,94 +932,23 @@ static struct a6xx_gmu_bo
 *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
 		size_t size)
 {
 	struct a6xx_gmu_bo *bo;
-	int ret, count, i;
 
 	bo = kzalloc(sizeof(*bo), GFP_KERNEL);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c static struct a6xx_gmu_bo · line 946

Quoted 10 lines

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +3 -1

 	if (!bo)
 		return ERR_PTR(-ENOMEM);
 
 	bo->size = PAGE_ALIGN(size);
+	bo->attrs = DMA_ATTR_WRITE_COMBINE;
 
-	count = bo->size >> PAGE_SHIFT;
+	bo->virt = dma_alloc_attrs(gmu->dev, bo->size, &bo->iova,
 GFP_KERNEL,
+		bo->attrs);

I see that there is a dma_alloc_wc()/dma_free_wc() which appears to do the same set up that you are using here.

Could you use those wrappers, or do you need to keep track of the bo->attrs elsewhere?

Mike

Quoted 169 lines

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -73

-	bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
-	if (!bo->pages) {
+	if (!bo->virt) {
 		kfree(bo);
 		return ERR_PTR(-ENOMEM);
 	}
 
-	for (i = 0; i < count; i++) {
-		bo->pages[i] = alloc_page(GFP_KERNEL);
-		if (!bo->pages[i])
-			goto err;
-	}
-
-	bo->iova = gmu->uncached_iova_base;
-
-	for (i = 0; i < count; i++) {
-		ret = iommu_map(gmu->domain,
-			bo->iova + (PAGE_SIZE * i),
-			page_to_phys(bo->pages[i]), PAGE_SIZE,
-			IOMMU_READ | IOMMU_WRITE);
-
-		if (ret) {
-			DRM_DEV_ERROR(gmu->dev, "Unable to map GMU
 buffer object\n");
-
-			for (i = i - 1 ; i >= 0; i--)
-				iommu_unmap(gmu->domain,
-					bo->iova + (PAGE_SIZE * i),
-					PAGE_SIZE);
-
-			goto err;
-		}
-	}
-
-	bo->virt = vmap(bo->pages, count, VM_IOREMAP,
-		pgprot_writecombine(PAGE_KERNEL));
-	if (!bo->virt)
-		goto err;
-
-	/* Align future IOVA addresses on 1MB boundaries */
-	gmu->uncached_iova_base += ALIGN(size, SZ_1M);
-
 	return bo;
-
-err:
-	for (i = 0; i < count; i++) {
-		if (bo->pages[i])
-			__free_pages(bo->pages[i], 0);
-	}
-
-	kfree(bo->pages);
-	kfree(bo);
-
-	return ERR_PTR(-ENOMEM);
-}
-
-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
-{
-	int ret;
-
-	/*
-	 * The GMU address space is hardcoded to treat the range
-	 * 0x60000000 - 0x80000000 as un-cached memory. All buffers shared
-	 * between the GMU and the CPU will live in this space
-	 */
-	gmu->uncached_iova_base = 0x60000000;
-
-
-	gmu->domain = iommu_domain_alloc(&platform_bus_type);
-	if (!gmu->domain)
-		return -ENODEV;
-
-	ret = iommu_attach_device(gmu->domain, gmu->dev);
-
-	if (ret) {
-		iommu_domain_free(gmu->domain);
-		gmu->domain = NULL;
-	}
-
-	return ret;
 }

/* Return the 'arc-level' for the given frequency */

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +7 -5

@@ -1289,10 +1208,6 @@ void a6xx_gmu_remove(struct a6xx_gpu
 *a6xx_gpu)
 
 	a6xx_gmu_memory_free(gmu, gmu->hfi);
 
-	iommu_detach_device(gmu->domain, gmu->dev);
-
-	iommu_domain_free(gmu->domain);
-
 	free_irq(gmu->gmu_irq, gmu);
 	free_irq(gmu->hfi_irq, gmu);

@@ -1313,7 +1228,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
 struct device_node *node)
 
 	gmu->dev = &pdev->dev;
 
-	of_dma_configure(gmu->dev, node, true);
+	/* Pass force_dma false to require the DT to set the dma region */
+	ret = of_dma_configure(gmu->dev, node, false);
+	if (ret)
+		return ret;
+
+	/* Set the mask after the of_dma_configure() */
+	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(31));
 
 	/* Fow now, don't do anything fancy until we get our feet under us */

	gmu->idle_level = GMU_IDLE_STATE_ACTIVE;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -5

@@ -1325,11 +1246,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
 struct device_node *node)
 	if (ret)
 		goto err_put_device;
 
-	/* Set up the IOMMU context bank */
-	ret = a6xx_gmu_memory_probe(gmu);
-	if (ret)
-		goto err_put_device;
-
 	/* Allocate memory for for the HFI queues */
 	gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K);

	if (IS_ERR(gmu->hfi))

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -0

@@ -1375,11 +1291,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
 struct device_node *node)

err_memory:

	a6xx_gmu_memory_free(gmu, gmu->hfi);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +0 -5

-	if (gmu->domain) {
-		iommu_detach_device(gmu->domain, gmu->dev);
-
-		iommu_domain_free(gmu->domain);
-	}

	ret = -ENODEV;

err_put_device:

drivers/gpu/drm/msm/adreno/a6xx_gmu.h +2 -6

index 2af91ed..d10cddd 100644
@@ -12,8 +12,8 @@
 struct a6xx_gmu_bo {
 	void *virt;
 	size_t size;
-	u64 iova;
-	struct page **pages;
+	dma_addr_t iova;
+	unsigned long attrs;
 };
 
 /*

@@ -49,9 +49,6 @@ struct a6xx_gmu {
 	int hfi_irq;
 	int gmu_irq;
 
-	struct iommu_domain *domain;
-	u64 uncached_iova_base;
-
 	struct device *gxpd;
 
 	int idle_level;
--

2.7.4
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