Add support for DisplayPort driver on SnapDragon.

From: Chandan Uddaraju <[email protected]>

Add bindings for Snapdragon DisplayPort and
display-port PLL driver.

Changes in V2:
Provide details about sel-gpio

Changes in V4:
Provide details about max dp lanes
Change the commit text

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

---
 .../devicetree/bindings/display/msm/dp.txt         | 252 +++++++++++++++++++++
 .../devicetree/bindings/display/msm/dpu.txt        |  16 +-
 2 files changed, 264 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt

From: Chandan Uddaraju <[email protected]>

Add bindings for Snapdragon DisplayPort and
display-port PLL driver.

Changes in V2:
Provide details about sel-gpio

Changes in V4:
Provide details about max dp lanes
Change the commit text

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

---
 .../devicetree/bindings/display/msm/dp.txt         | 252 +++++++++++++++++++++
 .../devicetree/bindings/display/msm/dpu.txt        |  16 +-
 2 files changed, 264 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt

Documentation/devicetree/bindings/display/msm/dp.txt new file +9 -0

new file mode 100644
index 0000000..1a4e17f
@@ -0,0 +1,252 @@
+Qualcomm Technologies, Inc.
+DP is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification.
+DP Controller: Required properties:
+- compatible:           Should be "qcom,dp-display".
+- reg:                  Base address and length of DP hardware's memory mapped regions.
+- cell-index:           Specifies the controller instance.
+- reg-names:            A list of strings that name the list of regs.
+                       "dp_ahb" - DP controller memory region.
+                       "dp_aux" - DP AUX memory region.

Documentation/devicetree/bindings/display/msm/dp.txt new file +33 -0

+- pll-node:            phandle to DP PLL node.
+- vdda-1p2-supply:             phandle to vdda 1.2V regulator node.
+- vdda-0p9-supply:             phandle to vdda 0.9V regulator node.
+- qcom,aux-cfg0-settings:              Specifies the DP AUX configuration 0 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg1-settings:              Specifies the DP AUX configuration 1 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg2-settings:              Specifies the DP AUX configuration 2 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg3-settings:              Specifies the DP AUX configuration 3 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg4-settings:              Specifies the DP AUX configuration 4 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg5-settings:              Specifies the DP AUX configuration 5 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg6-settings:              Specifies the DP AUX configuration 6 settings. The first
+                                       entry in this array corresponds to the register offset
+                                       within DP AUX, while the remaining entries indicate the
+                                       programmable values.
+- qcom,aux-cfg7-settings:              Specifies the DP AUX configuration 7 settings. The first
+                                       entry in this array corresponds to the register offset

Documentation/devicetree/bindings/display/msm/dp.txt new file +5 -0

+- qcom,<type>-supply-entries:          A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types"
+                                       can be "core", "ctrl", and "phy". Within the same type,
+                                       there can be more than one instance of this binding,
+                                       in which case the entry would be appended with the
+                                       supply entry index.

Documentation/devicetree/bindings/display/msm/dp.txt new file +14 -0

+               cell-index = <0>;
+               compatible = "qcom,dp-display";
+
+               reg =   <0 0x90000 0x0dc>,
+                       <0 0x90200 0x0c0>,
+                       <0 0x90400 0x508>,
+                       <0 0x90a00 0x094>,
+                       <1 0xeaa00 0x200>,
+                       <1 0xea200 0x200>,
+                       <1 0xea600 0x200>,
+                       <2 0x02000 0x1a0>,
+                       <3 0x00000 0x621c>,
+                       <1 0xea000 0x180>,
+                       <1 0xe8000 0x20>,

Documentation/devicetree/bindings/display/msm/dp.txt new file +92 -0

+               clocks =  <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+                       <&rpmhcc RPMH_CXO_CLK>,
+                       <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+                       <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                       <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+               clock-names = "core_aux_clk", "core_ref_clk_src",
+                       "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+                       "core_usb_pipe_clk", "ctrl_link_clk",
+                       "ctrl_link_iface_clk", "ctrl_pixel_clk",
+                       "crypto_clk", "pixel_clk_rcg";
+
+               pll-node = <&dp_pll>;
+               vdda-1p2-supply = <&vreg_l3c_1p2>;
+               vdda-0p9-supply = <&vreg_l4a_0p8>;
+               qcom,aux-cfg0-settings = [20 00];
+               qcom,aux-cfg1-settings = [24 13 23 1d];
+               qcom,aux-cfg2-settings = [28 24];
+               qcom,aux-cfg3-settings = [2c 00];
+               qcom,aux-cfg4-settings = [30 0a];
+               qcom,aux-cfg5-settings = [34 26];
+               qcom,aux-cfg6-settings = [38 0a];
+               qcom,aux-cfg7-settings = [3c 03];
+               qcom,aux-cfg8-settings = [40 bb];
+               qcom,aux-cfg9-settings = [44 03];
+
+               qcom,max-pclk-frequency-khz = <675000>;
+               qcom,max-lanes-for-dp = <2>;
+
+               qcom,ctrl-supply-entries {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       qcom,ctrl-supply-entry@0 {
+                               reg = <0>;
+                               qcom,supply-name = "vdda-1p2";
+                               qcom,supply-min-voltage = <1200000>;
+                               qcom,supply-max-voltage = <1200000>;
+                               qcom,supply-enable-load = <21800>;
+                               qcom,supply-disable-load = <4>;
+                       };
+               };
+
+               qcom,phy-supply-entries {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       qcom,phy-supply-entry@0 {
+                               reg = <0>;
+                               qcom,supply-name = "vdda-0p9";
+                               qcom,supply-min-voltage = <880000>;
+                               qcom,supply-max-voltage = <880000>;
+                               qcom,supply-enable-load = <36000>;
+                               qcom,supply-disable-load = <32>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               dp_in: endpoint {
+                                       remote-endpoint = <&dpu_intf0_out>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               dp_out: endpoint {
+                               };
+                       };
+               };
+       };
+
+       dp_pll: dp-pll@c011000 {
+               compatible = "qcom,dp-pll-10nm";
+               label = "DP PLL";
+               cell-index = <0>;
+               #clock-cells = <1>;
+
+               reg = <1 0xea000 0x200>,
+                     <1 0xeaa00 0x200>,
+                     <1 0xea200 0x200>,
+                     <1 0xea600 0x200>,
+                     <2 0x03000 0x8>;
+               reg-names = "pll_base", "phy_base", "ln_tx0_base",

Documentation/devicetree/bindings/display/msm/dpu.txt +11 -2

+       Port 1 -> DPU_INTF1 (DSI1)
+       Port 2 -> DPU_INTF2 (DSI2)
 
 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate assignment

@@ -125,13 +126,20 @@ Example:
 
                                port@0 {
                                        reg = <0>;
-                                       dpu_intf1_out: endpoint {
-                                               remote-endpoint = <&dsi0_in>;
+                                       dpu_intf0_out: endpoint {
+                                               remote-endpoint = <&dp_in>;
                                        };
                                };
 
                                port@1 {
                                        reg = <1>;
+                                       dpu_intf1_out: endpoint {
+                                               remote-endpoint = <&dsi0_in>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
                                        dpu_intf2_out: endpoint {
                                                remote-endpoint = <&dsi1_in>;
                                        };

Signature · 1 line

$(echo -e 'The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,

Quoting Vara Reddy (2020-03-04 16:10:24)

Quoted 14 lines

From: Chandan Uddaraju <[email protected]>

Add bindings for Snapdragon DisplayPort and
display-port PLL driver.

Changes in V2:
Provide details about sel-gpio

Changes in V4:
Provide details about max dp lanes
Change the commit text

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

Quoted 7 lines

---
 .../devicetree/bindings/display/msm/dp.txt         | 252 
+++++++++++++++++++++
 .../devicetree/bindings/display/msm/dpu.txt        |  16 +-
 2 files changed, 264 insertions(+), 4 deletions(-)
 create mode 100644 

Documentation/devicetree/bindings/display/msm/dp.txt

Having this in YAML will certainly make it easier to review. Please do that as Rob H has asked.

Quoted 30 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +2 -0

new file mode 100644
index 0000000..1a4e17f
@@ -0,0 +1,252 @@
+Qualcomm Technologies, Inc.
+DP is the master Display Port device which supports DP host 

controllers that are compatible with VESA Display Port interface specification. +DP Controller: Required properties:

+- compatible:           Should be "qcom,dp-display".
+- reg:                  Base address and length of DP hardware's 
memory mapped regions.
+- cell-index:           Specifies the controller instance.
+- reg-names:            A list of strings that name the list of regs.

Documentation/devicetree/bindings/display/msm/dp.txt new file +6 -0

+                       "dp_ahb" - DP controller memory region.
+                       "dp_aux" - DP AUX memory region.
+                       "dp_link" - DP link layer memory region.
+                       "dp_p0" - DP pixel clock domain memory region.
+                       "dp_phy" - DP PHY memory region.
+                       "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane 

memory region.
+ "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane
memory region.
+ "dp_mmss_cc" - Display Clock Control memory
region.

Documentation/devicetree/bindings/display/msm/dp.txt new file +3 -0

+                       "qfprom_physical" - QFPROM Phys memory region.
+                       "dp_pll" - USB3 DP combo PLL memory region.
+                       "usb3_dp_com" - USB3 DP PHY combo memory 

Quoted 2 lines

region.
+ "hdcp_physical" - DP HDCP memory region.

A handful of these register properties overlap with the USB PHY region.

I suspect the existing qcom,sc7180-qmp-usb3-phy USB PHY binding that we have is wrong. It should describe both the USB part and the DP part of the combo PHY. Probably the DP part can be a subnode like how the superspeed PHY is a child node of the wrapper node. Then we'll have to figure out how to coordinate the access to usb3_dp_com (which I presume corresponds to the dp_com region in the usb3-phy binding) so that the USB and DP PHY drivers can figure out how to configure the "type-c" pins on the SoC to be 2 lanes DP and 2 lanes USB or 4 lanes USB or 4 lanes DP.

Quoted 4 lines

+- interrupt-parent     phandle to the interrupt parent device node.
+- interrupts:          The interrupt signal from the DP block.
+- clocks:               Clocks required for Display Port operation. 

Quoted 9 lines

See [1] for details on clock bindings.
+- clock-names: Names of the clocks corresponding to handles.
Following clocks are required:
+ "core_aux_clk",
"core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+ "core_usb_pipe_clk", "ctrl_link_clk",
"ctrl_link_iface_clk", "ctrl_crypto_clk",
+ "ctrl_pixel_clk", "pixel_clk_rcg",
"pixel_parent".

Please remove _clk suffix on all clock names. It's redundant.

Quoted 65 lines

+- pll-node:            phandle to DP PLL node.
+- vdda-1p2-supply:             phandle to vdda 1.2V regulator node.
+- vdda-0p9-supply:             phandle to vdda 0.9V regulator node.
+- qcom,aux-cfg0-settings:              Specifies the DP AUX 

configuration 0 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg1-settings: Specifies the DP AUX
configuration 1 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg2-settings: Specifies the DP AUX
configuration 2 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg3-settings: Specifies the DP AUX
configuration 3 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg4-settings: Specifies the DP AUX
configuration 4 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg5-settings: Specifies the DP AUX
configuration 5 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg6-settings: Specifies the DP AUX
configuration 6 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg7-settings: Specifies the DP AUX
configuration 7 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg8-settings: Specifies the DP AUX
configuration 8 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the

Quoted 8 lines

+ programmable values.
+- qcom,aux-cfg9-settings: Specifies the DP AUX
configuration 9 settings. The first
+ entry in this array
corresponds to the register offset
+ within DP AUX, while the
remaining entries indicate the
+ programmable values.

It would be better if these properties were understandable by us mere kernel developers out there. Is it possible to make them into standalone properties that control certain configuration tunings? Are any of these not variable per-board and can be hardcoded based on the SoC into the driver?

Quoted 2 lines

+- qcom,max-pclk-frequency-khz: An integer specifying the
maximum. pixel clock in KHz supported by Display Port.

This can't be detected at runtime?

Quoted 3 lines

+- qcom,max-lanes-for-dp: Maximum number of lanes that
can be used for Display port.

This can come from an of graph walk to figure out how many possible lanes are connected? Or some more standard property that describes logical to physical lane mapping, like data-lanes?

Quoted 20 lines

+- qcom,<type>-supply-entries: A node that lists the elements
of the supply used by the a particular "type" of DP module. The module "types"
+ can be "core", "ctrl", and
"phy". Within the same type,
+ there can be more than one
instance of this binding,
+ in which case the entry would
be appended with the

Documentation/devicetree/bindings/display/msm/dp.txt new file +3 -0

+                                       supply entry index.
+                                       e.g. qcom,ctrl-supply-entry@0
+                                       -- qcom,supply-name: name of 

the supply (vdd/vdda/vddio)
+ -- qcom,supply-min-voltage:
minimum voltage level (uV)
+ -- qcom,supply-max-voltage:
maximum voltage level (uV)
+ -- qcom,supply-enable-load:
load drawn (uA) from enabled supply
+ -- qcom,supply-disable-load:
load drawn (uA) from disabled supply

Quoted 8 lines

+ -- qcom,supply-pre-on-sleep:
time to sleep (ms) before turning on
+ -- qcom,supply-post-on-sleep:
time to sleep (ms) after turning on
+ -- qcom,supply-pre-off-sleep:
time to sleep (ms) before turning off
+ -- qcom,supply-post-off-sleep:
time to sleep (ms) after turning off

All these regulator properties look like things that should be handled by board constraints on certain supplies, not by this binding or the driver that matches this binding.

Quoted 9 lines

+- pinctrl-names: List of names to assign mdss pin states
defined in pinctrl device node
+ Refer to pinctrl-bindings.txt
+- pinctrl-<0..n>: Lists phandles each pointing to the pin
configuration node within a pin
+ controller. These pin
configurations are installed in the pinctrl
+ device node. Refer to
pinctrl-bindings.txt

These two properties aren't needed.

Quoted 11 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +2 -0

+DP Endpoint properties:
+  - remote-endpoint: For port@0, set to phandle of the connected 

panel/bridge's
+ input endpoint. For port@1, set to the DPU interface output. See
[2] for

Documentation/devicetree/bindings/display/msm/dp.txt new file +5 -0

+    device graph info.
+
+Optional properties:
+- qcom,aux-en-gpio:            Specifies the aux-channel enable gpio.
+- qcom,aux-sel-gpio:           Specifies the mux-selection that might 

be needed for aux interface.

Please use the normal '<your name here>-gpios' property for gpios.

Quoted 9 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +5 -0

+
+
+DP PLL: Required properties:
+- compatible:           Should be "qcom,dp-pll-10nm".
+- reg:                  Base address and length of DP hardware's 

memory mapped regions.

+- cell-index:           Specifies the PLL instance.
+- reg-names:            A list of strings that name the list of regs.
+                       "pll_base" - DP PLL memory region.

Quoted 5 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +2 -0

+                       "phy_base" - DP PHY memory region.
+                       "ln_tx0_base" - USB3 DP PHY combo TX-0 lane 

memory region.
+ "ln_tx1_base" - USB3 DP PHY combo TX-1 lane
memory region.

This was in the other node binding. Probably the only reg property required here is pll_base?

Quoted 4 lines

+                       "gdsc_base" - gdsc memory region.
+- interrupt-parent     phandle to the interrupt parent device node.
+- interrupts:          The interrupt signal from the DP block.

Quoted 8 lines

+- clocks: Clocks required for Display Port operation.
See [1] for details on clock bindings.
+- clock-names: Names of the clocks corresponding to handles.
Following clocks are required:
+ "iface_clk", "ref_clk", cfg_ahb_clk",
"pipe_clk".

+- clock-rate:           Initial clock rate to be configured. For the 
shared clocks, the default value                       is set to zero so that minimum clock value is configured. Non-zero clock

We have assigned-clock-rates for this.

Documentation/devicetree/bindings/display/msm/dp.txt line 125

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +8 -0

+                       value can be used to configure DP pixel clock.
+
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/graph.txt
+
+Example:
+       msm_dp: dp_display@ae90000{

No underscores in node names. It should also be somewhat generic like 'display-controller' or 'displayport-controller' and the first reg property should match the unit address after the at sign (@).

Quoted 14 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +14 -0

+               cell-index = <0>;
+               compatible = "qcom,dp-display";
+
+               reg =   <0 0x90000 0x0dc>,
+                       <0 0x90200 0x0c0>,
+                       <0 0x90400 0x508>,
+                       <0 0x90a00 0x094>,
+                       <1 0xeaa00 0x200>,
+                       <1 0xea200 0x200>,
+                       <1 0xea600 0x200>,
+                       <2 0x02000 0x1a0>,
+                       <3 0x00000 0x621c>,
+                       <1 0xea000 0x180>,
+                       <1 0xe8000 0x20>,

Documentation/devicetree/bindings/display/msm/dp.txt line 149

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +10 -0

+                       <4 0xe1000 0x034>;
+               reg-names = "dp_ahb", "dp_aux", "dp_link",
+                       "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+                       "dp_mmss_cc", "qfprom_physical", "dp_pll",
+                       "usb3_dp_com", "hdcp_physical";
+
+               interrupt-parent = <&display_subsystem>;
+               interrupts = <12 0>;
+
+               extcon = <&usb_1_ssphy>;

Please no extcon

Quoted 93 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +69 -0

+               clocks =  <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+                       <&rpmhcc RPMH_CXO_CLK>,
+                       <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+                       <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                       <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
+                       <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+               clock-names = "core_aux_clk", "core_ref_clk_src",
+                       "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+                       "core_usb_pipe_clk", "ctrl_link_clk",
+                       "ctrl_link_iface_clk", "ctrl_pixel_clk",
+                       "crypto_clk", "pixel_clk_rcg";
+
+               pll-node = <&dp_pll>;
+               vdda-1p2-supply = <&vreg_l3c_1p2>;
+               vdda-0p9-supply = <&vreg_l4a_0p8>;
+               qcom,aux-cfg0-settings = [20 00];
+               qcom,aux-cfg1-settings = [24 13 23 1d];
+               qcom,aux-cfg2-settings = [28 24];
+               qcom,aux-cfg3-settings = [2c 00];
+               qcom,aux-cfg4-settings = [30 0a];
+               qcom,aux-cfg5-settings = [34 26];
+               qcom,aux-cfg6-settings = [38 0a];
+               qcom,aux-cfg7-settings = [3c 03];
+               qcom,aux-cfg8-settings = [40 bb];
+               qcom,aux-cfg9-settings = [44 03];
+
+               qcom,max-pclk-frequency-khz = <675000>;
+               qcom,max-lanes-for-dp = <2>;
+
+               qcom,ctrl-supply-entries {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       qcom,ctrl-supply-entry@0 {
+                               reg = <0>;
+                               qcom,supply-name = "vdda-1p2";
+                               qcom,supply-min-voltage = <1200000>;
+                               qcom,supply-max-voltage = <1200000>;
+                               qcom,supply-enable-load = <21800>;
+                               qcom,supply-disable-load = <4>;
+                       };
+               };
+
+               qcom,phy-supply-entries {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       qcom,phy-supply-entry@0 {
+                               reg = <0>;
+                               qcom,supply-name = "vdda-0p9";
+                               qcom,supply-min-voltage = <880000>;
+                               qcom,supply-max-voltage = <880000>;
+                               qcom,supply-enable-load = <36000>;
+                               qcom,supply-disable-load = <32>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               dp_in: endpoint {
+                                       remote-endpoint = 

<&dpu_intf0_out>;

Documentation/devicetree/bindings/display/msm/dp.txt new file +23 -0

+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               dp_out: endpoint {
+                               };
+                       };
+               };
+       };
+
+       dp_pll: dp-pll@c011000 {
+               compatible = "qcom,dp-pll-10nm";
+               label = "DP PLL";
+               cell-index = <0>;
+               #clock-cells = <1>;
+
+               reg = <1 0xea000 0x200>,
+                     <1 0xeaa00 0x200>,
+                     <1 0xea200 0x200>,
+                     <1 0xea600 0x200>,
+                     <2 0x03000 0x8>;
+               reg-names = "pll_base", "phy_base", "ln_tx0_base",

Documentation/devicetree/bindings/display/msm/dp.txt line 251

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +10 -0

+                       "ln_tx1_base", "gdsc_base";
+
+               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                        <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+                        <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                        <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+               clock-names = "iface_clk", "ref_clk",
+                       "cfg_ahb_clk", "pipe_clk";
+               clock-rate = <0>;
+

Remove this extra newline.

Quoted 9 lines

Documentation/devicetree/bindings/display/msm/dp.txt new file +1 -0

+       };

Documentation/devicetree/bindings/display/msm/dpu.txt +0 -0

index 551ae26..7e99e45 100644
@@ -63,8 +63,9 @@ Required properties:
        Documentation/devicetree/bindings/graph.txt
        Documentation/devicetree/bindings/media/video-interfaces.txt
 

Documentation/devicetree/bindings/display/msm/dpu.txt Required properties: · line 66

Quoted 3 lines

Documentation/devicetree/bindings/display/msm/dpu.txt +1 -2

-       Port 0 -> DPU_INTF1 (DSI1)
-       Port 1 -> DPU_INTF2 (DSI2)
+       Port 0 -> DPU_INTF0 (DP)

Why is port 0 changed to be DP? Can't we add DP to the end so that older DTs remain compatible?

Quoted 34 lines

Documentation/devicetree/bindings/display/msm/dpu.txt +2 -0

+       Port 1 -> DPU_INTF1 (DSI1)
+       Port 2 -> DPU_INTF2 (DSI2)
 
 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate 

assignment

Documentation/devicetree/bindings/display/msm/dpu.txt +9 -2

@@ -125,13 +126,20 @@ Example:
 
                                port@0 {
                                        reg = <0>;
-                                       dpu_intf1_out: endpoint {
-                                               remote-endpoint = 
 <&dsi0_in>;
+                                       dpu_intf0_out: endpoint {
+                                               remote-endpoint = 
 <&dp_in>;
                                        };
                                };
 
                                port@1 {
                                        reg = <1>;
+                                       dpu_intf1_out: endpoint {
+                                               remote-endpoint = 
 <&dsi0_in>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;

                                        dpu_intf2_out: endpoint {
                                                remote-endpoint = 
<&dsi1_in>;
                                        };

Quoted 2 lines

--
$(echo -e 'The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,

You should fix your signature :)

From: Chandan Uddaraju <[email protected]>

Add the needed displayPort files to enable DP driver on msm target.

"dp_display" module is the main module that calls into other sub-modules. "dp_drm" file represents the interface between DRM framework and DP driver.

changes in v2:
-- Update copyright markings on all relevant files.
-- Change pr_err() to DRM_ERROR()
-- Use APIs directly instead of function pointers.
-- Use drm_display_mode structure to store link parameters. -- Use macros for register definitions instead of hardcoded values. -- Replace writel_relaxed/readl_relaxed with writel/readl
and remove memory barriers.
-- Remove unnecessary NULL checks.
-- Use drm helper functions for dpcd read/write.
-- Use DRM_DEBUG_DP for debug msgs.

changes in V3:
-- Removed changes in dpu_io_util.[ch]
-- Added locking around "is_connected" flag and removed atomic_set() -- Removed the argument validation checks in all the static functions
except initialization functions and few API across msm/dp files.
-- Removed hardcoded values for register reads/writes
-- Removed vreg related generic structures.
-- Added return values where ever necessary.
-- Updated dp_ctrl_on function.
-- Calling the ctrl specific catalog functions directly instead of
function pointers.
-- Added separate change that adds standard value in drm_dp_helper file. -- Added separate change in this list that is used to initialize DP. -- Added change to use drm_dp_get_adjust_request_voltage() function.

changes in V4:
-- Fix mvid, nvid calculation.
-- Shift video timings to align to bottom right. -- Fix register offsets for pixel_m and pixel_n. -- Fix TPG programming sequence.
-- Update DP ack override register to recommended value. -- Added code to log displayport registers.
-- Update aux setup with recommended settings. -- Fix TU calculations for all resolutions.
-- Limit linkrate to HBR2 until HBR3 support is added. -- Update DPCD read sequence.
-- Update code comments in dp_power_init() of V3. -- Remove extcon dependencies.
-- Move drm helper functions locally.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

---
 drivers/gpu/drm/msm/Kconfig                        |    9 +
 drivers/gpu/drm/msm/Makefile                       |   13 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |   20 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |    8 +
 drivers/gpu/drm/msm/dp/dp_aux.c                    |  549 +++++++
 drivers/gpu/drm/msm/dp/dp_aux.h                    |   37 +
 drivers/gpu/drm/msm/dp/dp_catalog.c                | 1118 +++++++++++++
 drivers/gpu/drm/msm/dp/dp_catalog.h                |   87 +
 drivers/gpu/drm/msm/dp/dp_ctrl.c                   | 1727 ++++++++++++++++++++
 drivers/gpu/drm/msm/dp/dp_ctrl.h                   |   35 +
 drivers/gpu/drm/msm/dp/dp_display.c                |  974 +++++++++++
 drivers/gpu/drm/msm/dp/dp_display.h                |   28 +
 drivers/gpu/drm/msm/dp/dp_drm.c                    |  176 ++
 drivers/gpu/drm/msm/dp/dp_drm.h                    |   19 +
 drivers/gpu/drm/msm/dp/dp_hpd.c                    |   87 +
 drivers/gpu/drm/msm/dp/dp_hpd.h                    |   81 +
 drivers/gpu/drm/msm/dp/dp_link.c                   | 1246 ++++++++++++++
 drivers/gpu/drm/msm/dp/dp_link.h                   |  140 ++
 drivers/gpu/drm/msm/dp/dp_panel.c                  |  500 ++++++
 drivers/gpu/drm/msm/dp/dp_panel.h                  |   95 ++
 drivers/gpu/drm/msm/dp/dp_parser.c                 |  507 ++++++
 drivers/gpu/drm/msm/dp/dp_parser.h                 |  224 +++
 drivers/gpu/drm/msm/dp/dp_power.c                  |  563 +++++++
 drivers/gpu/drm/msm/dp/dp_power.h                  |   52 +
 drivers/gpu/drm/msm/dp/dp_reg.h                    |  489 ++++++
 drivers/gpu/drm/msm/msm_drv.c                      |    2 +
 drivers/gpu/drm/msm/msm_drv.h                      |   53 +-
 27 files changed, 8836 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_display.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_display.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_link.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_link.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_power.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_power.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_reg.h

drivers/gpu/drm/msm/Kconfig +0 -0

index 6deaa7d..7946cb1 100644

drivers/gpu/drm/msm/Kconfig +5 -0

+	help
+	  Compile in support for DP driver in msm drm driver. DP external
+	  display support is enabled through this config option. It can
+	  be primary or secondary display on device.
+
 config DRM_MSM_DSI
 	bool "Enable DSI support in MSM DRM driver"
 	depends on DRM_MSM

drivers/gpu/drm/msm/Makefile +1 -0

index 1579cf0..c846599 100644
@@ -2,6 +2,7 @@
 ccflags-y := -I $(srctree)/$(src)
 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
+ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
 
 msm-y := \
 	adreno/adreno_device.o \

drivers/gpu/drm/msm/Makefile +11 -0

 msm-$(CONFIG_DRM_MSM_GPU_STATE)	+= adreno/a6xx_gpu_state.o
 
+msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
+	dp/dp_catalog.o \
+	dp/dp_ctrl.o \
+	dp/dp_display.o \
+	dp/dp_drm.o \
+	dp/dp_hpd.o \
+	dp/dp_link.o \
+	dp/dp_panel.o \
+	dp/dp_parser.o \
+	dp/dp_power.o
+
 msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
 msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
 msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +20 -0

index f8ac3bf..b063243 100644
@@ -978,6 +978,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 
 	trace_dpu_enc_mode_set(DRMID(drm_enc));
 
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp)
+		msm_dp_display_mode_set(priv->dp, drm_enc, mode, adj_mode);
+
 	list_for_each_entry(conn_iter, connector_list, head)
 		if (conn_iter->encoder == drm_enc)
 			conn = conn_iter;

@@ -1141,6 +1144,7 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 {
 	struct dpu_encoder_virt *dpu_enc = NULL;
 	int ret = 0;
+	struct msm_drm_private *priv;
 	struct drm_display_mode *cur_mode = NULL;
 
 	if (!drm_enc) {

@@ -1151,6 +1155,7 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 
 	mutex_lock(&dpu_enc->enc_lock);
 	cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
+	priv = drm_enc->dev->dev_private;
 
 	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
 			     cur_mode->vdisplay);

@@ -1171,6 +1176,15 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 
 	_dpu_encoder_virt_enable_helper(drm_enc);
 
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
+		ret = msm_dp_display_enable(priv->dp,
+						drm_enc);
+		if (ret) {
+			DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
+				ret);
+			goto out;
+		}
+	}
 	dpu_enc->enabled = true;
 
 out:

@@ -1201,6 +1215,12 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
 	priv = drm_enc->dev->dev_private;
 	dpu_kms = to_dpu_kms(priv->kms);
 
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
+		if (msm_dp_display_disable(priv->dp, drm_enc)) {
+			DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
+			return;
+		}
+	}
 	trace_dpu_enc_disable(DRMID(drm_enc));
 
 	/* wait for idle */

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +8 -0

index c71c18d..c1dfcc4 100644
@@ -100,6 +100,14 @@ static void drm_mode_to_intf_timing_params(
 	 * display_v_end -= mode->hsync_start - mode->hdisplay;
 	 * }
 	 */
+	/* for DP/EDP, Shift timings to align it to bottom right */
+	if ((phys_enc->hw_intf->cap->type == INTF_DP) ||
+		(phys_enc->hw_intf->cap->type == INTF_EDP)) {
+		timing->h_back_porch += timing->h_front_porch;
+		timing->h_front_porch = 0;
+		timing->v_back_porch += timing->v_front_porch;
+		timing->v_front_porch = 0;
+	}
 }
 
 static u32 get_horizontal_total(const struct intf_timing_params *timing)

drivers/gpu/drm/msm/dp/dp_aux.c new file +0 -0

new file mode 100644
index 0000000..e033a90

drivers/gpu/drm/msm/dp/dp_aux.c new file +21 -0

+
+#include <linux/delay.h>
+
+#include "dp_reg.h"
+#include "dp_aux.h"
+
+#define DP_AUX_ENUM_STR(x)		#x
+
+struct dp_aux_private {
+	struct device *dev;
+	struct dp_aux dp_aux;
+	struct dp_catalog *catalog;
+
+	struct mutex mutex;
+	struct completion comp;
+
+	u32 aux_error_num;
+	u32 retry_cnt;
+	bool cmd_busy;
+	bool native;
+	bool read;

drivers/gpu/drm/msm/dp/dp_aux.c new file +11 -0

+	case DP_AUX_ERR_ADDR:
+		return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
+	case DP_AUX_ERR_TOUT:
+		return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
+	case DP_AUX_ERR_NACK:
+		return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
+	case DP_AUX_ERR_DEFER:
+		return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
+	case DP_AUX_ERR_NACK_DEFER:
+		return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
+	default:

drivers/gpu/drm/msm/dp/dp_aux.c new file +37 -0

+		return 0;
+	}
+
+	/* Pack cmd and write to HW */
+	data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
+	if (aux->read)
+		data[0] |=  BIT(4); /* R/W */
+
+	data[1] = (msg->address >> 8) & 0xff;	/* addr[15:8] */
+	data[2] = msg->address & 0xff;		/* addr[7:0] */
+	data[3] = (msg->size - 1) & 0xff;	/* len[7:0] */
+
+	for (i = 0; i < len; i++) {
+		reg = (i < 4) ? data[i] : msgdata[i - 4];
+		/* index = 0, write */
+		reg = (((reg) << DP_AUX_DATA_OFFSET)
+		       & DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE;
+		if (i == 0)
+			reg |= DP_AUX_DATA_INDEX_WRITE;
+		aux->catalog->aux_data = reg;
+		dp_catalog_aux_write_data(aux->catalog);
+	}
+
+	dp_catalog_aux_clear_trans(aux->catalog, false);
+
+	reg = 0; /* Transaction number == 1 */
+	if (!aux->native) { /* i2c */
+		reg |= DP_AUX_TRANS_CTRL_I2C;
+
+		if (aux->no_send_addr)
+			reg |= DP_AUX_TRANS_CTRL_NO_SEND_ADDR;
+
+		if (aux->no_send_stop)
+			reg |= DP_AUX_TRANS_CTRL_NO_SEND_STOP;
+	}
+
+	reg |= DP_AUX_TRANS_CTRL_GO;

drivers/gpu/drm/msm/dp/dp_aux.c new file +29 -0

+
 
+	reinit_completion(&aux->comp);
+
+	len = dp_aux_write(aux, msg);
+	if (len == 0) {
+		DRM_ERROR("DP AUX write failed\n");
+		return -EINVAL;
+	}
+
+	timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
+	if (!timeout) {
+		DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write"));
+		return -ETIMEDOUT;
+	}
+
+	if (aux->aux_error_num == DP_AUX_ERR_NONE) {
+		ret = len;
+	} else {
+		DRM_ERROR_RATELIMITED("aux err: %s\n",
+			dp_aux_get_error(aux->aux_error_num));
+
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
+		struct drm_dp_aux_msg *msg)

drivers/gpu/drm/msm/dp/dp_aux.c new file +7 -0

+	data |= DP_AUX_DATA_READ;  /* read */
+
+	aux->catalog->aux_data = data;
+	dp_catalog_aux_write_data(aux->catalog);
+
+	dp = msg->buffer;
+

drivers/gpu/drm/msm/dp/dp_aux.c new file +40 -0

+				i, actual_i);
+	}
+}
+
+static void dp_aux_native_handler(struct dp_aux_private *aux)
+{
+	u32 isr = aux->isr;
+
+	if (isr & DP_INTR_AUX_I2C_DONE)
+		aux->aux_error_num = DP_AUX_ERR_NONE;
+	else if (isr & DP_INTR_WRONG_ADDR)
+		aux->aux_error_num = DP_AUX_ERR_ADDR;
+	else if (isr & DP_INTR_TIMEOUT)
+		aux->aux_error_num = DP_AUX_ERR_TOUT;
+	if (isr & DP_INTR_NACK_DEFER)
+		aux->aux_error_num = DP_AUX_ERR_NACK;
+
+	complete(&aux->comp);
+}
+
+static void dp_aux_i2c_handler(struct dp_aux_private *aux)
+{
+	u32 isr = aux->isr;
+
+	if (isr & DP_INTR_AUX_I2C_DONE) {
+		if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
+			aux->aux_error_num = DP_AUX_ERR_NACK;
+		else
+			aux->aux_error_num = DP_AUX_ERR_NONE;
+	} else {
+		if (isr & DP_INTR_WRONG_ADDR)
+			aux->aux_error_num = DP_AUX_ERR_ADDR;
+		else if (isr & DP_INTR_TIMEOUT)
+			aux->aux_error_num = DP_AUX_ERR_TOUT;
+		if (isr & DP_INTR_NACK_DEFER)
+			aux->aux_error_num = DP_AUX_ERR_NACK_DEFER;
+		if (isr & DP_INTR_I2C_NACK)
+			aux->aux_error_num = DP_AUX_ERR_NACK;
+		if (isr & DP_INTR_I2C_DEFER)
+			aux->aux_error_num = DP_AUX_ERR_DEFER;

drivers/gpu/drm/msm/dp/dp_aux.c new file +14 -0

+
+	if (aux->native || i2c_read || ((input_msg->address != edid_address) &&
+		(input_msg->address != segment_address)))
+		return;
+
+
+	data = input_msg->buffer;
+	if (input_msg->address == segment_address)
+		aux->segment = *data;
+	else
+		aux->offset = *data;
+}
+
+/**

drivers/gpu/drm/msm/dp/dp_aux.c new file +65 -0

+	bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT;
+	bool i2c_read = input_msg->request &
+		(DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
+
+	if (!i2c_mot || !i2c_read || (input_msg->size == 0))
+		return;
+
+	aux->read = false;
+	aux->cmd_busy = true;
+	aux->no_send_addr = true;
+	aux->no_send_stop = true;
+
+	/*
+	 * Send the segment address for every i2c read in which the
+	 * middle-of-tranaction flag is set. This is required to support EDID
+	 * reads of more than 2 blocks as the segment address is reset to 0
+	 * since we are overriding the middle-of-transaction flag for read
+	 * transactions.
+	 */
+	memset(&helper_msg, 0, sizeof(helper_msg));
+	helper_msg.address = segment_address;
+	helper_msg.buffer = &aux->segment;
+	helper_msg.size = 1;
+	dp_aux_cmd_fifo_tx(aux, &helper_msg);
+
+	/*
+	 * Send the offset address for every i2c read in which the
+	 * middle-of-transaction flag is set. This will ensure that the sink
+	 * will update its read pointer and return the correct portion of the
+	 * EDID buffer in the subsequent i2c read trasntion triggered in the
+	 * native AUX transfer function.
+	 */
+	memset(&helper_msg, 0, sizeof(helper_msg));
+	helper_msg.address = input_msg->address;
+	helper_msg.buffer = &aux->offset;
+	helper_msg.size = 1;
+	dp_aux_cmd_fifo_tx(aux, &helper_msg);
+	aux->offset += message_size;
+
+	if (aux->offset == 0x80 || aux->offset == 0x100)
+		aux->segment = 0x0; /* reset segment at end of block */
+}
+
+/*
+ * This function does the real job to process an AUX transaction.
+ * It will call aux_reset() function to reset the AUX channel,
+ * if the waiting is timeout.
+ */
+static ssize_t dp_aux_transfer(struct drm_dp_aux *drm_aux,
+			       struct drm_dp_aux_msg *msg)
+{
+	ssize_t ret;
+	int const aux_cmd_native_max = 16;
+	int const aux_cmd_i2c_max = 128;
+	int const retry_count = 5;
+	struct dp_aux_private *aux = container_of(drm_aux,
+		struct dp_aux_private, drm_aux);
+
+	mutex_lock(&aux->mutex);
+
+	aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
+
+	/* Ignore address only message */
+	if ((msg->size == 0) || (msg->buffer == NULL)) {
+		msg->reply = aux->native ?

drivers/gpu/drm/msm/dp/dp_aux.c new file +19 -0

+		ret = -EINVAL;
+		goto unlock_exit;
+	}
+
+	dp_aux_update_offset_and_segment(aux, msg);
+	dp_aux_transfer_helper(aux, msg);
+
+	aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
+	aux->cmd_busy = true;
+
+	if (aux->read) {
+		aux->no_send_addr = true;
+		aux->no_send_stop = false;
+	} else {
+		aux->no_send_addr = true;
+		aux->no_send_stop = true;
+	}
+
+	ret = dp_aux_cmd_fifo_tx(aux, msg);

drivers/gpu/drm/msm/dp/dp_aux.c new file +16 -0

+
+	if (aux->aux_error_num == DP_AUX_ERR_NONE) {
+		if (aux->read)
+			dp_aux_cmd_fifo_rx(aux, msg);
+
+		msg->reply = aux->native ?
+			DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
+	} else {
+		/* Reply defer to retry */
+		msg->reply = aux->native ?
+			DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
+	}
+
+	/* Return requested size for success or retry */
+	ret = msg->size;
+	aux->retry_cnt = 0;

drivers/gpu/drm/msm/dp/dp_aux.c new file +52 -0

+
+	for (i = 0; i < PHY_AUX_CFG_MAX; i++)
+		aux_cfg[i].current_index = 0;
+}
+
+void dp_aux_isr(struct dp_aux *dp_aux)
+{
+	struct dp_aux_private *aux;
+
+	if (!dp_aux) {
+		DRM_ERROR("invalid input\n");
+		return;
+	}
+
+	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
+
+	aux->isr = dp_catalog_aux_get_irq(aux->catalog);
+
+	if (!aux->cmd_busy)
+		return;
+
+	if (aux->native)
+		dp_aux_native_handler(aux);
+	else
+		dp_aux_i2c_handler(aux);
+}
+
+void dp_aux_reconfig(struct dp_aux *dp_aux)
+{
+	struct dp_aux_private *aux;
+
+	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
+
+	dp_catalog_aux_update_cfg(aux->catalog,
+			dp_aux->cfg, PHY_AUX_CFG1);
+	dp_catalog_aux_reset(aux->catalog);
+}
+
+void dp_aux_init(struct dp_aux *dp_aux, struct dp_aux_cfg *aux_cfg)
+{
+	struct dp_aux_private *aux;
+
+	if (!dp_aux || !aux_cfg) {
+		DRM_ERROR("invalid input\n");
+		return;
+	}
+
+	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
+
+	dp_aux_reset_phy_config_indices(aux_cfg);
+	dp_catalog_aux_setup(aux->catalog, aux_cfg);
+	dp_catalog_aux_reset(aux->catalog);

drivers/gpu/drm/msm/dp/dp_aux.c new file +6 -0

+		return;
+	}
+
+	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
+	drm_dp_aux_unregister(&aux->drm_aux);
+}

drivers/gpu/drm/msm/dp/dp_aux.c new file +7 -0

+		rc = -ENOMEM;
+		goto error;
+	}
+
+	init_completion(&aux->comp);
+	aux->cmd_busy = false;
+	mutex_init(&aux->mutex);

drivers/gpu/drm/msm/dp/dp_aux.c new file +4 -0

+}
+
+void dp_aux_put(struct dp_aux *dp_aux)
+{

drivers/gpu/drm/msm/dp/dp_aux.c new file +1 -0

+}

drivers/gpu/drm/msm/dp/dp_aux.h new file +9 -0

new file mode 100644
index 0000000..ca22b5c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DP_AUX_H_
+#define _DP_AUX_H_
+
+#include "dp_catalog.h"

drivers/gpu/drm/msm/dp/dp_aux.h new file +7 -0

+struct dp_aux {
+	struct drm_dp_aux *drm_aux;
+	struct dp_aux_cfg *cfg;
+};
+
+int dp_aux_register(struct dp_aux *aux);
+void dp_aux_unregister(struct dp_aux *aux);

drivers/gpu/drm/msm/dp/dp_aux.h new file +2 -0

+
+#endif /*__DP_AUX_H_*/

drivers/gpu/drm/msm/dp/dp_catalog.c new file +84 -0

new file mode 100644
index 0000000..bd1debd
@@ -0,0 +1,1118 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#define pr_fmt(fmt)	"[drm-dp] %s: " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <drm/drm_dp_helper.h>
+
+#include "dp_catalog.h"
+#include "dp_reg.h"
+
+#define POLLING_SLEEP_US			1000
+#define POLLING_TIMEOUT_US			10000
+
+#define REFTIMER_DEFAULT_VALUE			0x20000
+#define SCRAMBLER_RESET_COUNT_VALUE		0xFC
+
+#define DP_INTERRUPT_STATUS_ACK_SHIFT	1
+#define DP_INTERRUPT_STATUS_MASK_SHIFT	2
+
+#define DP_INTERRUPT_STATUS1 \
+	(DP_INTR_AUX_I2C_DONE| \
+	DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
+	DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
+	DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
+	DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
+
+#define DP_INTERRUPT_STATUS1_ACK \
+	(DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT)
+#define DP_INTERRUPT_STATUS1_MASK \
+	(DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT)
+
+#define DP_INTERRUPT_STATUS2 \
+	(DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
+	DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
+
+#define DP_INTERRUPT_STATUS2_ACK \
+	(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT)
+#define DP_INTERRUPT_STATUS2_MASK \
+	(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
+
+static u8 const vm_pre_emphasis[4][4] = {
+	{0x00, 0x0B, 0x12, 0xFF},       /* pe0, 0 db */
+	{0x00, 0x0A, 0x12, 0xFF},       /* pe1, 3.5 db */
+	{0x00, 0x0C, 0xFF, 0xFF},       /* pe2, 6.0 db */
+	{0xFF, 0xFF, 0xFF, 0xFF}        /* pe3, 9.5 db */
+};
+
+/* voltage swing, 0.2v and 1.0v are not support */
+static u8 const vm_voltage_swing[4][4] = {
+	{0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v  */
+	{0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
+	{0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
+	{0xFF, 0xFF, 0xFF, 0xFF}  /* sw1, 1.2 v, optional */
+};
+
+static u8 const vm_pre_emphasis_hbr3_hbr2[4][4] = {
+	{0x00, 0x0C, 0x15, 0x1A},
+	{0x02, 0x0E, 0x16, 0xFF},
+	{0x02, 0x11, 0xFF, 0xFF},
+	{0x04, 0xFF, 0xFF, 0xFF}
+};
+
+static u8 const vm_voltage_swing_hbr3_hbr2[4][4] = {
+	{0x02, 0x12, 0x16, 0x1A},
+	{0x09, 0x19, 0x1F, 0xFF},
+	{0x10, 0x1F, 0xFF, 0xFF},
+	{0x1F, 0xFF, 0xFF, 0xFF}
+};
+
+static u8 const vm_pre_emphasis_hbr_rbr[4][4] = {
+	{0x00, 0x0C, 0x14, 0x19},
+	{0x00, 0x0B, 0x12, 0xFF},
+	{0x00, 0x0B, 0xFF, 0xFF},
+	{0x04, 0xFF, 0xFF, 0xFF}
+};
+
+static u8 const vm_voltage_swing_hbr_rbr[4][4] = {
+	{0x08, 0x0F, 0x16, 0x1F},
+	{0x11, 0x1E, 0x1F, 0xFF},
+	{0x19, 0x1F, 0xFF, 0xFF},

drivers/gpu/drm/msm/dp/dp_catalog.c new file +128 -0

+{
+	return readl_relaxed(catalog->io->dp_aux.base + offset);
+}
+
+static inline void dp_write_aux(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	/*
+	 * To make sure aux reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	writel(data, catalog->io->dp_aux.base + offset);
+}
+
+static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset)
+{
+	return readl_relaxed(catalog->io->dp_ahb.base + offset);
+}
+
+static inline void dp_write_ahb(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	/*
+	 * To make sure phy reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	writel(data, catalog->io->dp_ahb.base + offset);
+}
+
+static inline u32 dp_read_cc(struct dp_catalog_private *catalog, u32 offset)
+{
+	return readl_relaxed(catalog->io->dp_cc_io.base + offset);
+}
+
+static inline void dp_write_phy(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	/*
+	 * To make sure phy reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	writel(data, catalog->io->phy_io.base + offset);
+}
+
+static inline u32 dp_read_phy(struct dp_catalog_private *catalog,
+			       u32 offset)
+{
+	/*
+	 * To make sure phy reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	return readl_relaxed(catalog->io->phy_io.base + offset);
+}
+
+static inline void dp_write_pll(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	writel_relaxed(data, catalog->io->dp_pll_io.base + offset);
+}
+
+static inline void dp_write_ln_tx0(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	writel_relaxed(data, catalog->io->ln_tx0_io.base + offset);
+}
+
+static inline void dp_write_ln_tx1(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	writel_relaxed(data, catalog->io->ln_tx1_io.base + offset);
+}
+
+static inline u32 dp_read_ln_tx0(struct dp_catalog_private *catalog,
+			       u32 offset)
+{
+	return readl_relaxed(catalog->io->ln_tx0_io.base + offset);
+}
+
+static inline u32 dp_read_ln_tx1(struct dp_catalog_private *catalog,
+			       u32 offset)
+{
+	return readl_relaxed(catalog->io->ln_tx1_io.base + offset);
+}
+
+static inline void dp_write_usb_cm(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	/*
+	 * To make sure usb reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	writel(data, catalog->io->usb3_dp_com.base + offset);
+}
+
+static inline u32 dp_read_usb_cm(struct dp_catalog_private *catalog,
+			       u32 offset)
+{
+	/*
+	 * To make sure usb reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	return readl_relaxed(catalog->io->usb3_dp_com.base + offset);
+}
+
+static inline void dp_write_p0(struct dp_catalog_private *catalog,
+			       u32 offset, u32 data)
+{
+	/*
+	 * To make sure interface reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	writel(data, catalog->io->dp_p0.base + offset);
+}
+
+static inline u32 dp_read_p0(struct dp_catalog_private *catalog,
+			       u32 offset)
+{
+	/*
+	 * To make sure interface reg writes happens before any other operation,
+	 * this function uses writel() instread of writel_relaxed()
+	 */
+	return readl_relaxed(catalog->io->dp_p0.base + offset);
+}
 
+static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset)
+{
+	return readl_relaxed(catalog->io->dp_link.base + offset);
+}
+

drivers/gpu/drm/msm/dp/dp_catalog.c new file +7 -0

+/* aux related catalog functions */
+u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	return dp_read_aux(catalog, REG_DP_AUX_DATA);

drivers/gpu/drm/msm/dp/dp_catalog.c new file +7 -0

+}
+
+int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read)
+{
+	int rc = 0;
+	u32 data = 0;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,

drivers/gpu/drm/msm/dp/dp_catalog.c new file +54 -0

+}
+
+void dp_catalog_aux_reset(struct dp_catalog *dp_catalog)
+{
+	u32 aux_ctrl;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	aux_ctrl = dp_read_aux(catalog, REG_DP_AUX_CTRL);
+
+	aux_ctrl |= DP_AUX_CTRL_RESET;
+	dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
+	usleep_range(1000, 1100); /* h/w recommended delay */
+
+	aux_ctrl &= ~DP_AUX_CTRL_RESET;
+	dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
+}
+
+void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable)
+{
+	u32 aux_ctrl;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	aux_ctrl = dp_read_aux(catalog, REG_DP_AUX_CTRL);
+
+	if (enable) {
+		dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff);
+		dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff);
+		aux_ctrl |= DP_AUX_CTRL_ENABLE;
+	} else {
+		aux_ctrl &= ~DP_AUX_CTRL_ENABLE;
+	}
+
+	dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
+}
+
+void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog,
+		struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 new_index = 0, current_index = 0;
+
+	if (type >= PHY_AUX_CFG_MAX) {
+		DRM_ERROR("invalid input\n");
+		return;
+	}
+
+	current_index = cfg[type].current_index;
+	new_index = (current_index + 1) % cfg[type].cfg_cnt;
+	DRM_DEBUG_DP("Updating %s from 0x%08x to 0x%08x\n",
+		dp_phy_aux_config_type_to_string(type),
+	cfg[type].lut[current_index], cfg[type].lut[new_index]);

drivers/gpu/drm/msm/dp/dp_catalog.c new file +8 -0

+	for (i = 0; i < len; i++) {
+		x0 = dp_read_ahb(catalog, addr_off + 0x0);
+		x4 = dp_read_ahb(catalog, addr_off + 0x4);
+		x8 = dp_read_ahb(catalog, addr_off + 0x8);
+		xc = dp_read_ahb(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+

drivers/gpu/drm/msm/dp/dp_catalog.c new file +11 -0

+
+	for (i = 0; i < len; i++) {
+		x0 = dp_read_aux(catalog, addr_off + 0x0);
+		x4 = dp_read_aux(catalog, addr_off + 0x4);
+		x8 = dp_read_aux(catalog, addr_off + 0x8);
+		xc = dp_read_aux(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+
+		addr_off += 16;
+	}

drivers/gpu/drm/msm/dp/dp_catalog.c new file +8 -0

+	for (i = 0; i < len; i++) {
+		x0 = dp_read_link(catalog, addr_off + 0x0);
+		x4 = dp_read_link(catalog, addr_off + 0x4);
+		x8 = dp_read_link(catalog, addr_off + 0x8);
+		xc = dp_read_link(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+

drivers/gpu/drm/msm/dp/dp_catalog.c new file +10 -0

+
+	for (i = 0; i < len; i++) {
+		x0 = dp_read_p0(catalog, addr_off + 0x0);
+		x4 = dp_read_p0(catalog, addr_off + 0x4);
+		x8 = dp_read_p0(catalog, addr_off + 0x8);
+		xc = dp_read_p0(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+
+		addr_off += 16;

drivers/gpu/drm/msm/dp/dp_catalog.c new file +8 -0

+	for (i = 0; i < len; i++) {
+		x0 = dp_read_usb_cm(catalog, addr_off + 0x0);
+		x4 = dp_read_usb_cm(catalog, addr_off + 0x4);
+		x8 = dp_read_usb_cm(catalog, addr_off + 0x8);
+		xc = dp_read_usb_cm(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+

drivers/gpu/drm/msm/dp/dp_catalog.c new file +10 -0

+
+	for (i = 0; i < len; i++) {
+		x0 = dp_read_ln_tx0(catalog, addr_off + 0x0);
+		x4 = dp_read_ln_tx0(catalog, addr_off + 0x4);
+		x8 = dp_read_ln_tx0(catalog, addr_off + 0x8);
+		xc = dp_read_ln_tx0(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+
+		addr_off += 16;

drivers/gpu/drm/msm/dp/dp_catalog.c new file +9 -0

+	for (i = 0; i < len; i++) {
+		x0 = dp_read_ln_tx1(catalog, addr_off + 0x0);
+		x4 = dp_read_ln_tx1(catalog, addr_off + 0x4);
+		x8 = dp_read_ln_tx1(catalog, addr_off + 0x8);
+		xc = dp_read_ln_tx1(catalog, addr_off + 0xc);
+		pr_info("%08x : %08x %08x %08x %08x\n", addr_off, x0, x4, x8,
+			xc);
+
+		addr_off += 16;

drivers/gpu/drm/msm/dp/dp_catalog.c new file +166 -0

+}
+
+void dp_catalog_aux_setup(struct dp_catalog *dp_catalog,
+		struct dp_aux_cfg *cfg)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	int i = 0;
+
+	dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN |
+		DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
+		DP_PHY_PD_CTL_DP_CLAMP_EN);
+
+	/* Turn on BIAS current for PHY/PLL */
+	dp_write_pll(catalog,
+		QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN |
+		QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_L_EN |
+		QSERDES_COM_EN_SYSCLK_TX_SEL);
+
+	dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PSR_PWRDN);
+
+	/* Make sure that hardware is done with  PSR power down */
+	wmb();
+	dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN |
+		DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN
+		| DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN
+		| DP_PHY_PD_CTL_DP_CLAMP_EN);
+
+	dp_write_pll(catalog,
+		QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN |
+		QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_R_EN |
+		QSERDES_COM_CLKBUF_L_EN | QSERDES_COM_EN_SYSCLK_TX_SEL |
+		QSERDES_COM_CLKBUF_RX_DRIVE_L);
+
+	/* DP AUX CFG register programming */
+	for (i = 0; i < PHY_AUX_CFG_MAX; i++) {
+		DRM_DEBUG_DP("%s: offset=0x%08x, value=0x%08x\n",
+			dp_phy_aux_config_type_to_string(i),
+			cfg[i].offset, cfg[i].lut[cfg[i].current_index]);
+		dp_write_phy(catalog, cfg[i].offset,
+			cfg[i].lut[cfg[i].current_index]);
+	}
+
+	dp_write_phy(catalog, REG_DP_PHY_AUX_INTERRUPT_MASK,
+			PHY_AUX_STOP_ERR_MASK |	PHY_AUX_DEC_ERR_MASK |
+			PHY_AUX_SYNC_ERR_MASK |	PHY_AUX_ALIGN_ERR_MASK |
+			PHY_AUX_REQ_ERR_MASK);
+}
+
+int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 intr, intr_ack;
+
+	intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS);
+	intr &= ~DP_INTERRUPT_STATUS1_MASK;
+	intr_ack = (intr & DP_INTERRUPT_STATUS1)
+			<< DP_INTERRUPT_STATUS_ACK_SHIFT;
+	dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack |
+			DP_INTERRUPT_STATUS1_MASK);
+
+	return intr;
+
+}
+
+/* controller related catalog functions */
+void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
+				u32 dp_tu, u32 valid_boundary,
+				u32 valid_boundary2)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary);
+	dp_write_link(catalog, REG_DP_TU, dp_tu);
+	dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2);
+}
+
+void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	dp_write_link(catalog, REG_DP_STATE_CTRL, state);
+}
+
+void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 cfg)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	DRM_DEBUG_DP("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
+
+	dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg);
+}
+
+void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 ln_0 = 0, ln_1 = 1, ln_2 = 2, ln_3 = 3; /* One-to-One mapping */
+	u32 ln_mapping;
+
+	ln_mapping = ln_0 << LANE0_MAPPING_SHIFT;
+	ln_mapping |= ln_1 << LANE1_MAPPING_SHIFT;
+	ln_mapping |= ln_2 << LANE2_MAPPING_SHIFT;
+	ln_mapping |= ln_3 << LANE3_MAPPING_SHIFT;
+
+	dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING,
+			ln_mapping);
+}
+
+void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
+						bool enable)
+{
+	u32 mainlink_ctrl;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	if (enable) {
+		/*
+		 * To make sure link reg writes happens before other operation,
+		 * dp_write_link() function uses writel()
+		 */
+		dp_write_link(catalog, REG_DP_MAINLINK_CTRL,
+				DP_MAINLINK_FB_BOUNDARY_SEL);
+		dp_write_link(catalog, REG_DP_MAINLINK_CTRL,
+					DP_MAINLINK_FB_BOUNDARY_SEL |
+					DP_MAINLINK_CTRL_RESET);
+		dp_write_link(catalog, REG_DP_MAINLINK_CTRL,
+					DP_MAINLINK_FB_BOUNDARY_SEL);
+		dp_write_link(catalog, REG_DP_MAINLINK_CTRL,
+					DP_MAINLINK_FB_BOUNDARY_SEL |
+					DP_MAINLINK_CTRL_ENABLE);
+	} else {
+		mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+		mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE;
+		dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
+	}
+}
+
+void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog,
+					u32 colorimetry_cfg,
+					u32 test_bits_depth)
+{
+	u32 misc_val;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	misc_val = dp_read_link(catalog, REG_DP_MISC1_MISC0);
+	misc_val |= colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT;
+	misc_val |= test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT;
+	/* Configure clock to synchronous mode */
+	misc_val |= DP_MISC0_SYNCHRONOUS_CLK;
+
+	DRM_DEBUG_DP("misc settings = 0x%x\n", misc_val);
+	dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val);
+}
+
+void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
+					u32 rate, u32 stream_rate_khz,
+					bool fixed_nvid)
+{
+	u32 pixel_m, pixel_n;
+	u32 mvid, nvid;

drivers/gpu/drm/msm/dp/dp_catalog.c new file +79 -0

+
+	mvid = (pixel_m & 0xFFFF) * 5;
+	nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
+
+	if (nvid < nvid_fixed) {
+		u32 temp;
+
+		temp = (nvid_fixed / nvid) * nvid;
+		mvid = (nvid_fixed / nvid) * mvid;
+		nvid = temp;
+	}
+
+	if (link_rate_hbr2 == rate)
+		nvid *= 2;
+
+	if (link_rate_hbr3 == rate)
+		nvid *= 3;
+
+	DRM_DEBUG_DP("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
+	dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid);
+	dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid);
+	dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0);
+}
+
+
+int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog,
+					u32 pattern)
+{
+	int bit, ret;
+	u32 data;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	bit = BIT(pattern - 1);
+	DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, pattern);
+	dp_write_link(catalog, REG_DP_STATE_CTRL, bit);
+
+	bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;
+
+	/* Poll for mainlink ready status */
+	ret = readx_poll_timeout(readl, catalog->io->dp_link.base +
+					REG_DP_MAINLINK_READY,
+					data, data & bit,
+					POLLING_SLEEP_US, POLLING_TIMEOUT_US);
+	if (ret < 0) {
+		DRM_ERROR("set pattern for link_train=%d failed\n", pattern);
+		return ret;
+	}
+	return 0;
+}
+
+void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 typec_ctrl;
+
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL,
+			USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET_MUX |
+			USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET_MUX);
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_PHY_MODE_CTRL,
+						USB3_DP_COM_PHY_MODE_DP);
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET,
+						USB3_DP_COM_SW_RESET_SET);
+
+	/* Default configuration i.e CC1 */
+	typec_ctrl = USB3_DP_COM_TYPEC_CTRL_PORTSEL_MUX;
+	if (flip)
+		typec_ctrl |= USB3_DP_COM_TYPEC_CTRL_PORTSEL;
+
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_TYPEC_CTRL, typec_ctrl);
+
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_SWI_CTRL, 0x00);
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET, 0x00);
+
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_POWER_DOWN_CTRL,
+					USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN);
+	dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
+

drivers/gpu/drm/msm/dp/dp_catalog.c new file +10 -0

+
+	sw_reset = dp_read_ahb(catalog, REG_DP_SW_RESET);
+
+	sw_reset |= DP_SW_RESET;
+	dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset);
+	usleep_range(1000, 1100); /* h/w recommended delay */
+
+	sw_reset &= ~DP_SW_RESET;
+	dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset);
+}

drivers/gpu/drm/msm/dp/dp_catalog.c new file +10 -0

+				catalog->io->dp_link.base +
+				REG_DP_MAINLINK_READY,
+				data, data & DP_MAINLINK_READY_FOR_VIDEO,
+				POLLING_SLEEP_US, POLLING_TIMEOUT_US);
+	if (ret < 0) {
+		DRM_ERROR("mainlink not ready\n");
+		return false;
+	}
+
+	return true;

drivers/gpu/drm/msm/dp/dp_catalog.c new file +274 -0

+
+	if (enable) {
+		dp_write_ahb(catalog, REG_DP_INTR_STATUS,
+				DP_INTERRUPT_STATUS1_MASK);
+		dp_write_ahb(catalog, REG_DP_INTR_STATUS2,
+				DP_INTERRUPT_STATUS2_MASK);
+	} else {
+		dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00);
+		dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00);
+	}
+}
+
+void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool en)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	if (en) {
+		u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
+
+		dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK,
+				DP_DP_HPD_PLUG_INT_ACK |
+				DP_DP_IRQ_HPD_INT_ACK |
+				DP_DP_HPD_REPLUG_INT_ACK |
+				DP_DP_HPD_UNPLUG_INT_ACK);
+		dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK,
+				DP_DP_HPD_PLUG_INT_MASK |
+				DP_DP_IRQ_HPD_INT_MASK |
+				DP_DP_HPD_REPLUG_INT_MASK |
+				DP_DP_HPD_UNPLUG_INT_MASK);
+
+		/* Configure REFTIMER */
+		reftimer |= REFTIMER_DEFAULT_VALUE;
+		dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
+		/* Enable HPD */
+		dp_write_aux(catalog, REG_DP_DP_HPD_CTRL,
+				DP_DP_HPD_CTRL_HPD_EN);
+	} else {
+		/* Disable HPD */
+		dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0x0);
+	}
+}
+
+int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 intr, intr_ack;
+
+	intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS2);
+	intr &= ~DP_INTERRUPT_STATUS2_MASK;
+	intr_ack = (intr & DP_INTERRUPT_STATUS2)
+			<< DP_INTERRUPT_STATUS_ACK_SHIFT;
+	dp_write_ahb(catalog, REG_DP_INTR_STATUS2,
+			intr_ack | DP_INTERRUPT_STATUS2_MASK);
+
+	return intr;
+}
+
+void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	dp_write_ahb(catalog, REG_DP_PHY_CTRL,
+			DP_PHY_CTRL_SW_RESET_PLL | DP_PHY_CTRL_SW_RESET);
+	usleep_range(1000, 1100); /* h/w recommended delay */
+	dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0);
+}
+
+void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog,
+		bool flipped, u8 ln_cnt)
+{
+	u32 info;
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u8 orientation = BIT(!!flipped);
+
+	info = ln_cnt & DP_PHY_SPARE0_MASK;
+	info |= (orientation & DP_PHY_SPARE0_MASK)
+			<< DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT;
+	DRM_DEBUG_DP("Shared Info = 0x%x\n", info);
+
+	dp_write_phy(catalog, REG_DP_PHY_SPARE0, info);
+}
+
+int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog,
+		u8 v_level, u8 p_level)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u8 voltage_swing_cfg, pre_emphasis_cfg;
+
+	DRM_DEBUG_DP("hw: v=%d p=%d\n", v_level, p_level);
+
+	voltage_swing_cfg = vm_voltage_swing_hbr_rbr[v_level][p_level];
+	pre_emphasis_cfg = vm_pre_emphasis_hbr_rbr[v_level][p_level];
+
+	if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) {
+		DRM_ERROR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
+			v_level, voltage_swing_cfg, p_level, pre_emphasis_cfg);
+		return -EINVAL;
+	}
+
+	/* Enable MUX to use Cursor values from these registers */
+	voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
+	pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
+
+	/* Configure host and panel only if both values are allowed */
+	dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg);
+	dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg);
+	dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL,
+					pre_emphasis_cfg);
+	dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL,
+					pre_emphasis_cfg);
+	DRM_DEBUG_DP("hw: vx_value=0x%x px_value=0x%x\n",
+			voltage_swing_cfg, pre_emphasis_cfg);
+
+	return 0;
+}
+
+void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
+			u32 pattern)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 value = 0x0;
+
+	/* Make sure to clear the current pattern before starting a new one */
+	dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0);
+
+	switch (pattern) {
+	case DP_LINK_QUAL_PATTERN_D10_2:
+		dp_write_link(catalog, REG_DP_STATE_CTRL,
+				DP_STATE_CTRL_LINK_TRAINING_PATTERN1);
+		return;
+	case DP_LINK_QUAL_PATTERN_PRBS7:
+		dp_write_link(catalog, REG_DP_STATE_CTRL,
+				DP_STATE_CTRL_LINK_PRBS7);
+		return;
+	case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:
+		dp_write_link(catalog, REG_DP_STATE_CTRL,
+				DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN);
+		/* 00111110000011111000001111100000 */
+		dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0,
+				0x3E0F83E0);
+		/* 00001111100000111110000011111000 */
+		dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1,
+				0x0F83E0F8);
+		/* 1111100000111110 */
+		dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2,
+				0x0000F83E);
+		return;
+	case DP_LINK_QUAL_PATTERN_HBR2_EYE:
+	case DP_LINK_QUAL_PATTERN_ERROR_RATE:
+		value &= ~DP_HBR2_ERM_PATTERN;
+		if (pattern == DP_LINK_QUAL_PATTERN_HBR2_EYE)
+			value = DP_HBR2_ERM_PATTERN;
+		dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
+					value);
+		value |= SCRAMBLER_RESET_COUNT_VALUE;
+		dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
+					value);
+		dp_write_link(catalog, REG_DP_MAINLINK_LEVELS,
+					DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2);
+		dp_write_link(catalog, REG_DP_STATE_CTRL,
+					DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE);
+		return;
+	default:
+		DRM_DEBUG_DP("No valid test pattern requested:0x%x\n", pattern);
+		return;
+	}
+}
+
+u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	return dp_read_link(catalog, REG_DP_MAINLINK_READY);
+}
+
+/* panel related catalog functions */
+int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,
+				dp_catalog->total);
+	dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC,
+				dp_catalog->sync_start);
+	dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
+				dp_catalog->width_blanking);
+	dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
+	return 0;
+}
+
+void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog,
+				struct drm_display_mode *drm_mode)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+	u32 hsync_period, vsync_period;
+	u32 display_v_start, display_v_end;
+	u32 hsync_start_x, hsync_end_x;
+	u32 v_sync_width;
+	u32 hsync_ctl;
+	u32 display_hctl;
+
+	/* TPG config parameters*/
+	hsync_period = drm_mode->htotal;
+	vsync_period = drm_mode->vtotal;
+
+	display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) *
+					hsync_period);
+	display_v_end = ((vsync_period - (drm_mode->vsync_start -
+					drm_mode->vdisplay))
+					* hsync_period) - 1;
+
+	display_v_start += drm_mode->htotal - drm_mode->hsync_start;
+	display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay);
+
+	hsync_start_x = drm_mode->htotal - drm_mode->hsync_start;
+	hsync_end_x = hsync_period - (drm_mode->hsync_start -
+					drm_mode->hdisplay) - 1;
+
+	v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start;
+
+	hsync_ctl = (hsync_period << 16) |
+			(drm_mode->hsync_end - drm_mode->hsync_start);
+	display_hctl = (hsync_end_x << 16) | hsync_start_x;
+
+
+	dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0);
+	dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);
+	dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period *
+			hsync_period);
+	dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width *
+			hsync_period);
+	dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl);
+	dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0);
+	dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start);
+	dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end);
+	dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
+	dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0);
+
+	dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL,
+				DP_TPG_CHECKERED_RECT_PATTERN);
+	dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG,
+				DP_TPG_VIDEO_CONFIG_BPP_8BIT |
+				DP_TPG_VIDEO_CONFIG_RGB);
+	dp_write_p0(catalog, MMSS_DP_BIST_ENABLE,
+				DP_BIST_ENABLE_DPBIST_EN);
+	dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN,
+				DP_TIMING_ENGINE_EN_EN);
+	DRM_DEBUG_DP("%s: enabled tpg\n", __func__);
+}
+
+void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+				struct dp_catalog_private, dp_catalog);
+
+	dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0);
+	dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0);
+	dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0);

drivers/gpu/drm/msm/dp/dp_catalog.c new file +1 -0

+}

drivers/gpu/drm/msm/dp/dp_catalog.h new file +75 -0

new file mode 100644
index 0000000..c453586d
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DP_CATALOG_H_
+#define _DP_CATALOG_H_
+
+#include "dp_parser.h"
+
+/* interrupts */
+#define DP_INTR_HPD		BIT(0)
+#define DP_INTR_AUX_I2C_DONE	BIT(3)
+#define DP_INTR_WRONG_ADDR	BIT(6)
+#define DP_INTR_TIMEOUT		BIT(9)
+#define DP_INTR_NACK_DEFER	BIT(12)
+#define DP_INTR_WRONG_DATA_CNT	BIT(15)
+#define DP_INTR_I2C_NACK	BIT(18)
+#define DP_INTR_I2C_DEFER	BIT(21)
+#define DP_INTR_PLL_UNLOCKED	BIT(24)
+#define DP_INTR_AUX_ERROR	BIT(27)
+
+#define DP_INTR_READY_FOR_VIDEO		BIT(0)
+#define DP_INTR_IDLE_PATTERN_SENT	BIT(3)
+#define DP_INTR_FRAME_END		BIT(6)
+#define DP_INTR_CRC_UPDATED		BIT(9)
+
+struct dp_catalog {
+	u32 aux_data;
+	u32 total;
+	u32 sync_start;
+	u32 width_blanking;
+	u32 dp_active;
+};
+
+/* AUX APIs */
+u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
+int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
+int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog);
+int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read);
+void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
+void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog,
+			struct dp_aux_cfg *cfg,
+			enum dp_phy_aux_config_type type);
+void dp_catalog_aux_setup(struct dp_catalog *dp_catalog,
+			struct dp_aux_cfg *aux_cfg);
+int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
+
+/* DP Controller APIs */
+void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
+void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
+void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
+void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
+				u32 stream_rate_khz, bool fixed_nvid);
+int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern);
+void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip);
+bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, bool flipped,
+				u8 lane_cnt);
+int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
+				u8 p_level);
+int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
+				u32 dp_tu, u32 valid_boundary,
+				u32 valid_boundary2);
+void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
+				u32 pattern);
+u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog);