Add SS/HS-USB changes for Qualcomm SM8150 chipset
v3 cover Add SS/HS-USB changes for Qualcomm SM8150 chipset
This series adds support for the Synopsis 7nm HSPHY USB driver being used in QCOM chipsets. The HSPHY register map differs compared to other PHY revisions. In addition, modifications and updates are done to the QMP driver to add new registers/offsets, and to update the initialization sequence for enabling the SSUSB path on SM8150.
Changes in v3:
- Use devm_reset_control_get_exclusive instead of referencing index for reset handle
Changes in v2:
- Fixed YAML errors caught by dt_binding_check
Jack Pham (1):
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support
Wesley Cheng (3):
dt-bindings: phy: Add binding for qcom,usb-hs-7nm
phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs
phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
.../devicetree/bindings/phy/qcom,usb-hs-7nm.yaml | 76 ++++++ drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-qmp.c | 157 +++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 198 +++++++++++++- drivers/phy/qualcomm/phy-qcom-snps-7nm.c | 294 +++++++++++++++++++++ 6 files changed, 734 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-7nm.c
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PATCH v3 1/4 dt-bindings: phy: Add binding for qcom,usb-hs-7nm
This binding shows the descriptions and properties for the 7nm Synopsis HS USB PHY used on QCOM platforms.
Signed-off-by Wesley Cheng <[email protected]>
Reviewed-by Rob Herring <[email protected]>
--- .../devicetree/bindings/phy/qcom,usb-hs-7nm.yaml | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml
Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml new file +76 -0
@@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-7nm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys 7nm High-Speed USB PHY + +maintainers: + - Wesley Cheng <[email protected]> + +description: | + Qualcomm Hi-Speed 7nm USB PHY + +properties: + compatible: + enum: + - qcom,usb-snps-hs-7nm-phy + - qcom,sm8150-usb-hs-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: rpmhcc ref clock + + clock-names: + items: + - const: ref + + resets: + items: + - description: PHY core reset + + vdda-pll-supply: + description: phandle to the regulator VDD supply node. + + vdda18-supply: + description: phandle to the regulator 1.8V supply node. + + vdda33-supply: + description: phandle to the regulator 3.3V supply node. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - vdda-pll-supply + - vdda18-supply + - vdda33-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sm8150.h> + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sm8150-usb-hs-phy"; + reg = <0 0x088e2000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; +...
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PATCH v3 2/4 phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs
In reply to Wesley ChengThis adds the SNPS FemtoPHY driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver.
Signed-off-by Wesley Cheng <[email protected]>
Reviewed-by Philipp Zabel <[email protected]>
--- drivers/phy/qualcomm/Kconfig | 10 ++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-snps-7nm.c | 294 +++++++++++++++++++++++++++++++ 3 files changed, 305 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-7nm.c
drivers/phy/qualcomm/Kconfig +10 -0
@@ -85,6 +85,16 @@ config PHY_QCOM_USB_HS Support for the USB high-speed ULPI compliant phy on Qualcomm chipsets. +config PHY_QCOM_USB_SNPS_HS_7NM + tristate "Qualcomm 7nm USB HS PHY module" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable support for the USB high-speed SNPS phy on Qualcomm 7nm + chipsets. This PHY has differences in the register map compared + to the 28nm variant. The PHY is paired with a Synopsys DWC3 USB + controller on MSM SOCs. + config PHY_QCOM_USB_HSIC tristate "Qualcomm USB HSIC ULPI PHY module" depends on USB_ULPI_BUS
drivers/phy/qualcomm/Makefile +1 -0
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_USB_SNPS_HS_7NM) += phy-qcom-snps-7nm.o
drivers/phy/qualcomm/phy-qcom-snps-7nm.c new file +294 -0
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PATCH v3 3/4 phy: qcom-qmp: Add SM8150 QMP USB3 PHY support
In reply to Wesley ChengFrom: Jack Pham <[email protected]>
Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions.
Signed-off-by Jack Pham <[email protected]>
Signed-off-by Wesley Cheng <[email protected]>
--- drivers/phy/qualcomm/phy-qcom-qmp.c | 153 ++++++++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 198 +++++++++++++++++++++++++++++++++++- 2 files changed, 349 insertions(+), 2 deletions(-)
drivers/phy/qualcomm/phy-qcom-qmp.c +153 -0
@@ -160,6 +160,12 @@ enum qphy_reg_layout { [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, }; +static const unsigned int qmp_v4_usb3phy_regs_layout[] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x44 , + [QPHY_PCS_STATUS ] =0x14 , +}; +static const unsigned int sdm845_ufsphy_regs_layout[] = { [QPHY_START_CTRL ] =0x00 , [QPHY_PCS_READY_STATUS ] =0x160 ,
@@ -972,6 +978,115 @@ enum qphy_reg_layout { QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_EN_CENTER ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_PER1 ,0x31 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_PER2 ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 ,0xde ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 ,0x07 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 ,0xde ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 ,0x07 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SYSCLK_BUF_ENABLE ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CMN_IPTRIM ,0x20 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CP_CTRL_MODE0 ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CP_CTRL_MODE1 ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_RCTRL_MODE0 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_RCTRL_MODE1 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_CCTRL_MODE0 ,0x36 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_CCTRL_MODE1 ,0x36 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SYSCLK_EN_SEL ,0x1a ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP_EN ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP1_MODE0 ,0x14 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP2_MODE0 ,0x34 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP1_MODE1 ,0x34 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP2_MODE1 ,0x82 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DEC_START_MODE0 ,0x82 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DEC_START_MODE1 ,0x82 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START1_MODE0 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START2_MODE0 ,0xea ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START3_MODE0 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE_MAP ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START1_MODE1 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START2_MODE1 ,0xea ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START3_MODE1 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE1_MODE0 ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE1_MODE1 ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE2_MODE1 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_HSCLK_SEL ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CORECLK_DIV_MODE1 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 ,0xca ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 ,0x1e ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 ,0xca ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 ,0x1e ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL ,0x11 ), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_TX_RES_CODE_LANE_TX ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V4_TX_RES_CODE_LANE_RX ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V4_TX_LANE_MODE_1 ,0xd5 ), +QMP_PHY_INIT_CFG (QSERDES_V4_TX_RCV_DETECT_LVL_2 ,0x12 ), +QMP_PHY_INIT_CFG (QSERDES_V4_TX_PI_QEC_CTRL ,0x20 ), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SO_GAIN ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN ,0x2f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW ,0xff ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_PI_CONTROLS ,0x99 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SB2_THRESH1 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SB2_THRESH2 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SB2_GAIN1 ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SB2_GAIN2 ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_VGA_CAL_CNTRL1 ,0x54 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_VGA_CAL_CNTRL2 ,0x0e ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x4a ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW ,0xc0 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x77 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_SIGDET_CNTRL ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL ,0x0e ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_LOW ,0xbf ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH ,0xbf ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH2 ,0x3f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH3 ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH4 ,0x94 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_LOW ,0xdc ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH ,0xdc ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH2 ,0x5c ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH3 ,0x0b ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH4 ,0xb3 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DFE_EN_TIMER ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET ,0x38 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DCC_CTRL1 ,0x0c ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_GM_CAL ,0x1f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_VTH_CODE ,0x10 ), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { +/* Lock Det settings */ +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG1 ,0xd0 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG2 ,0x07 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG6 ,0x13 ), + +QMP_PHY_INIT_CFG (QPHY_V4_PCS_REFGEN_REQ_CONFIG1 ,0x21 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RX_SIGDET_LVL ,0xaa ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_CDR_RESET_TIME ,0x0a ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 ,0x88 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCS_TX_RX_CONFIG ,0x0c ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG1 ,0x4b ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG5 ,0x10 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL ,0xf8 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 ,0x07 ), +}; + +/* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg {/* phy-type - PCIE/UFS/USB */
@@ -1126,6 +1241,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) "aux", "cfg_ahb", "ref", "com_aux", }; +static const char *const qmp_v4_phy_clk_l[] = { +"aux" ,"ref_clk_src" ,"ref" ,"com_aux" , +}; +static const char *const sdm845_ufs_phy_clk_l[] = {"ref" ,"ref_aux" , };
@@ -1392,6 +1511,37 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { + .type =PHY_TYPE_USB3 , + .nlanes =1 , + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (sm8150_usb3_serdes_tbl), + .tx_tbl = sm8150_usb3_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (sm8150_usb3_tx_tbl), + .rx_tbl = sm8150_usb3_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (sm8150_usb3_rx_tbl), + .pcs_tbl = sm8150_usb3_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (sm8150_usb3_pcs_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks =ARRAY_SIZE (qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .start_ctrl =SERDES_START |PCS_START , + .pwrdn_ctrl =SW_PWRDN , + + .has_pwrdn_delay = true, + .pwrdn_delay_min =POWER_DOWN_DELAY_US_MIN , + .pwrdn_delay_max =POWER_DOWN_DELAY_US_MAX , + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + static void qcom_qmp_phy_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[],
@@ -2117,6 +2267,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = &sm8150_ufsphy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-usb3-phy", + .data = &sm8150_usb3phy_cfg, }, { }, };
drivers/phy/qualcomm/phy-qcom-qmp.h +196 -2
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PATCH v3 4/4 phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
In reply to Wesley ChengThe register map for SM8150 QMP USB SSPHY has moved QPHY_POWER_DOWN_CONTROL to a different offset. Allow for an offset in the register table to override default value if it is a DP capable PHY.
Signed-off-by Wesley Cheng <[email protected]>
--- drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp.c +4 -0
@@ -164,6 +164,7 @@ enum qphy_reg_layout { [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x44, [QPHY_PCS_STATUS] = 0x14, + [QPHY_COM_POWER_DOWN_CONTROL] = 0x40, };static const unsigned int sdm845_ufsphy_regs_layout[] = {
@@ -1627,6 +1628,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)if (cfg->has_phy_com_ctrl)qphy_setbits (serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL ],SW_PWRDN ); +else if (!cfg->has_phy_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL ]) +qphy_setbits (pcs, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL ], + cfg->pwrdn_ctrl);else qphy_setbits (pcs,QPHY_POWER_DOWN_CONTROL , cfg->pwrdn_ctrl);
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Re: [PATCH v3 4/4] phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
Quoted 24 lines · Wesley Cheng
The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROLto a different offset. Allow for an offset in the register table to override default value if it is a DP capable PHY.Signed-off-by Wesley Cheng <[email protected]>--- drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++++ 1 file changed, 4 insertions(+)drivers/phy/qualcomm/phy-qcom-qmp.c +1
-0@@ -164,6 +164,7 @@ enum qphy_reg_layout { [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x44, [QPHY_PCS_STATUS] = 0x14, + [QPHY_COM_POWER_DOWN_CONTROL] = 0x40, };static const unsigned int sdm845_ufsphy_regs_layout[] = {
drivers/phy/qualcomm/phy-qcom-qmp.c static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) · line 1636
Quoted 9 lines
drivers/phy/qualcomm/phy-qcom-qmp.c +3
-0@@ -1627,6 +1628,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)if (cfg->has_phy_com_ctrl)qphy_setbits (serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL ],SW_PWRDN ); +else if (!cfg->has_phy_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL ]) +qphy_setbits (pcs, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL ], + cfg->pwrdn_ctrl);else qphy_setbits (pcs,QPHY_POWER_DOWN_CONTROL , cfg->pwrdn_ctrl);
Will add logic to the qcom_qmp_phy_com_exit() API as well to fix the power down offset if DP com is being used, and will check for has_phy_dp_com_ctrl instead of !has_phy_com_ctrl, as to ensure this only applies to PHYs that have DP COM.
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