Add support for DisplayPort driver on SnapDragon.

From: Chandan Uddaraju <[email protected]>

Add bindings for Snapdragon DisplayPort and
display-port PLL driver.

Changes in V2:
Provide details about sel-gpio

Changes in V4:
Provide details about max dp lanes
Change the commit text

Changes in V5:
Moved dp.txt to yaml file.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display Port dt properties.
+

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +13 -0

+
+     reg-names:
+       description: |
+         Names for different register regions defined above. The required region
+         is mentioned below.
+       items:
+         - const: dp_ahb
+         - const: dp_aux
+         - const: dp_link
+         - const: dp_p0
+         - const: dp_phy
+         - const: dp_ln_tx0
+         - const: dp_ln_tx1

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +9 -0

+
+     clock-names:
+       description: |
+         Device clock names in the same order as mentioned in clocks property.
+         The required clocks are mentioned below.
+       items:
+         - const: core_aux_clk
+         - const: core_ref_clk_src
+         - const: core_usb_ref_clk

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +63 -0

+
+     aux-cfg1-settings:
+       description: |
+         Specifies the DP AUX configuration 1 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg2-settings:
+       description: |
+         Specifies the DP AUX configuration 2 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg3-settings:
+       description: |
+         Specifies the DP AUX configuration 3 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg4-settings:
+       description: |
+         Specifies the DP AUX configuration 4 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg5-settings:
+       description: |
+         Specifies the DP AUX configuration 5 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg6-settings:
+       description: |
+         Specifies the DP AUX configuration 6 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg7-settings:
+       description: |
+         Specifies the DP AUX configuration 7 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg8-settings:
+       description: |
+         Specifies the DP AUX configuration 8 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg9-settings:
+       description: |
+         Specifies the DP AUX configuration 9 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +9 -0

+
+     aux-en-gpio:
+       maxItems: 1
+       description: Specifies the aux-channel enable gpio.
+
+     aux-sel-gpio:
+       maxItems: 1
+       description: Specifies the sux-channel select gpio.
+

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +29 -0

+     type: object
+     description: Node contains properties of Display port pll and phy driver.
+
+     properties:
+       compatible:
+         items:
+           - const: qcom,dp-pll-10nm
+
+       cell-index:
+         description: Specifies the controller instance.
+
+       reg:
+         description: Physical base address and length of DP phy and pll registers.
+
+       reg-names:
+         description: |
+           Names for different register regions defined above. The required region
+           is mentioned below.
+         items:
+           - const: pll_base
+           - const: phy_base
+           - const: ln_tx0_base
+           - const: ln_tx1_base
+           - const: gdsc_base
+
+       clocks:
+         description: List of clock specifiers for clocks needed by the device.
+
+       clock-names:

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+                <0 0xae90200 0 0x200>,
+                <0 0xae90400 0 0xc00>,
+                <0 0xae91000 0 0x400>,
+                <0 0x88eaa00 0 0x200>,

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +64 -0

+
+        pll-node = <&dp_pll>;
+        vdda-1p2-supply = <&vreg_l3c_1p2>;
+        vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+        aux-cfg0-settings = [20 00];
+        aux-cfg1-settings = [24 13 23 1d];
+        aux-cfg2-settings = [28 24];
+        aux-cfg3-settings = [2c 00];
+        aux-cfg4-settings = [30 0a];
+        aux-cfg5-settings = [34 26];
+        aux-cfg6-settings = [38 0a];
+        aux-cfg7-settings = [3c 03];
+        aux-cfg8-settings = [40 bb];
+        aux-cfg9-settings = [44 03];
+
+        max-pclk-frequency-khz = <67500>;
+        data-lanes = <2>;
+
+        aux-en-gpio = <&msmgpio 55 1>;
+        aux-sel-gpio = <&msmgpio 110 1>;
+        usbplug-cc-gpio = <&msmgpio 90 1>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dp_in: endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dp_out: endpoint {
+                };
+            };
+        };
+    };
+
+    dp_pll: dp-pll@088ea000 {
+        compatible = "qcom,dp-pll-10nm";
+        label = "DP PLL";
+        cell-index = <0>;
+        #clock-cells = <1>;
+
+        reg = <0 0x088ea000 0 0x200>,
+              <0 0x088eaa00 0 0x200>,
+              <0 0x088ea200 0 0x200>,
+              <0 0x088ea600 0 0x200>,
+              <0 0x08803000 0 0x8>;
+        reg-names = "pll_base", "phy_base", "ln_tx0_base",
+            "ln_tx1_base", "gdsc_base";
+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+             <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+             <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+             <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+        clock-names = "iface_clk", "ref_clk",
+            "cfg_ahb_clk", "pipe_clk";
+    };
+

Documentation/devicetree/bindings/display/msm/dpu.txt +12 -4

index 551ae26..7e99e45 100644
@@ -63,8 +63,9 @@ Required properties:
 	Documentation/devicetree/bindings/graph.txt
 	Documentation/devicetree/bindings/media/video-interfaces.txt
 
-	Port 0 -> DPU_INTF1 (DSI1)
-	Port 1 -> DPU_INTF2 (DSI2)
+	Port 0 -> DPU_INTF0 (DP)
+	Port 1 -> DPU_INTF1 (DSI1)
+	Port 2 -> DPU_INTF2 (DSI2)
 
 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate assignment

@@ -125,13 +126,20 @@ Example:
 
 				port@0 {
 					reg = <0>;
-					dpu_intf1_out: endpoint {
-						remote-endpoint = <&dsi0_in>;
+					dpu_intf0_out: endpoint {
+						remote-endpoint = <&dp_in>;
 					};
 				};
 
 				port@1 {
 					reg = <1>;
+					dpu_intf1_out: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
 					dpu_intf2_out: endpoint {
 						remote-endpoint = <&dsi1_in>;
 					};

Signature · 5 lines

1.9.1
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

From: Chandan Uddaraju <[email protected]>

Add bindings for Snapdragon DisplayPort and display-port PLL driver.

Changes in V2:
Provide details about sel-gpio

Changes in V4:
Provide details about max dp lanes
Change the commit text

Changes in V5:
Moved dp.txt to yaml file.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

---
 .../devicetree/bindings/display/msm/dp-sc7180.yaml | 325

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +8 -0

+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display Port dt properties.
+
+maintainers:

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +9 -0

+         is mentioned below.
+       items:
+         - const: dp_ahb
+         - const: dp_aux
+         - const: dp_link
+         - const: dp_p0
+         - const: dp_phy
+         - const: dp_ln_tx0
+         - const: dp_ln_tx1

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +5 -0

+         The required clocks are mentioned below.
+       items:
+         - const: core_aux_clk
+         - const: core_ref_clk_src
+         - const: core_usb_ref_clk

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +56 -0

+
+     aux-cfg1-settings:
+       description: |
+         Specifies the DP AUX configuration 1 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg2-settings:
+       description: |
+         Specifies the DP AUX configuration 2 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg3-settings:
+       description: |
+         Specifies the DP AUX configuration 3 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg4-settings:
+       description: |
+         Specifies the DP AUX configuration 4 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg5-settings:
+       description: |
+         Specifies the DP AUX configuration 5 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg6-settings:
+       description: |
+         Specifies the DP AUX configuration 6 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg7-settings:
+       description: |
+         Specifies the DP AUX configuration 7 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg8-settings:
+       description: |
+         Specifies the DP AUX configuration 8 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +9 -0

+
+     aux-en-gpio:
+       maxItems: 1
+       description: Specifies the aux-channel enable gpio.
+
+     aux-sel-gpio:
+       maxItems: 1
+       description: Specifies the sux-channel select gpio.
+

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+                <0 0xae90200 0 0x200>,
+                <0 0xae90400 0 0xc00>,
+                <0 0xae91000 0 0x400>,
+                <0 0x88eaa00 0 0x200>,

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +64 -0

+
+        pll-node = <&dp_pll>;
+        vdda-1p2-supply = <&vreg_l3c_1p2>;
+        vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+        aux-cfg0-settings = [20 00];
+        aux-cfg1-settings = [24 13 23 1d];
+        aux-cfg2-settings = [28 24];
+        aux-cfg3-settings = [2c 00];
+        aux-cfg4-settings = [30 0a];
+        aux-cfg5-settings = [34 26];
+        aux-cfg6-settings = [38 0a];
+        aux-cfg7-settings = [3c 03];
+        aux-cfg8-settings = [40 bb];
+        aux-cfg9-settings = [44 03];
+
+        max-pclk-frequency-khz = <67500>;
+        data-lanes = <2>;
+
+        aux-en-gpio = <&msmgpio 55 1>;
+        aux-sel-gpio = <&msmgpio 110 1>;
+        usbplug-cc-gpio = <&msmgpio 90 1>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dp_in: endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dp_out: endpoint {
+                };
+            };
+        };
+    };
+
+    dp_pll: dp-pll@088ea000 {
+        compatible = "qcom,dp-pll-10nm";
+        label = "DP PLL";
+        cell-index = <0>;
+        #clock-cells = <1>;
+
+        reg = <0 0x088ea000 0 0x200>,
+              <0 0x088eaa00 0 0x200>,
+              <0 0x088ea200 0 0x200>,
+              <0 0x088ea600 0 0x200>,
+              <0 0x08803000 0 0x8>;
+        reg-names = "pll_base", "phy_base", "ln_tx0_base",
+            "ln_tx1_base", "gdsc_base";
+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+             <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+             <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+             <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+        clock-names = "iface_clk", "ref_clk",
+            "cfg_ahb_clk", "pipe_clk";
+    };
+

Documentation/devicetree/bindings/display/msm/dpu.txt +3 -2

index 551ae26..7e99e45 100644
@@ -63,8 +63,9 @@ Required properties:
 	Documentation/devicetree/bindings/graph.txt
 	Documentation/devicetree/bindings/media/video-interfaces.txt
 
-	Port 0 -> DPU_INTF1 (DSI1)
-	Port 1 -> DPU_INTF2 (DSI2)
+	Port 0 -> DPU_INTF0 (DP)
+	Port 1 -> DPU_INTF1 (DSI1)
+	Port 2 -> DPU_INTF2 (DSI2)
 
 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate 

assignment @@ -125,13 +126,20 @@ Example:

};
--
1.9.1
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Hi Tanmay

Reviewing the yaml bindings triggered a few comments. See below.

Sam

Quoted 12 lines

From: Chandan Uddaraju <[email protected]>

Add bindings for Snapdragon DisplayPort and
display-port PLL driver.

Changes in V2:
Provide details about sel-gpio

Changes in V4:
Provide details about max dp lanes
Change the commit text

Quoted 5 lines

Changes in V5:
Moved dp.txt to yaml file.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

As you handle the patch, thus the patch passed throgh you, you are supposed to sign-off the patch.

The changes to dpu.txt is not explained in the changelog.

Quoted 9 lines

---
 .../devicetree/bindings/display/msm/dp-sc7180.yaml | 325 
+++++++++++++++++++++
 .../devicetree/bindings/display/msm/dpu.txt        |  16 +-
 2 files changed, 337 insertions(+), 4 deletions(-)
 create mode 100644 

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 1

Quoted 7 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +1 -0

new file mode 100644
index 0000000..761a01d
@@ -0,0 +1,325 @@
+# SPDX-License-Identifier: GPL-2.0-only

For new bindings please use: (GPL-2.0-only OR BSD-2-Clause)

Quoted 15 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +13 -0

+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display Port dt properties.
+
+maintainers:
+  - Chandan Uddaraju <[email protected]>
+  - Vara Reddy <[email protected]>
+
+description: |
+  Device tree bindings for MSM Display Port which supports DP host 

controllers

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 18

Quoted 4 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+  that are compatible with VESA Display Port interface specification.
+
+properties:
+  "msm_dp":

The quotes seems not necessary.
This describes the name of the node.
The typical way to identify a node is using a compatible.

So I think that the right solution here is to drop "msm_dp".

Quoted 5 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +3 -0

+    type: object
+    description: |
+      Node containing Display port register address bases, clocks, 

power supplies.
+

And start here.

Quoted 4 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+    properties:
+     compatible:
+       items:
+         - const: qcom,dp-display

Quoted 7 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +6 -0

+
+     cell-index:
+       description: Specifies the controller instance.
+
+     reg:
+       description: Physical base address and length of controller's 

registers.

This description is generic and can be omitted.

But it would be good with a descrition of the individual registers like this:

reg:
items:
- description: AHB bla bla
- description: aux bla bla

Quoted 21 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+     reg-names:
+       description: |
+         Names for different register regions defined above. The 

required region

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +15 -0

+         is mentioned below.
+       items:
+         - const: dp_ahb
+         - const: dp_aux
+         - const: dp_link
+         - const: dp_p0
+         - const: dp_phy
+         - const: dp_ln_tx0
+         - const: dp_ln_tx1
+         - const: afprom_physical
+         - const: dp_pll
+         - const: usb3_dp_com
+         - const: hdcp_physical
+
+     interrupts:

Quoted 5 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+       description: The interrupt signal from the DP block.
+
+     clocks:
+       description: List of clock specifiers for clocks needed by the 

device.

items:
- description: aux clock bla bla
- description: ref clock bla bla

Quoted 15 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+     clock-names:
+       description: |
+         Device clock names in the same order as mentioned in clocks 

property.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +8 -0

+         The required clocks are mentioned below.
+       items:
+         - const: core_aux_clk
+         - const: core_ref_clk_src
+         - const: core_usb_ref_clk
+         - const: core_usb_cfg_ahb_clk
+         - const: core_usb_pipe_clk
+         - const: ctrl_link_clk

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 74

Quoted 7 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         - const: ctrl_link_iface_clk
+         - const: ctrl_pixel_clk
+         - const: crypto_clk
+         - const: pixel_clk_rcg
+
+     pll-node:
+       description: phandle to DP PLL node.

Add type (phandle)

Quoted 13 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +11 -0

+
+     vdda-1p2-supply:
+       description: phandle to vdda 1.2V regulator node.
+
+     vdda-0p9-supply:
+       description: phandle to vdda 0.9V regulator node.
+
+     aux-cfg0-settings:
+       description: |
+         Specifies the DP AUX configuration 0 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml

Quoted 2 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.

Add type, goes for all *-settings

Quoted 80 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +5 -0

+
+     aux-cfg1-settings:
+       description: |
+         Specifies the DP AUX configuration 1 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg2-settings:
+       description: |
+         Specifies the DP AUX configuration 2 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg3-settings:
+       description: |
+         Specifies the DP AUX configuration 3 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg4-settings:
+       description: |
+         Specifies the DP AUX configuration 4 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg5-settings:
+       description: |
+         Specifies the DP AUX configuration 5 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg6-settings:
+       description: |
+         Specifies the DP AUX configuration 6 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg7-settings:
+       description: |
+         Specifies the DP AUX configuration 7 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg8-settings:
+       description: |
+         Specifies the DP AUX configuration 8 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg9-settings:
+       description: |
+         Specifies the DP AUX configuration 9 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +5 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     max-pclk-frequency-khz:
+       description: Maximum displayport pixel clock supported for the 

chipset.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+
+     data-lanes:

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 160

Quoted 6 lines

+ description: Maximum number of lanes that can be used for
Display port.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+     usbplug-cc-gpio:
+       maxItems: 1
+       description: Specifies the usbplug orientation gpio.

Shall be named -gpios. Goes for all -gpio properties.
maxItems: 1 is good. Keep it.

Quoted 19 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +15 -0

+
+     aux-en-gpio:
+       maxItems: 1
+       description: Specifies the aux-channel enable gpio.
+
+     aux-sel-gpio:
+       maxItems: 1
+       description: Specifies the sux-channel select gpio.
+
+     ports:
+       description: |
+         Contains display port controller endpoint subnode.
+         remote-endpoint: |
+           For port@0, set to phandle of the connected panel/bridge's
+           input endpoint. For port@1, set to the DPU interface 

output.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+           Documentation/devicetree/bindings/graph.txt and
+           

Documentation/devicetree/bindings/media/video-interfaces.txt.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml

Quoted 2 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+
+  "dp_pll":

quotes should not be required here.

I looks like yo try to describe two differents nodes in the same file. Consider to split in two files.

Some of the comments from above applies here too.

Quoted 36 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+     type: object
+     description: Node contains properties of Display port pll and 

phy driver.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +11 -0

+
+     properties:
+       compatible:
+         items:
+           - const: qcom,dp-pll-10nm
+
+       cell-index:
+         description: Specifies the controller instance.
+
+       reg:
+         description: Physical base address and length of DP phy and 

pll registers.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+       reg-names:
+         description: |
+           Names for different register regions defined above. The 

required region

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +10 -0

+           is mentioned below.
+         items:
+           - const: pll_base
+           - const: phy_base
+           - const: ln_tx0_base
+           - const: ln_tx1_base
+           - const: gdsc_base
+
+       clocks:
+         description: List of clock specifiers for clocks needed by 

the device.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+       clock-names:
+         description: |
+           Device clock names in the same order as mentioned in 

clocks property.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 218

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +8 -0

+           The required clocks are mentioned below.
+         items:
+           - const: iface
+           - const: ref
+           - const: cfg_ahb
+           - const: pipe
+
+examples:

4 spaces as indent - good.
You have include files - good.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 226

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +8 -0

+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/gpio/gpio.h>
+    msm_dp: displayport-controller@ae90000{
+                cell-index = <0>;

indent only four spaces

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 228

Quoted 2 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+        compatible = "qcom,dp-display";
+        reg =   <0 0xae90000 0 0x200>,

Only one space after '=' - rememebr to adjust indent in following lines.

Quoted 4 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+                <0 0xae90200 0 0x200>,
+                <0 0xae90400 0 0xc00>,
+                <0 0xae91000 0 0x400>,
+                <0 0x88eaa00 0 0x200>,

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 242

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +10 -0

+                <0 0x88ea200 0 0x200>,
+                <0 0x88ea600 0 0x200>,
+                <0 0x780000 0 0x6228>,
+                <0 0x088ea000 0 0x40>,
+                <0 0x88e8000 0 0x20>,
+                <0 0x0aee1000 0 0x034>;
+        reg-names = "dp_ahb", "dp_aux", "dp_link",
+            "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+            "qfprom_physical", "dp_pll",
+            "usb3_dp_com", "hdcp_physical";

Indent so names in following lines starts where names in previous lines starts.
Like this:

        reg-names = "dp_ahb", "dp_aux", "dp_link",
                    "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
                    "qfprom_physical", "dp_pll",
                    "usb3_dp_com", "hdcp_physical";

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 248

Quoted 6 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +6 -0

+
+        interrupt-parent = <&display_subsystem>;
+        interrupts = <12 0>;
+
+        clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+            <&rpmhcc RPMH_CXO_CLK>,

Indent so '<' are aligned under each other. Like done above for reg =

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 261

Quoted 13 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +13 -0

+            <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+            <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+            <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+        clock-names = "core_aux_clk", "core_ref_clk_src",
+            "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+            "core_usb_pipe_clk", "ctrl_link_clk",
+            "ctrl_link_iface_clk", "ctrl_pixel_clk",
+            "crypto_clk", "pixel_clk_rcg";

Fix indent

Quoted 102 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +64 -0

+
+        pll-node = <&dp_pll>;
+        vdda-1p2-supply = <&vreg_l3c_1p2>;
+        vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+        aux-cfg0-settings = [20 00];
+        aux-cfg1-settings = [24 13 23 1d];
+        aux-cfg2-settings = [28 24];
+        aux-cfg3-settings = [2c 00];
+        aux-cfg4-settings = [30 0a];
+        aux-cfg5-settings = [34 26];
+        aux-cfg6-settings = [38 0a];
+        aux-cfg7-settings = [3c 03];
+        aux-cfg8-settings = [40 bb];
+        aux-cfg9-settings = [44 03];
+
+        max-pclk-frequency-khz = <67500>;
+        data-lanes = <2>;
+
+        aux-en-gpio = <&msmgpio 55 1>;
+        aux-sel-gpio = <&msmgpio 110 1>;
+        usbplug-cc-gpio = <&msmgpio 90 1>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dp_in: endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dp_out: endpoint {
+                };
+            };
+        };
+    };
+
+    dp_pll: dp-pll@088ea000 {
+        compatible = "qcom,dp-pll-10nm";
+        label = "DP PLL";
+        cell-index = <0>;
+        #clock-cells = <1>;
+
+        reg = <0 0x088ea000 0 0x200>,
+              <0 0x088eaa00 0 0x200>,
+              <0 0x088ea200 0 0x200>,
+              <0 0x088ea600 0 0x200>,
+              <0 0x08803000 0 0x8>;
+        reg-names = "pll_base", "phy_base", "ln_tx0_base",
+            "ln_tx1_base", "gdsc_base";
+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+             <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+             <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+             <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+        clock-names = "iface_clk", "ref_clk",
+            "cfg_ahb_clk", "pipe_clk";
+    };
+

Documentation/devicetree/bindings/display/msm/dpu.txt +3 -2

index 551ae26..7e99e45 100644
@@ -63,8 +63,9 @@ Required properties:
 	Documentation/devicetree/bindings/graph.txt
 	Documentation/devicetree/bindings/media/video-interfaces.txt
 
-	Port 0 -> DPU_INTF1 (DSI1)
-	Port 1 -> DPU_INTF2 (DSI2)
+	Port 0 -> DPU_INTF0 (DP)
+	Port 1 -> DPU_INTF1 (DSI1)
+	Port 2 -> DPU_INTF2 (DSI2)
 
 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate 

assignment

Documentation/devicetree/bindings/display/msm/dpu.txt +9 -2

@@ -125,13 +126,20 @@ Example:
 
 				port@0 {
 					reg = <0>;
-					dpu_intf1_out: endpoint {
-						remote-endpoint = <&dsi0_in>;
+					dpu_intf0_out: endpoint {
+						remote-endpoint = <&dp_in>;
 					};
 				};
 
 				port@1 {
 					reg = <1>;
+					dpu_intf1_out: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
 					dpu_intf2_out: endpoint {

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/dpu.txt +0 -1

 						remote-endpoint = <&dsi1_in>;
 					};
--

1.9.1
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +139 -0

+
+maintainers:
+  - Chandan Uddaraju <[email protected]>
+  - Vara Reddy <[email protected]>
+
+description: |
+  Device tree bindings for MSM Display Port which supports DP host controllers
+  that are compatible with VESA Display Port interface specification.
+
+properties:
+  "msm_dp":
+    type: object
+    description: |
+      Node containing Display port register address bases, clocks, power supplies.
+
+    properties:
+     compatible:
+       items:
+         - const: qcom,dp-display
+
+     cell-index:
+       description: Specifies the controller instance.
+
+     reg:
+       description: Physical base address and length of controller's registers.
+
+     reg-names:
+       description: |
+         Names for different register regions defined above. The required region
+         is mentioned below.
+       items:
+         - const: dp_ahb
+         - const: dp_aux
+         - const: dp_link
+         - const: dp_p0
+         - const: dp_phy
+         - const: dp_ln_tx0
+         - const: dp_ln_tx1
+         - const: afprom_physical
+         - const: dp_pll
+         - const: usb3_dp_com
+         - const: hdcp_physical
+
+     interrupts:
+       description: The interrupt signal from the DP block.
+
+     clocks:
+       description: List of clock specifiers for clocks needed by the device.
+
+     clock-names:
+       description: |
+         Device clock names in the same order as mentioned in clocks property.
+         The required clocks are mentioned below.
+       items:
+         - const: core_aux_clk
+         - const: core_ref_clk_src
+         - const: core_usb_ref_clk
+         - const: core_usb_cfg_ahb_clk
+         - const: core_usb_pipe_clk
+         - const: ctrl_link_clk
+         - const: ctrl_link_iface_clk
+         - const: ctrl_pixel_clk
+         - const: crypto_clk
+         - const: pixel_clk_rcg
+
+     pll-node:
+       description: phandle to DP PLL node.
+
+     vdda-1p2-supply:
+       description: phandle to vdda 1.2V regulator node.
+
+     vdda-0p9-supply:
+       description: phandle to vdda 0.9V regulator node.
+
+     aux-cfg0-settings:
+       description: |
+         Specifies the DP AUX configuration 0 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg1-settings:
+       description: |
+         Specifies the DP AUX configuration 1 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg2-settings:
+       description: |
+         Specifies the DP AUX configuration 2 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg3-settings:
+       description: |
+         Specifies the DP AUX configuration 3 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg4-settings:
+       description: |
+         Specifies the DP AUX configuration 4 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg5-settings:
+       description: |
+         Specifies the DP AUX configuration 5 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg6-settings:
+       description: |
+         Specifies the DP AUX configuration 6 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg7-settings:
+       description: |
+         Specifies the DP AUX configuration 7 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg8-settings:
+       description: |
+         Specifies the DP AUX configuration 8 settings.
+         The first entry in this array corresponds to the register offset
+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg9-settings:
+       description: |

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +72 -0

+
+     usbplug-cc-gpio:
+       maxItems: 1
+       description: Specifies the usbplug orientation gpio.
+
+     aux-en-gpio:
+       maxItems: 1
+       description: Specifies the aux-channel enable gpio.
+
+     aux-sel-gpio:
+       maxItems: 1
+       description: Specifies the sux-channel select gpio.
+
+     ports:
+       description: |
+         Contains display port controller endpoint subnode.
+         remote-endpoint: |
+           For port@0, set to phandle of the connected panel/bridge's
+           input endpoint. For port@1, set to the DPU interface output.
+           Documentation/devicetree/bindings/graph.txt and
+           Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+  "dp_pll":
+     type: object
+     description: Node contains properties of Display port pll and phy driver.
+
+     properties:
+       compatible:
+         items:
+           - const: qcom,dp-pll-10nm
+
+       cell-index:
+         description: Specifies the controller instance.
+
+       reg:
+         description: Physical base address and length of DP phy and pll registers.
+
+       reg-names:
+         description: |
+           Names for different register regions defined above. The required region
+           is mentioned below.
+         items:
+           - const: pll_base
+           - const: phy_base
+           - const: ln_tx0_base
+           - const: ln_tx1_base
+           - const: gdsc_base
+
+       clocks:
+         description: List of clock specifiers for clocks needed by the device.
+
+       clock-names:
+         description: |
+           Device clock names in the same order as mentioned in clocks property.
+           The required clocks are mentioned below.
+         items:
+           - const: iface
+           - const: ref
+           - const: cfg_ahb
+           - const: pipe
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/gpio/gpio.h>
+    msm_dp: displayport-controller@ae90000{
+                cell-index = <0>;
+        compatible = "qcom,dp-display";
+        reg =   <0 0xae90000 0 0x200>,

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +15 -0

+        reg-names = "dp_ahb", "dp_aux", "dp_link",
+            "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+            "qfprom_physical", "dp_pll",
+            "usb3_dp_com", "hdcp_physical";
+
+        interrupt-parent = <&display_subsystem>;
+        interrupts = <12 0>;
+
+        clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+            <&rpmhcc RPMH_CXO_CLK>,
+            <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+            <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+            <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +28 -0

+        data-lanes = <2>;
+
+        aux-en-gpio = <&msmgpio 55 1>;
+        aux-sel-gpio = <&msmgpio 110 1>;
+        usbplug-cc-gpio = <&msmgpio 90 1>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dp_in: endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dp_out: endpoint {
+                };
+            };
+        };
+    };
+
+    dp_pll: dp-pll@088ea000 {
+        compatible = "qcom,dp-pll-10nm";
+        label = "DP PLL";

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +9 -0

+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+             <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+             <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+             <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+        clock-names = "iface_clk", "ref_clk",
+            "cfg_ahb_clk", "pipe_clk";
+    };
+

Documentation/devicetree/bindings/display/msm/dpu.txt +0 -0

index 551ae26..7e99e45 100644

Documentation/devicetree/bindings/display/msm/dpu.txt +0 -0

 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate assignment

Quoting Tanmay Shah (2020-03-31 17:30:27)

Quoted 7 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +0 -0

new file mode 100644
index 0000000..761a01d

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 7

Quoted 7 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

@@ -0,0 +1,325 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display Port dt properties.

This title should be something like

"Qualcomm Display Port Controller"

Quoted 165 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+
+maintainers:
+  - Chandan Uddaraju <[email protected]>
+  - Vara Reddy <[email protected]>
+
+description: |
+  Device tree bindings for MSM Display Port which supports DP host

controllers

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+  that are compatible with VESA Display Port interface specification.
+
+properties:
+  "msm_dp":
+    type: object
+    description: |
+      Node containing Display port register address bases, clocks, 

power
supplies.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +11 -0

+
+    properties:
+     compatible:
+       items:
+         - const: qcom,dp-display
+
+     cell-index:
+       description: Specifies the controller instance.
+
+     reg:
+       description: Physical base address and length of controller's

registers.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+     reg-names:
+       description: |
+         Names for different register regions defined above. The 

required
region

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +19 -0

+         is mentioned below.
+       items:
+         - const: dp_ahb
+         - const: dp_aux
+         - const: dp_link
+         - const: dp_p0
+         - const: dp_phy
+         - const: dp_ln_tx0
+         - const: dp_ln_tx1
+         - const: afprom_physical
+         - const: dp_pll
+         - const: usb3_dp_com
+         - const: hdcp_physical
+
+     interrupts:
+       description: The interrupt signal from the DP block.
+
+     clocks:
+       description: List of clock specifiers for clocks needed by the

device.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+     clock-names:
+       description: |
+         Device clock names in the same order as mentioned in clocks

property.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +26 -0

+         The required clocks are mentioned below.
+       items:
+         - const: core_aux_clk
+         - const: core_ref_clk_src
+         - const: core_usb_ref_clk
+         - const: core_usb_cfg_ahb_clk
+         - const: core_usb_pipe_clk
+         - const: ctrl_link_clk
+         - const: ctrl_link_iface_clk
+         - const: ctrl_pixel_clk
+         - const: crypto_clk
+         - const: pixel_clk_rcg
+
+     pll-node:
+       description: phandle to DP PLL node.
+
+     vdda-1p2-supply:
+       description: phandle to vdda 1.2V regulator node.
+
+     vdda-0p9-supply:
+       description: phandle to vdda 0.9V regulator node.
+
+     aux-cfg0-settings:
+       description: |
+         Specifies the DP AUX configuration 0 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg1-settings:
+       description: |
+         Specifies the DP AUX configuration 1 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg2-settings:
+       description: |
+         Specifies the DP AUX configuration 2 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg3-settings:
+       description: |
+         Specifies the DP AUX configuration 3 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg4-settings:
+       description: |
+         Specifies the DP AUX configuration 4 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg5-settings:
+       description: |
+         Specifies the DP AUX configuration 5 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg6-settings:
+       description: |
+         Specifies the DP AUX configuration 6 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg7-settings:
+       description: |
+         Specifies the DP AUX configuration 7 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg8-settings:
+       description: |
+         Specifies the DP AUX configuration 8 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +7 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     aux-cfg9-settings:
+       description: |
+         Specifies the DP AUX configuration 9 settings.
+         The first entry in this array corresponds to the register 

offset

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +5 -0

+         within DP AUX, while the remaining entries indicate the
+         programmable values.
+
+     max-pclk-frequency-khz:
+       description: Maximum displayport pixel clock supported for the

chipset.

Quoted 5 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +3 -0

+
+     data-lanes:
+       description: Maximum number of lanes that can be used for 

Display
port.

This should be an array of cells, not a single cell indicating the number of lanes.

Quoted 83 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +19 -0

+
+     usbplug-cc-gpio:
+       maxItems: 1
+       description: Specifies the usbplug orientation gpio.
+
+     aux-en-gpio:
+       maxItems: 1
+       description: Specifies the aux-channel enable gpio.
+
+     aux-sel-gpio:
+       maxItems: 1
+       description: Specifies the sux-channel select gpio.
+
+     ports:
+       description: |
+         Contains display port controller endpoint subnode.
+         remote-endpoint: |
+           For port@0, set to phandle of the connected panel/bridge's
+           input endpoint. For port@1, set to the DPU interface 

output.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+           Documentation/devicetree/bindings/graph.txt and
+           

Documentation/devicetree/bindings/media/video-interfaces.txt.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+  "dp_pll":
+     type: object
+     description: Node contains properties of Display port pll and 

phy
driver.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +11 -0

+
+     properties:
+       compatible:
+         items:
+           - const: qcom,dp-pll-10nm
+
+       cell-index:
+         description: Specifies the controller instance.
+
+       reg:
+         description: Physical base address and length of DP phy and 

pll
registers.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+       reg-names:
+         description: |
+           Names for different register regions defined above. The

required region

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +10 -0

+           is mentioned below.
+         items:
+           - const: pll_base
+           - const: phy_base
+           - const: ln_tx0_base
+           - const: ln_tx1_base
+           - const: gdsc_base
+
+       clocks:
+         description: List of clock specifiers for clocks needed by 

the
device.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +4 -0

+
+       clock-names:
+         description: |
+           Device clock names in the same order as mentioned in 

clocks
property.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +18 -0

+           The required clocks are mentioned below.
+         items:
+           - const: iface
+           - const: ref
+           - const: cfg_ahb
+           - const: pipe
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/gpio/gpio.h>
+    msm_dp: displayport-controller@ae90000{
+                cell-index = <0>;
+        compatible = "qcom,dp-display";
+        reg =   <0 0xae90000 0 0x200>,

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 238

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +10 -0

+                <0 0xae90200 0 0x200>,
+                <0 0xae90400 0 0xc00>,
+                <0 0xae91000 0 0x400>,
+                <0 0x88eaa00 0 0x200>,
+                <0 0x88ea200 0 0x200>,
+                <0 0x88ea600 0 0x200>,
+                <0 0x780000 0 0x6228>,
+                <0 0x088ea000 0 0x40>,
+                <0 0x88e8000 0 0x20>,
+                <0 0x0aee1000 0 0x034>;

This needs to be split up into at least two nodes. Any address above that starts in 88e needs to be put into a new node underneath the qmp phy. That is the "DP PHY" that lives in the power domain of the USB+DP combo phy. The qfprom_physical reg property should be removed from here and this binding should use the nvmem binding to reach into the qfprom to read out things (I guess there's some sort of HDCP key in the qfprom?).

After that I don't know why there are so many different reg properties for the DP controller here and why it needs to be split up. It looks like we should just map the register space from 0xae90000 up to 0xae91400 as one big register region and have the driver figure out how to operate on top of that. If it changes between SoC versions then we should have a more specific compatible that tells us what registers are in what place.

Quoted 22 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +22 -0

+        reg-names = "dp_ahb", "dp_aux", "dp_link",
+            "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+            "qfprom_physical", "dp_pll",
+            "usb3_dp_com", "hdcp_physical";
+
+        interrupt-parent = <&display_subsystem>;
+        interrupts = <12 0>;
+
+        clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+            <&rpmhcc RPMH_CXO_CLK>,
+            <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+            <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+            <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
+            <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+        clock-names = "core_aux_clk", "core_ref_clk_src",
+            "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+            "core_usb_pipe_clk", "ctrl_link_clk",
+            "ctrl_link_iface_clk", "ctrl_pixel_clk",

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 263

Quoted 3 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +3 -0

+            "crypto_clk", "pixel_clk_rcg";
+
+        pll-node = <&dp_pll>;

If the DP PLL and DP controller need to be controlled from two software entities, it may make sense to just combine that DP PLL into the controller node and have this node be a clk provider. The pll-node property is pretty ugly and should be removed.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 276

Quoted 13 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +13 -0

+        vdda-1p2-supply = <&vreg_l3c_1p2>;
+        vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+        aux-cfg0-settings = [20 00];
+        aux-cfg1-settings = [24 13 23 1d];
+        aux-cfg2-settings = [28 24];
+        aux-cfg3-settings = [2c 00];
+        aux-cfg4-settings = [30 0a];
+        aux-cfg5-settings = [34 26];
+        aux-cfg6-settings = [38 0a];
+        aux-cfg7-settings = [3c 03];
+        aux-cfg8-settings = [40 bb];
+        aux-cfg9-settings = [44 03];

This pile of properties is board specific configuration tuning or something? Can this go into the driver? Or can it be made more human readable? I seem to recall that the USB phy had similar properties and we made them into human readable properties when board integrators needed to change them. The easiest approach there is to put everything in the driver for now and then when something has to change for a board it gets punted out to the DT and that overrides the "default" settings that are used in the driver.

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 278

Quoted 2 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +2 -0

+
+        max-pclk-frequency-khz = <67500>;

What is this? Why isn't this in the driver?

Quoted 28 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +28 -0

+        data-lanes = <2>;
+
+        aux-en-gpio = <&msmgpio 55 1>;
+        aux-sel-gpio = <&msmgpio 110 1>;
+        usbplug-cc-gpio = <&msmgpio 90 1>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dp_in: endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dp_out: endpoint {
+                };
+            };
+        };
+    };
+
+    dp_pll: dp-pll@088ea000 {
+        compatible = "qcom,dp-pll-10nm";
+        label = "DP PLL";

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml line 316

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +10 -0

+        cell-index = <0>;
+        #clock-cells = <1>;
+
+        reg = <0 0x088ea000 0 0x200>,
+              <0 0x088eaa00 0 0x200>,
+              <0 0x088ea200 0 0x200>,
+              <0 0x088ea600 0 0x200>,
+              <0 0x08803000 0 0x8>;
+        reg-names = "pll_base", "phy_base", "ln_tx0_base",
+            "ln_tx1_base", "gdsc_base";

I guess the DP_PLL lives inside the qmp combo phy? That would match how the USB phy binding has been done there. This whole node should be combined with the DP phy node that will be placed as a child of the qmp phy wrapper (i.e. qcom,sc7180-qmp-usb3-phy compatible node). Might as well change that compatible from qcom,sc7180-qmp-usb3-phy to be qcom,sc7180-qmp-usb3-dp-phy too so that it can create the DP phy bits too.

Quoted 18 lines

Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml new file +9 -0

+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+             <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+             <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+             <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+        clock-names = "iface_clk", "ref_clk",
+            "cfg_ahb_clk", "pipe_clk";
+    };
+

Documentation/devicetree/bindings/display/msm/dpu.txt +0 -0

index 551ae26..7e99e45 100644
@@ -63,8 +63,9 @@ Required properties:
        Documentation/devicetree/bindings/graph.txt
        Documentation/devicetree/bindings/media/video-interfaces.txt
 

Documentation/devicetree/bindings/display/msm/dpu.txt Required properties: · line 68

Quoted 5 lines

Documentation/devicetree/bindings/display/msm/dpu.txt +3 -2

-       Port 0 -> DPU_INTF1 (DSI1)
-       Port 1 -> DPU_INTF2 (DSI2)
+       Port 0 -> DPU_INTF0 (DP)
+       Port 1 -> DPU_INTF1 (DSI1)
+       Port 2 -> DPU_INTF2 (DSI2)

DP should come last so that the port mapping doesn't have to change.

Quoted 4 lines

Documentation/devicetree/bindings/display/msm/dpu.txt +0 -0

 Optional properties:
 - assigned-clocks: list of clock specifiers for clocks needing rate

assignment

From: Chandan Uddaraju <[email protected]>

The constant N value (0x8000) is used by multiple DP

drivers. Define this value in header file and use this in the existing i915 display driver.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

Quoting Tanmay Shah (2020-03-31 17:30:28)

Quoted 3 lines

From: Chandan Uddaraju <[email protected]>

The constant N value (0x8000) is used by multiple DP

There's one driver using it, not multiple.

Quoted 5 lines

drivers. Define this value in header file and use this in the existing i915 display driver.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c new file +43 -0

new file mode 100644
index 0000000..aa845d0
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+/*
+ * Display Port PLL driver block diagram for branch clocks
+ *
+ *              +------------------------------+
+ *              |         DP_VCO_CLK           |
+ *              |                              |
+ *              |    +-------------------+     |
+ *              |    |   (DP PLL/VCO)    |     |
+ *              |    +---------+---------+     |
+ *              |              v               |
+ *              |   +----------+-----------+   |
+ *              |   | hsclk_divsel_clk_src |   |
+ *              |   +----------+-----------+   |
+ *              +------------------------------+
+ *                              |
+ *          +---------<---------v------------>----------+
+ *          |                                           |
+ * +--------v---------+                                 |
+ * |    dp_phy_pll    |                                 |
+ * |     link_clk     |                                 |
+ * +--------+---------+                                 |
+ *          |                                           |
+ *          |                                           |
+ *          v                                           v
+ * Input to DISPCC block                                |
+ * for link clk, crypto clk                             |
+ * and interface clock                                  |
+ *                                                      |
+ *                                                      |
+ *      +--------<------------+-----------------+---<---+
+ *      |                     |                 |
+ * +----v---------+  +--------v-----+  +--------v------+
+ * | vco_divided  |  | vco_divided  |  | vco_divided   |
+ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
+ * |              |  |              |  |               |
+ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
+ * +-------+------+  +-----+--------+  +--------+------+
+ *         |                 |                  |

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c new file +16 -0

+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#include "dp_pll_10nm.h"
+
+#define NUM_PROVIDED_CLKS              2
+
+#define DP_LINK_CLK_SRC                        0
+#define DP_PIXEL_CLK_SRC               1
+

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +16 -0

new file mode 100644
index 0000000..fff2e8d
@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#define pr_fmt(fmt)    "%s: " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+
+#include "dp_hpd.h"
+#include "dp_pll.h"
+#include "dp_pll_10nm.h"
+

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +11 -0

+
+static int dp_config_vco_rate_10nm(struct msm_dp_pll *pll,
+               unsigned long rate)
+{
+       u32 res = 0;
+       struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll);
+
+       res = dp_vco_pll_init_db_10nm(pll, rate);
+       if (res) {
+               DRM_ERROR("VCO Init DB failed\n");
+               return res;

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +5 -0

+
+long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *parent_rate)
+{
+       unsigned long rrate = rate;

Quoting Tanmay Shah (2020-03-31 17:30:30)

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c

Quoted 49 lines

new file mode 100644
index 0000000..aa845d0

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c new file +3 -0

@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights 

reserved.
+ */

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c new file +39 -0

+
+/*
+ * Display Port PLL driver block diagram for branch clocks
+ *
+ *              +------------------------------+
+ *              |         DP_VCO_CLK           |
+ *              |                              |
+ *              |    +-------------------+     |
+ *              |    |   (DP PLL/VCO)    |     |
+ *              |    +---------+---------+     |
+ *              |              v               |
+ *              |   +----------+-----------+   |
+ *              |   | hsclk_divsel_clk_src |   |
+ *              |   +----------+-----------+   |
+ *              +------------------------------+
+ *                              |
+ *          +---------<---------v------------>----------+
+ *          |                                           |
+ * +--------v---------+                                 |
+ * |    dp_phy_pll    |                                 |
+ * |     link_clk     |                                 |
+ * +--------+---------+                                 |
+ *          |                                           |
+ *          |                                           |
+ *          v                                           v
+ * Input to DISPCC block                                |
+ * for link clk, crypto clk                             |
+ * and interface clock                                  |
+ *                                                      |
+ *                                                      |
+ *      +--------<------------+-----------------+---<---+
+ *      |                     |                 |
+ * +----v---------+  +--------v-----+  +--------v------+
+ * | vco_divided  |  | vco_divided  |  | vco_divided   |
+ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
+ * |              |  |              |  |               |
+ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
+ * +-------+------+  +-----+--------+  +--------+------+
+ *         |                 |                  |

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c line 53

Quoted 10 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c new file +10 -0

+ *         v---->----------v-------------<------v
+ *                         |
+ *              +----------+---------+
+ *              |   dp_phy_pll_vco   |
+ *              |       div_clk      |
+ *              +---------+----------+
+ *                        |
+ *                        v
+ *              Input to DISPCC block
+ *              for DP pixel clock

I suspect this shouldn't be a complicated clk provider at all. Take a look at commit 42d068472ddf ("phy: Add DisplayPort configuration options") for how the phy should manage the link rate, etc. If the dispcc pixel clock needs to know what rate is coming in, then a single clk_hw can be implemented here that tells the consumer (i.e. dispcc) the rate that it will see at the output of this node. Otherwise, modeling the clk tree inside this PLL block like this is super overly complicated and wasteful. Don't do it.

Quoted 16 lines

+ *
+ */

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c new file +14 -0

+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#include "dp_pll_10nm.h"
+
+#define NUM_PROVIDED_CLKS              2
+
+#define DP_LINK_CLK_SRC                        0
+#define DP_PIXEL_CLK_SRC               1
+

[...]

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c

Quoted 22 lines

new file mode 100644
index 0000000..fff2e8d

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +3 -0

@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights 

reserved.
+ */

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +12 -0

+
+#define pr_fmt(fmt)    "%s: " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+
+#include "dp_hpd.h"
+#include "dp_pll.h"
+#include "dp_pll_10nm.h"
+

[...]

Quoted 6 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +6 -0

+
+static int dp_config_vco_rate_10nm(struct msm_dp_pll *pll,
+               unsigned long rate)
+{
+       u32 res = 0;
+       struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll);

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c

Quoted 10 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +10 -0

+
+       res = dp_vco_pll_init_db_10nm(pll, rate);
+       if (res) {
+               DRM_ERROR("VCO Init DB failed\n");
+               return res;
+       }
+
+       if (dp_res->lane_cnt != 4) {
+               if (dp_res->orientation == ORIENTATION_CC2)
+                       PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL,

0x6d);

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c

Quoted 2 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +2 -0

+               else
+                       PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL,

0x75);

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c line 125

Quoted 3 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +3 -0

+       } else {
+               PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL, 0x7d);
+       }

For example, this part here can be done through the phy configuration ops. A lane count check in the set rate clk op is quite odd!

Quoted 5 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +5 -0

+
+long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *parent_rate)
+{
+       unsigned long rrate = rate;

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c line 517

Quoted 10 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +10 -0

+       struct msm_dp_pll *pll = to_msm_dp_pll(hw);
+
+       if (rate <= pll->min_rate)
+               rrate = pll->min_rate;
+       else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000)
+               rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
+       else if (rate <= DP_VCO_HSCLK_RATE_5400MHZDIV1000)
+               rrate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;
+       else
+               rrate = pll->max_rate;

This is basically link rate setting through the clk framework. Calling clk_set_rate() on the pixel clk is complicated and opaque. I'd expect to see the DP controller driver set the link rate on the phy with phy_configure(), and then that can change the rate that is seen downstream at the pixel clk. Does the pixel clk need to do anything with the rate? Probably not? I suspect it can just enable the pixel clk when it needs to and disable it when it doesn't need it.

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c line 521

Quoted 4 lines

drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c new file +4 -0

+
+       DRM_DEBUG_DP("%s: rrate=%ld\n", __func__, rrate);
+
+       *parent_rate = rrate;

_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

These patches add support for Display-Port driver on SnapDragon 845 hardware. It adds DP driver and DP PLL driver files along with the needed device-tree bindings.

The block diagram of DP driver is shown below:

                 +-------------+
                 |DRM FRAMEWORK|
                 +------+------+
                        |
                   +----v----+
                   | DP DRM  |
                   +----+----+
                        |
                   +----v----+
     +------------+|   DP    +----------++------+
     +             | DISPLAY |+---+      |      |
     |             +-+-----+-+    |      |      |
     |               |     |      |      |      |
     |               |     |      |      |      |
     |               |     |      |      |      |
     v               v     v      v      v      v
 +------+          +---+ +----+ +----+ +---+ +-----+
 |  DP  |          |DP | | DP | | DP | |DP | | DP  |
 |PARSER|          |AUX| |LINK| |CTRL| |PHY| |POWER|
 +--+---+          +---+ +----+ +--+-+ +-+-+ +-----+
    |                              |     |
 +--v---+                         +v-----v+
 |DEVICE|                         |  DP   |
 | TREE |                         |CATALOG|
 +------+                         +---+---+
                                      |
                                  +---v----+
                                  |CTRL/PHY|
                                  |   HW   |
                                  +--------+

These patches have dependency on clock driver changes mentioned below:
https://patchwork.kernel.org/patch/10632753/
https://patchwork.kernel.org/patch/10632757/

Chandan Uddaraju (4):
dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon
drm: add constant N value in helper file
drm/msm/dp: add displayPort driver support
drm/msm/dp: add support for DP PLL driver

Jeykumar Sankaran (1):
drm/msm/dpu: add display port support in DPU

 .../devicetree/bindings/display/msm/dp-sc7180.yaml |  325 ++++
 .../devicetree/bindings/display/msm/dpu.txt        |   16 +-
 drivers/gpu/drm/i915/display/intel_display.c       |    2 +-
 drivers/gpu/drm/msm/Kconfig                        |   21 +
 drivers/gpu/drm/msm/Makefile                       |   16 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |   28 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |    8 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   65 +-
 drivers/gpu/drm/msm/dp/dp_aux.c                    |  531 ++++++
 drivers/gpu/drm/msm/dp/dp_aux.h                    |   35 +
 drivers/gpu/drm/msm/dp/dp_catalog.c                |  988 +++++++++++
 drivers/gpu/drm/msm/dp/dp_catalog.h                |   86 +
 drivers/gpu/drm/msm/dp/dp_ctrl.c                   | 1707 ++++++++++++++++++++
 drivers/gpu/drm/msm/dp/dp_ctrl.h                   |   35 +
 drivers/gpu/drm/msm/dp/dp_display.c                |  943 +++++++++++
 drivers/gpu/drm/msm/dp/dp_display.h                |   31 +
 drivers/gpu/drm/msm/dp/dp_drm.c                    |  170 ++
 drivers/gpu/drm/msm/dp/dp_drm.h                    |   19 +
 drivers/gpu/drm/msm/dp/dp_hpd.c                    |   69 +
 drivers/gpu/drm/msm/dp/dp_hpd.h                    |   79 +
 drivers/gpu/drm/msm/dp/dp_link.c                   | 1216 ++++++++++++++
 drivers/gpu/drm/msm/dp/dp_link.h                   |  132 ++
 drivers/gpu/drm/msm/dp/dp_panel.c                  |  490 ++++++
 drivers/gpu/drm/msm/dp/dp_panel.h                  |   95 ++
 drivers/gpu/drm/msm/dp/dp_parser.c                 |  473 ++++++
 drivers/gpu/drm/msm/dp/dp_parser.h                 |  220 +++
 drivers/gpu/drm/msm/dp/dp_power.c                  |  545 +++++++
 drivers/gpu/drm/msm/dp/dp_power.h                  |  115 ++
 drivers/gpu/drm/msm/dp/dp_reg.h                    |  489 ++++++
 drivers/gpu/drm/msm/dp/pll/dp_pll.c                |  127 ++
 drivers/gpu/drm/msm/dp/pll/dp_pll.h                |   57 +
 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c           |  401 +++++
 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h           |   86 +
 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c      |  524 ++++++
 drivers/gpu/drm/msm/msm_drv.c                      |    2 +
 drivers/gpu/drm/msm/msm_drv.h                      |   53 +-
 include/drm/drm_dp_helper.h                        |    2 +
 37 files changed, 10178 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml
 create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_display.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_display.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_link.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_link.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_power.c
 create mode 100644 drivers/gpu/drm/msm/dp/dp_power.h
 create mode 100644 drivers/gpu/drm/msm/dp/dp_reg.h
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.c
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.h
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c

--
1.9.1