FAILED: patch "[PATCH] drm/i915/gt: Move snb GT workarounds from init_clock_gating" failed to apply to 5.4-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From fd2599bda5a989c3332f4956fd7760ec32bd51ee Mon Sep 17 00:00:00 2001
From: Chris Wilson <[email protected]>
Date: Thu, 11 Jun 2020 09:01:38 +0100
Subject: [PATCH] drm/i915/gt: Move snb GT workarounds from init_clock_gating
to workarounds
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied.
Signed-off-by Chris Wilson <[email protected]>
Reviewed-by Mika Kuoppala <[email protected]>
(cherry picked from commit c3b93a943f2c9ee4a106db100a2fc3b2f126bfc5)
Signed-off-by Joonas Lahtinen <[email protected]>
drivers/gpu/drm/i915/gt/intel_workarounds.c +41 -0
@@ -692,6 +692,45 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)return 0 ; } +static void +snb_gt_workarounds_init (struct drm_i915_private *i915,struct i915_wa_list *wal) +{ +/* WaDisableHiZPlanesWhenMSAAEnabled:snb */ +wa_masked_en (wal, + _3D_CHICKEN, + _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); + +/* WaDisable_RenderCache_OperationalFlush:snb */ +wa_masked_dis (wal,CACHE_MODE_0 ,RC_OP_FLUSH_ENABLE ); + +/* +* BSpec recommends 8x4 when MSAA is used, +* however in practice 16x4 seems fastest. +* +* Note that PS/WM thread counts depend on the WIZ hashing +* disable bit, which we don't touch here, but it's good +* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). +*/ +wa_add (wal, +GEN6_GT_MODE ,0 , +_MASKED_FIELD (GEN6_WIZ_HASHING_MASK , GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); + +wa_masked_dis (wal,CACHE_MODE_0 ,CM0_STC_EVICT_DISABLE_LRA_SNB ); + +wa_masked_en (wal, + _3D_CHICKEN3, +/* WaStripsFansDisableFastClipPerformanceFix:snb */ + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | +/* +* Bspec says: +* "This bit must be set if 3DSTATE_CLIP clip mode is set +* to normal and 3DSTATE_SF number of SF output attributes +* is more than 16." +*/ + _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); +} +static void ivb_gt_workarounds_init (struct drm_i915_private *i915,struct i915_wa_list *wal) {
@@ -1132,6 +1171,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)vlv_gt_workarounds_init (i915, wal); else if (IS_IVYBRIDGE(i915)) ivb_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 6)) + snb_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else
drivers/gpu/drm/i915/intel_pm.c +0 -33
@@ -6902,27 +6902,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)I915_READ (ILK_DISPLAY_CHICKEN2 ) | ILK_ELPIN_409_SELECT); -/* WaDisableHiZPlanesWhenMSAAEnabled:snb */ -I915_WRITE (_3D_CHICKEN, -_MASKED_BIT_ENABLE (_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); - -/* WaDisable_RenderCache_OperationalFlush:snb */ -I915_WRITE (CACHE_MODE_0 ,_MASKED_BIT_DISABLE (RC_OP_FLUSH_ENABLE )); - -/* -* BSpec recoomends 8x4 when MSAA is used, -* however in practice 16x4 seems fastest. -* -* Note that PS/WM thread counts depend on the WIZ hashing -* disable bit, which we don't touch here, but it's good -* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -*/ -I915_WRITE (GEN6_GT_MODE , -_MASKED_FIELD (GEN6_WIZ_HASHING_MASK , GEN6_WIZ_HASHING_16x4)); - -I915_WRITE (CACHE_MODE_0 , -_MASKED_BIT_DISABLE (CM0_STC_EVICT_DISABLE_LRA_SNB )); - I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
@@ -6945,18 +6924,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); -/* WaStripsFansDisableFastClipPerformanceFix:snb */ -I915_WRITE (_3D_CHICKEN3, -_MASKED_BIT_ENABLE (_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); - -/* -* Bspec says: -* "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and -* 3DSTATE_SF number of SF output attributes is more than 16." -*/ -I915_WRITE (_3D_CHICKEN3, -_MASKED_BIT_ENABLE (_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); -/* * According to the spec the following bits should be * set in order to enable memory self-refresh and fbc: