Add real clock support for Rockchip's RK3188
Subsystems (5)
Heiko Stübner
maintainercover Add real clock support for Rockchip's RK3188
This series add a clock driver infrastructure for Rockchip SoCs in general and clock-definitions for the RK3188 in particular.
Due to the lack of any usable documentation of the RK3188 clocks, the clock tree is based on my own doc [0] collected by analyzing the clock_data code in current Rockchip kernels. As a result the gathered data may contain errors. So to prevent API issues with the clock-ids, the exported ones are currently limited to well understood or really measured clocks.
The previous attempt to define parts separately in the devicetree did not really fit with the clock structure, which became apparent with more knowledge about the clock tree and this new driver framework, heavily inspired by the Samsung clock driver, fits very well for clock controllers in Rockchip SoCs.
The whole structure should support Rockchip SoCs at least down to the RK28xx (ARM9) which all share a very similar setup of their clock controllers in PLL, divider and gate handling as well as the included softreset parts.
[0] https://docs.google.com/document/d/1voaR9Xk3lisCQIG3ThySOSnSHBUequljQYnceFlr53w/edit?usp=sharing
Heiko Stuebner (11):
clk: divider: add CLK_DIVIDER_READ_ONLY flag
clk: rockchip: add basic infrastructure
clk: rockchip: add clock type for pll clocks and pll used on rk3066
clk: rockchip: add special cpu clock type
clk: rockchip: add reset controller
dt-bindings: add documentation for rk3188 clock and reset unit
clk: rockchip: add clock driver for rk3188 clocks
ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER
ARM: dts: rk3188: add cru node and update device clocks to use it
ARM: dts: rockchip: move rk3188 core input clocks into main dtsi
ARM: dts: rockchip: remove the now obsolete rk3188-clocks.dtsi
.../bindings/clock/rockchip,rk3188-cru.txt | 72 ++++ arch/arm/boot/dts/rk3188-clocks.dtsi | 289 ------------- arch/arm/boot/dts/rk3188.dtsi | 80 +++- arch/arm/mach-rockchip/Kconfig | 1 + drivers/clk/clk-divider.c | 10 +- drivers/clk/rockchip/Makefile | 6 + drivers/clk/rockchip/clk-cpu.c | 434 +++++++++++++++++++ drivers/clk/rockchip/clk-pll.c | 317 ++++++++++++++ drivers/clk/rockchip/clk-rk3188.c | 457 +++++++++++++++++++++ drivers/clk/rockchip/clk.c | 168 ++++++++ drivers/clk/rockchip/clk.h | 249 +++++++++++ drivers/clk/rockchip/softrst.c | 115 ++++++ include/dt-bindings/clock/rk3188-cru.h | 79 ++++ include/linux/clk-provider.h | 4 + 14 files changed, 1986 insertions(+), 295 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt delete mode 100644 arch/arm/boot/dts/rk3188-clocks.dtsi create mode 100644 drivers/clk/rockchip/clk-cpu.c create mode 100644 drivers/clk/rockchip/clk-pll.c create mode 100644 drivers/clk/rockchip/clk-rk3188.c create mode 100644 drivers/clk/rockchip/clk.c create mode 100644 drivers/clk/rockchip/clk.h create mode 100644 drivers/clk/rockchip/softrst.c create mode 100644 include/dt-bindings/clock/rk3188-cru.h
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 1/11 clk: divider: add CLK_DIVIDER_READ_ONLY flag
Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable.
Therefore add a READ_ONLY flag similar to the mux-one to clk-divider
Signed-off-by Heiko Stuebner <[email protected]>
--- drivers/clk/clk-divider.c | 10 +++++++++- include/linux/clk-provider.h | 4 ++++ 2 files changed, 13 insertions(+), 1 deletion(-)
drivers/clk/clk-divider.c +9 -1
@@ -249,6 +249,11 @@ const struct clk_ops clk_divider_ops = { };EXPORT_SYMBOL_GPL (clk_divider_ops); +const struct clk_ops clk_divider_ro_ops = { + .recalc_rate = clk_divider_recalc_rate, +}; +EXPORT_SYMBOL_GPL (clk_divider_ro_ops); + static struct clk *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width,
@@ -274,7 +279,10 @@ static struct clk *_register_divider(struct device *dev, const char *name, } init.name = name; - init.ops = &clk_divider_ops; +if (clk_divider_flags &CLK_DIVIDER_READ_ONLY ) + init.ops = &clk_divider_ro_ops; +else + init.ops = &clk_divider_ops; init.flags = flags |CLK_IS_BASIC ; init.parent_names = (parent_name ? &parent_name:NULL ); init.num_parents = (parent_name ?1 :0 );
include/linux/clk-provider.h +4 -0
@@ -312,6 +312,8 @@ struct clk_div_table {* of this register, and mask of divider bits are in higher 16-bit of this * register. While setting the divider bits, higher 16-bit should also be * updated to indicate changing divider bits. +* CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should +* not be changed by the clock framework. */ struct clk_divider {struct clk_hw hw;
@@ -327,8 +329,10 @@ struct clk_divider {#define CLK_DIVIDER_POWER_OF_TWO BIT(1)#define CLK_DIVIDER_ALLOW_ZERO BIT(2)#define CLK_DIVIDER_HIWORD_MASK BIT(3) +#define CLK_DIVIDER_READ_ONLY BIT(4)extern const struct clk_ops clk_divider_ops; +extern const struct clk_ops clk_divider_ro_ops; struct clk *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width,
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 2/11 clk: rockchip: add basic infrastructure
In reply to Heiko StübnerThis adds infrastructure for registering basic clock types. It is heavily inspired by the Samsung implementation and fits surprisingly well to the Rockchip clock controllers.
Signed-off-by Heiko Stuebner <[email protected]>
--- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk.c | 131 ++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 160 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+) create mode 100644 drivers/clk/rockchip/clk.c create mode 100644 drivers/clk/rockchip/clk.h
drivers/clk/rockchip/Makefile +1 -0
@@ -3,3 +3,4 @@ # obj-y += clk-rockchip.o +obj-y += clk.o
drivers/clk/rockchip/clk.c new file +131 -0
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drivers/clk/rockchip/clk.h new file +160 -0
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Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 3/11 clk: rockchip: add clock type for pll clocks and pll used on rk3066
In reply to Heiko StübnerAll known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle plls. 1 or more pll-dependant setting registers, a shared pll mode register and the pll lock status in a register somewhere else.
Therefore add shared infrastructure to handle the common pll actions and also the pll type used in rk3066 and rk3188 Cortex-A9 SoCs.
Signed-off-by Heiko Stuebner <[email protected]>
--- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-pll.c | 317 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 19 +++ drivers/clk/rockchip/clk.h | 66 +++++++++ 4 files changed, 403 insertions(+) create mode 100644 drivers/clk/rockchip/clk-pll.c
drivers/clk/rockchip/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-y += clk-rockchip.o obj-y += clk.o +obj-y += clk-pll.o
drivers/clk/rockchip/clk-pll.c new file +317 -0
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drivers/clk/rockchip/clk.c +19 -0
@@ -55,6 +55,25 @@ void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) clk_table[id] = clk; } +void __init rockchip_clk_register_plls (struct rockchip_pll_clock *list, +unsigned int nr_pll,void __iomem *reg_lock) +{ +struct clk *clk; +int idx; + +for (idx =0 ; idx < nr_pll; idx++, list++) { + clk =rockchip_clk_register_pll (list, reg_base, reg_lock, + &clk_lock); +if (IS_ERR (clk)) { +pr_err ("%s: failed to register clock %s\n" , __func__, + list->name); +continue ; + } + +rockchip_clk_add_lookup (clk, list->id); + } +} +void __init rockchip_clk_register_mux (struct rockchip_mux_clock *list,unsigned int nr_clk) {
drivers/clk/rockchip/clk.h +66 -0
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Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 4/11 clk: rockchip: add special cpu clock type
In reply to Heiko StübnerTo change the ARMCLK, Rockchip SoCs at least down to the Cortex-A8 RK2918 need special care. This includes reparenting the the armclk to a secondary parent for the duration of the parent rate-change and also the re-setting of tightly coupled children clocks.
Therefore define a special clock type for the cpuclk that attaches a notifier to the parent pll and handles the necessary steps in a clock notifier.
Also implemented are the necessary functions to handle the cpu clock of rk3188.
Signed-off-by Heiko Stuebner <[email protected]>
--- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-cpu.c | 434 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 18 ++ drivers/clk/rockchip/clk.h | 9 + 4 files changed, 462 insertions(+) create mode 100644 drivers/clk/rockchip/clk-cpu.c
drivers/clk/rockchip/Makefile +1 -0
@@ -5,3 +5,4 @@ obj-y += clk-rockchip.o obj-y += clk.o obj-y += clk-pll.o +obj-y += clk-cpu.o
drivers/clk/rockchip/clk-cpu.c new file +434 -0
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drivers/clk/rockchip/clk.c +18 -0
@@ -74,6 +74,24 @@ void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, } } +void __init rockchip_clk_register_armclk (unsigned int lookup_id, +const char *name,const char **parent_names, +unsigned int num_parents,void __iomem *reg_base, +struct device_node *np) +{ +struct clk *clk; + + clk =rockchip_clk_register_cpuclk (name, parent_names, num_parents, + reg_base, np, &clk_lock); +if (IS_ERR (clk)) { +pr_err ("%s: failed to register clock %s\n" , __func__, + name); +return ; + } + +rockchip_clk_add_lookup (clk, lookup_id); +} +void __init rockchip_clk_register_mux (struct rockchip_mux_clock *list,unsigned int nr_clk) {
drivers/clk/rockchip/clk.h +9 -0
@@ -103,6 +103,11 @@ struct clk *rockchip_clk_register_pll(struct rockchip_pll_clock *pll_clk, void __iomem *base, void __iomem *reg_lock, spinlock_t *lock); +struct clk *rockchip_clk_register_cpuclk (const char *name, +const char **parent_names,unsigned int num_parents, +void __iomem *reg_base,struct device_node *np, +spinlock_t *lock); +#define PNAME (x) static const char *x[] __initconst/**
@@ -222,5 +227,9 @@ void rockchip_clk_register_gate(struct rockchip_gate_clock *clk_list, unsigned int nr_clk);void rockchip_clk_register_plls (struct rockchip_pll_clock *pll_list,unsigned int nr_pll,void __iomem *reg_lock); +void rockchip_clk_register_armclk (unsigned int lookup_id, +const char *name,const char **parent_names, +unsigned int num_parents,void __iomem *reg_base, +struct device_node *np);#endif
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 5/11 clk: rockchip: add reset controller
In reply to Heiko StübnerAll Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller.
While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use.
Signed-off-by Heiko Stuebner <[email protected]>
--- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk.h | 14 +++++ drivers/clk/rockchip/softrst.c | 115 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 drivers/clk/rockchip/softrst.c
drivers/clk/rockchip/Makefile +1 -0
@@ -6,3 +6,4 @@ obj-y += clk-rockchip.o obj-y += clk.o obj-y += clk-pll.o obj-y += clk-cpu.o +obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
drivers/clk/rockchip/clk.h +14 -0
@@ -232,4 +232,18 @@ void rockchip_clk_register_armclk(unsigned int lookup_id, unsigned int num_parents, void __iomem *reg_base, struct device_node *np); +#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) + +#ifdef CONFIG_RESET_CONTROLLER +void rockchip_register_softrst (struct device_node *np, +unsigned int num_regs, +void __iomem *base,u8 flags); +#else +static inline void rockchip_register_softrst (struct device_node *np, +unsigned int num_regs, +void __iomem *base,u8 flags) +{ +} +#endif +#endif
drivers/clk/rockchip/softrst.c new file +115 -0
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Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 6/11 dt-bindings: add documentation for rk3188 clock and reset unit
In reply to Heiko StübnerThis add bindings documentation for the clock and reset unit found on rk3188 SoCs from Rockchip.
Signed-off-by Heiko Stuebner <[email protected]>
--- .../bindings/clock/rockchip,rk3188-cru.txt | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt new file +72 -0
@@ -0,0 +1,72 @@ +* Rockchip RK3188 Clock and Reset Unit + +The RK3188 clock controller generates and supplies clock to various controllers +within the SoC and also implements a reset controller for SoC peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3188-cru" +- reg: physical base address of the controller and length of memory mapped + region. The first element should be the cru register space and the second + element should be the address of the GRF_SOC_STATUS register providing the + pll lock status. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +- rockchip,armclk-divider-table: when the frequency of the APLL is changed + some core divider clocks also need to be updated. These divider clocks have + SoC specific divider clock output requirements for a specific APLL clock + speeds. When APLL clock rate is changed, these divider clocks are + reprogrammed with pre-determined values in order to maintain the SoC + specific divider clock outputs. This property lists the divider values + for these clocks for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + defined as + + cell #1: arm clock parent frequency + cell #2 ~ cell 3#: value of clock divider of core_peri and aclk_core. + +- #rockchip,armclk-cells: defines the number of cells in + rockchip,armclk-divider-table property. The value of this property depends on + the SoC type. For RK3188 SoCs it should be 3. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in dt-bindings/clock/rk3188-cru.h header and can be used +in device tree sources. + +External clocks: + +The basic input clock is generated outside the SoC. It is expected that it is +defined using standard clock bindings with a clock-output-name of "xin24m". + +Example: Clock controller node: + + cru: cru at 20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>, + <0x200080ac 0x4>; + + #clock-cells = <1>; + + #rockchip,armclk-cells = <3>; + rockchip,armclk-divider-table = <1608000 2 3>, + <1416000 2 3>, + <1200000 2 3>, + <1008000 2 3>, + < 816000 2 3>, + < 504000 1 3>, + < 312000 0 1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial at 10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART0>; + };
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 7/11 clk: rockchip: add clock driver for rk3188 clocks
In reply to Heiko StübnerThis adds a clock driver that handles the specific muxes, dividers and gates of rk3188 SoCs.
Clocks exported to the clock provider are currently limited to well known or measured ones.
Signed-off-by Heiko Stuebner <[email protected]>
--- drivers/clk/rockchip/Makefile | 2 + drivers/clk/rockchip/clk-rk3188.c | 457 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/rk3188-cru.h | 79 ++++++ 3 files changed, 538 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rk3188.c create mode 100644 include/dt-bindings/clock/rk3188-cru.h
drivers/clk/rockchip/Makefile +2 -0
@@ -7,3 +7,5 @@ obj-y += clk.o obj-y += clk-pll.o obj-y += clk-cpu.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o + +obj-y += clk-rk3188.o
drivers/clk/rockchip/clk-rk3188.c new file +457 -0
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include/dt-bindings/clock/rk3188-cru.h new file +79 -0
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Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 8/11 ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER
In reply to Heiko StübnerAll known Rockchip SoCs have a reset controller in their CRUs, so it's helpful to have the reset controller framework selected by default, only be deselected by the user in special cases.
Signed-off-by Heiko Stuebner <[email protected]>
--- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm/mach-rockchip/Kconfig +1 -0
@@ -2,6 +2,7 @@ config ARCH_ROCKCHIP bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7 select PINCTRL select PINCTRL_ROCKCHIP + select ARCH_HAS_RESET_CONTROLLER select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CACHE_L2X0
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 9/11 ARM: dts: rk3188: add cru node and update device clocks to use it
In reply to Heiko StübnerThis adds a node for the clock and reset unit on rk3188 SoCs and updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes.
As the clocks diverge a bit until rk3066 can catch up, the shared nodes between rk3066 and rk3188 get separated clocks-properties in the rk3188.dtsi.
Signed-off-by Heiko Stuebner <[email protected]>
--- arch/arm/boot/dts/rk3188.dtsi | 55 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-)
arch/arm/boot/dts/rk3188.dtsi +51 -4
@@ -15,6 +15,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3188-cru.h> #include "rk3xxx.dtsi" #include "rk3188-clocks.dtsi"
@@ -54,10 +55,12 @@ soc { global-timer at 1013c200 { interrupts = <GIC_PPI 11 0xf04>; + clocks = <&cru CORE_PERI>; }; local-timer at 1013c600 { interrupts = <GIC_PPI 13 0xf04>; + clocks = <&cru CORE_PERI>; }; sram: sram at 10080000 {
@@ -73,6 +76,50 @@ }; }; + uart0: serial at 10124000 { + clocks = <&cru SCLK_UART0>; + }; + + uart1: serial at 10126000 { + clocks = <&cru SCLK_UART1>; + }; + + uart2: serial at 20064000 { + clocks = <&cru SCLK_UART2>; + }; + + uart3: serial at 20068000 { + clocks = <&cru SCLK_UART3>; + }; + + dwmmc at 10214000 { + clocks = <&cru HCLK_MMC0>, <&cru SCLK_MMC0>; + clock-names = "biu", "ciu"; + }; + + dwmmc at 10218000 { + clocks = <&cru HCLK_MMC1>, <&cru SCLK_MMC1>; + clock-names = "biu", "ciu"; + }; + + cru: cru at 20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>, + <0x200080ac 0x4>; + + #clock-cells = <1>; + #reset-cells = <1>; + + #rockchip,armclk-cells = <3>; + rockchip,armclk-divider-table = <1608000 2 3>, + <1416000 2 3>, + <1200000 2 3>, + <1008000 2 3>, + < 816000 2 3>, + < 504000 1 3>, + < 312000 0 1>; + }; + pinctrl at 20008000 { compatible = "rockchip,rk3188-pinctrl"; reg = <0x20008000 0xa0>,
@@ -87,7 +134,7 @@ reg = <0x2000a000 0x100>, <0x20004064 0x8>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>;
@@ -100,7 +147,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>;
@@ -113,7 +160,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>;
@@ -126,7 +173,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>;
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 10/11 ARM: dts: rockchip: move rk3188 core input clocks into main dtsi
In reply to Heiko StübnerThe clock definitions get a lot shorter due to the soc clocks being handled by rk3188-cru and only the input clocks remaining. These can not simply live in the main rk3188.dtsi without affecting readability.
Signed-off-by Heiko Stuebner <[email protected]>
--- arch/arm/boot/dts/rk3188-clocks.dtsi | 18 ------------------ arch/arm/boot/dts/rk3188.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 18 deletions(-)
arch/arm/boot/dts/rk3188-clocks.dtsi +0 -18
@@ -19,24 +19,6 @@ #size-cells = <1>; ranges; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - dummy48m: dummy48m { compatible = "fixed-clock"; clock-frequency = <48000000>;
arch/arm/boot/dts/rk3188.dtsi +24 -0
@@ -52,6 +52,30 @@ }; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + }; + soc { global-timer at 1013c200 { interrupts = <GIC_PPI 11 0xf04>;
Signature · 1 line
1.9.0
Heiko Stübner
maintainerPATCH 11/11 ARM: dts: rockchip: remove the now obsolete rk3188-clocks.dtsi
In reply to Heiko StübnerThe clocks.dtsi does not contain any meaningful data anymore and can thus go away, as all clocks are now handled in the main dtsi.
Signed-off-by Heiko Stuebner <[email protected]>
--- arch/arm/boot/dts/rk3188-clocks.dtsi | 271 ----------------------------------- arch/arm/boot/dts/rk3188.dtsi | 1 - 2 files changed, 272 deletions(-) delete mode 100644 arch/arm/boot/dts/rk3188-clocks.dtsi
arch/arm/boot/dts/rk3188-clocks.dtsi deleted +0 -271
@@ -1,271 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk at 200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy150m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_aclk_core", - "reserved", "gate_i2s0", - "gate_i2s0_frac", "reserved", - "reserved", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk at 200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer3", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk at 200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk at 200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_timer2", "gate_timer4", - "gate_hsicphy", "gate_cif0_out", - "gate_timer5", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "reserved", - "gate_timer6", "gate_aclk_gpu_src"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk at 200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&dummy>, - <&clk_gates0 3>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "reserved", - "gate_aclk_intmem", "reserved", - "gate_hclk_imem1", "gate_hclk_imem0"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk at 200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk at 200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "reserved", "reserved", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk at 200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&dummy>, - <&dummy>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&dummy>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_otg1", - "gate_hclk_hsic", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "reserved", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk at 200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&dummy>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_aclk_gps"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk at 200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - }; - -};
arch/arm/boot/dts/rk3188.dtsi +0 -1
@@ -17,7 +17,6 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3188-cru.h> #include "rk3xxx.dtsi" -#include "rk3188-clocks.dtsi" / { compatible = "rockchip,rk3188";
Signature · 1 line
1.9.0