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FAILED: patch "[PATCH] drm/i915: Disable atomics in L3 for gen9" failed to apply to 5.11-stable tree

PATCH [email protected] 1 participant 1 message Mar 1, 2021

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Stable branch DRM drivers Intel i915
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The patch below does not apply to the 5.11-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 58586680ffadc37636120d9f59955aa5f7a32b7d Mon Sep 17 00:00:00 2001
From: Chris Wilson <[email protected]>
Date: Mon, 25 Jan 2021 22:01:52 +0000
Subject: [PATCH] drm/i915: Disable atomics in L3 for gen9

Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as the machine stops responding milliseconds after receipt of the reset request [GDRT]. By disabling the cached atomics, the hang do not occur and we presume the GPU would reset normally for similar hangs.

Sadly this is a shotgun approach, but since the impact is critical it is better to err on the safe side and work back from there.

Reported-by Jason Ekstrand <[email protected]>

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998

Signed-off-by Chris Wilson <[email protected]>
Cc Jason Ekstrand <[email protected]>
Cc Mika Kuoppala <[email protected]>
Cc Tvrtko Ursulin <[email protected]>
Cc Joonas Lahtinen <[email protected]>
Reviewed-by Jason Ekstrand <[email protected]>
Link https://patchwork.freedesktop.org/patch/msgid/[email protected]
Cc [email protected]
(cherry picked from commit b267c7ae0ad5b437b068f46919b17f85000154b4)
Signed-off-by Rodrigo Vivi <[email protected]>
drivers/gpu/drm/i915/gt/intel_workarounds.c +8 -0
index 3fdcd5ff71dd..ec366cf9ef56 100644
@@ -1834,6 +1834,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    GEN8_L3SQCREG4,
 			    GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+		/* Disable atomics in L3 to prevent unrecoverable hangs */
+		wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
+				 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+		wa_write_clr_set(wal, GEN8_L3SQCREG4,
+				 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+		wa_write_clr_set(wal, GEN9_SCRATCH1,
+				 EVICTION_PERF_FIX_ENABLE, 0);
 	}
 
 	if (IS_HASWELL(i915)) {
drivers/gpu/drm/i915/i915_reg.h +7 -0
index 598abd2f5b5f..7146cd0f3256 100644
@@ -8225,6 +8225,7 @@ enum {
 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
 #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
+#define  GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)

@@ -12107,6 +12108,12 @@ enum skl_power_gate {
 #define __GEN11_VCS2_MOCS0	0x10000
 #define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
 
+#define GEN9_SCRATCH_LNCF1		_MMIO(0xb008)
+#define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
+
+#define GEN9_SCRATCH1			_MMIO(0xb11c)
+#define   EVICTION_PERF_FIX_ENABLE	REG_BIT(8)
+
 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
 #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
 #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)