Enable miscellaneous hardware blocks to boot WPSS
Subsystems (7)
cover Enable miscellaneous hardware blocks to boot WPSS
This series enables miscellaneous hardware blocks to boot Wireless Processor Subsystem (WPSS) on SC7280 SoC.
[1] https://lore.kernel.org/patchwork/cover/1389010/
The series depends on ^^
Sibi Sankar (6):
soc: qcom: smem: Update max processor count
dt-bindings: mailbox: Add WPSS client index to IPCC
dt-bindings: reset: aoss: Add AOSS reset controller binding
dt-bindings: reset: pdc: Add PDC Global bindings
reset: qcom: Add PDC Global reset signals for WPSS
arm64: dts: qcom: sc7280: Add nodes to boot WPSS
.../devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 + .../devicetree/bindings/reset/qcom,pdc-global.yaml | 4 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++ drivers/reset/reset-qcom-pdc.c | 62 +++++++-- drivers/soc/qcom/smem.c | 2 +- include/dt-bindings/mailbox/qcom-ipcc.h | 1 + include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 + 7 files changed, 207 insertions(+), 12 deletions(-)
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PATCH 1/6 soc: qcom: smem: Update max processor count
Update max processor count to reflect the number of co-processors on SC7280 SoCs.
--- drivers/soc/qcom/smem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/soc/qcom/smem.c +1 -1
@@ -84,7 +84,7 @@#define SMEM_GLOBAL_HOST 0xfffe/* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 11 +#define SMEM_HOST_COUNT 14/** * struct smem_proc_comm - proc_comm communication struct (legacy)
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Re: [PATCH 1/6] soc: qcom: smem: Update max processor count
Quoting Sibi Sankar (2021-03-08 21:51:46)
Quoted 5 lines
Update max processor count to reflect the number of co-processors on SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
PATCH 2/6 dt-bindings: mailbox: Add WPSS client index to IPCC
In reply to Sibi SankarAdd WPSS remote processor client index to Inter-Processor Communication Controller (IPCC) block.
--- include/dt-bindings/mailbox/qcom-ipcc.h | 1 + 1 file changed, 1 insertion(+)
include/dt-bindings/mailbox/qcom-ipcc.h +1 -0
@@ -29,5 +29,6 @@#define IPCC_CLIENT_PCIE1 14#define IPCC_CLIENT_PCIE2 15#define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_WPSS 24#endif
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Re: [PATCH 2/6] dt-bindings: mailbox: Add WPSS client index to IPCC
Quoting Sibi Sankar (2021-03-08 21:51:47)
Quoted 5 lines
Add WPSS remote processor client index to Inter-Processor Communication Controller (IPCC) block.
Signed-off-by Sibi Sankar <[email protected]>---
Re: [PATCH 2/6] dt-bindings: mailbox: Add WPSS client index to IPCC
In reply to Sibi SankarQuoted 8 lines · Sibi Sankar
Add WPSS remote processor client index to Inter-Processor Communication Controller (IPCC) block.
Signed-off-by Sibi Sankar <[email protected]>--- include/dt-bindings/mailbox/qcom-ipcc.h | 1 + 1 file changed, 1 insertion(+)
PATCH 3/6 dt-bindings: reset: aoss: Add AOSS reset controller binding
In reply to Sibi SankarAdd AOSS reset controller bindings for SC7280 SoCs.
--- Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml +5 -0
@@ -21,6 +21,11 @@ properties: - const: "qcom,sc7180-aoss-cc" - const: "qcom,sdm845-aoss-cc" + - description: on SC7280 SoCs the following compatibles must be specified + items: + - const: "qcom,sc7280-aoss-cc" + - const: "qcom,sdm845-aoss-cc" + - description: on SDM845 SoCs the following compatibles must be specified items: - const: "qcom,sdm845-aoss-cc"
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Re: [PATCH 3/6] dt-bindings: reset: aoss: Add AOSS reset controller binding
Quoting Sibi Sankar (2021-03-08 21:51:48)
Quoted 4 lines
Add AOSS reset controller bindings for SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
Re: [PATCH 3/6] dt-bindings: reset: aoss: Add AOSS reset controller binding
In reply to Sibi SankarQuoted 7 lines · Sibi Sankar
Add AOSS reset controller bindings for SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 +++++ 1 file changed, 5 insertions(+)
PATCH 4/6 dt-bindings: reset: pdc: Add PDC Global bindings
In reply to Sibi SankarAdd PDC Global reset controller bindings for SC7280 SoCs.
--- Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++ include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 ++ 2 files changed, 6 insertions(+)
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +4 -0
@@ -21,6 +21,10 @@ properties: - const: "qcom,sc7180-pdc-global" - const: "qcom,sdm845-pdc-global" + - description: on SC7280 SoCs the following compatibles must be specified + items: + - const: "qcom,sc7280-pdc-global" + - description: on SDM845 SoCs the following compatibles must be specified items: - const: "qcom,sdm845-pdc-global"
include/dt-bindings/reset/qcom,sdm845-pdc.h +2 -0
@@ -16,5 +16,7 @@#define PDC_DISPLAY_SYNC_RESET 7#define PDC_COMPUTE_SYNC_RESET 8#define PDC_MODEM_SYNC_RESET 9 +#define PDC_WLAN_RF_SYNC_RESET 10 +#define PDC_WPSS_SYNC_RESET 11#endif
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Re: [PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings
Quoting Sibi Sankar (2021-03-08 21:51:49)
Quoted 13 lines
Add PDC Global reset controller bindings for SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++ include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 ++ 2 files changed, 6 insertions(+)Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +0
-0
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml properties: · line 26
Quoted 6 lines
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +3
-0@@ -21,6 +21,10 @@ properties: - const: "qcom,sc7180-pdc-global" - const: "qcom,sdm845-pdc-global" + - description: on SC7280 SoCs the following compatibles must be specified + items: + - const: "qcom,sc7280-pdc-global"
Somehow this one can drop sdm845-pdc-global but aoss-cc can't?
Quoted 4 lines
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +1
-0+ - description: on SDM845 SoCs the following compatibles must be specified items: - const: "qcom,sdm845-pdc-global"
Re: [PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings
Quoted 17 lines · Stephen Boyd
Quoting Sibi Sankar (2021-03-08 21:51:49)
Quoted 16 lines
Add PDC Global reset controller bindings for SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++ include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 ++ 2 files changed, 6 insertions(+)Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +0
-0@@ -21,6 +21,10 @@ properties: - const: "qcom,sc7180-pdc-global" - const: "qcom,sdm845-pdc-global"
Quoted 6 lines
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml properties: · line 26
Quoted 4 lines
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +1
-0+ - description: on SC7280 SoCs the following compatibles must bespecified
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +2
-0+ items: + - const: "qcom,sc7280-pdc-global"Somehow this one can drop sdm845-pdc-global but aoss-cc can't?
I missed replying to ^^. aoss-cc
reset is identical to that found
on SDM845 SoC but the pdc-reset
differs in the number of resets
and offset within the pdc register
space.
Quoted 6 lines
Quoted 6 lines
+
- description: on SDM845 SoCs the following compatibles must be
specified
items:
- const: "qcom,sdm845-pdc-global"
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings
In reply to Sibi SankarQuoted 8 lines · Sibi Sankar
Add PDC Global reset controller bindings for SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++ include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 ++ 2 files changed, 6 insertions(+)
PATCH 5/6 reset: qcom: Add PDC Global reset signals for WPSS
In reply to Sibi SankarAdd PDC Global reset signals for Wireless Processor Subsystem (WPSS) on SC7280 SoCs.
--- drivers/reset/reset-qcom-pdc.c | 62 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 11 deletions(-)
drivers/reset/reset-qcom-pdc.c +51 -11
@@ -11,18 +11,26 @@#include <dt-bindings/reset/qcom,sdm845-pdc.h> -#define RPMH_PDC_SYNC_RESET 0x100 +#define RPMH_SDM845_PDC_SYNC_RESET 0x100 +#define RPMH_SC7280_PDC_SYNC_RESET 0x1000struct qcom_pdc_reset_map {u8 bit; }; +struct qcom_pdc_reset_desc { +const struct qcom_pdc_reset_map *resets; +unsigned int offset; +size_t num_resets; +}; +struct qcom_pdc_reset_data {struct reset_controller_dev rcdev;struct regmap *regmap; +const struct qcom_pdc_reset_desc *desc; }; -static const struct regmap_config sdm845_pdc_regmap_config = { +static const struct regmap_config pdc_regmap_config = { .name ="pdc-reset" , .reg_bits =32 , .reg_stride =4 ,
@@ -44,6 +52,33 @@ static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = { [PDC_MODEM_SYNC_RESET] = {9}, }; +static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = { + .resets = sdm845_pdc_resets, + .offset =RPMH_SDM845_PDC_SYNC_RESET , + .num_resets =ARRAY_SIZE (sdm845_pdc_resets), +}; + +static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = { + [PDC_APPS_SYNC_RESET ] = {0 }, + [PDC_SP_SYNC_RESET ] = {1 }, + [PDC_AUDIO_SYNC_RESET ] = {2 }, + [PDC_SENSORS_SYNC_RESET ] = {3 }, + [PDC_AOP_SYNC_RESET ] = {4 }, + [PDC_DEBUG_SYNC_RESET ] = {5 }, + [PDC_GPU_SYNC_RESET ] = {6 }, + [PDC_DISPLAY_SYNC_RESET ] = {7 }, + [PDC_COMPUTE_SYNC_RESET ] = {8 }, + [PDC_MODEM_SYNC_RESET ] = {9 }, + [PDC_WLAN_RF_SYNC_RESET ] = {10 }, + [PDC_WPSS_SYNC_RESET ] = {11 }, +}; + +static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = { + .resets = sc7280_pdc_resets, + .offset =RPMH_SC7280_PDC_SYNC_RESET , + .num_resets =ARRAY_SIZE (sc7280_pdc_resets), +}; +static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data (struct reset_controller_dev *rcdev) {
@@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev, unsigned long idx) {struct qcom_pdc_reset_data *data =to_qcom_pdc_reset_data (rcdev); +const struct qcom_pdc_reset_map *map = &data->desc->resets[idx]; -return regmap_update_bits (data->regmap,RPMH_PDC_SYNC_RESET , -BIT (sdm845_pdc_resets[idx].bit), -BIT (sdm845_pdc_resets[idx].bit)); +return regmap_update_bits (data->regmap, data->desc->offset,BIT (map->bit),BIT (map->bit)); }static int qcom_pdc_control_deassert (struct reset_controller_dev *rcdev,unsigned long idx) {struct qcom_pdc_reset_data *data =to_qcom_pdc_reset_data (rcdev); +const struct qcom_pdc_reset_map *map = &data->desc->resets[idx]; -return regmap_update_bits (data->regmap,RPMH_PDC_SYNC_RESET , -BIT (sdm845_pdc_resets[idx].bit),0 ); +return regmap_update_bits (data->regmap, data->desc->offset,BIT (map->bit),0 ); }static const struct reset_control_ops qcom_pdc_reset_ops = {
@@ -76,22 +110,27 @@ static const struct reset_control_ops qcom_pdc_reset_ops = {static int qcom_pdc_reset_probe (struct platform_device *pdev) { +const struct qcom_pdc_reset_desc *desc;struct qcom_pdc_reset_data *data;struct device *dev = &pdev->dev;void __iomem *base;struct resource *res; + desc =device_get_match_data (&pdev->dev); +if (!desc) +return -EINVAL ; + data =devm_kzalloc (dev,sizeof (*data),GFP_KERNEL );if (!data)return -ENOMEM ; + data->desc = desc; res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); base =devm_ioremap_resource (dev, res);if (IS_ERR (base))return PTR_ERR (base); - data->regmap =devm_regmap_init_mmio (dev, base, - &sdm845_pdc_regmap_config); + data->regmap =devm_regmap_init_mmio (dev, base, &pdc_regmap_config);if (IS_ERR (data->regmap)) {dev_err (dev,"Unable to initialize regmap\n" );return PTR_ERR (data->regmap);
@@ -99,14 +138,15 @@ static int qcom_pdc_reset_probe(struct platform_device *pdev) data->rcdev.owner =THIS_MODULE ; data->rcdev.ops = &qcom_pdc_reset_ops; - data->rcdev.nr_resets =ARRAY_SIZE (sdm845_pdc_resets); + data->rcdev.nr_resets = desc->num_resets; data->rcdev.of_node = dev->of_node;return devm_reset_controller_register (dev, &data->rcdev); }static const struct of_device_id qcom_pdc_reset_of_match[] = { - { .compatible ="qcom,sdm845-pdc-global" }, + { .compatible ="qcom,sc7280-pdc-global" , .data = &sc7280_pdc_reset_desc }, + { .compatible ="qcom,sdm845-pdc-global" , .data = &sdm845_pdc_reset_desc }, {} };MODULE_DEVICE_TABLE (of, qcom_pdc_reset_of_match);
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Re: [PATCH 5/6] reset: qcom: Add PDC Global reset signals for WPSS
Quoting Sibi Sankar (2021-03-08 21:51:50)
Quoted 18 lines
Add PDC Global reset signals for Wireless Processor Subsystem (WPSS) on SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- drivers/reset/reset-qcom-pdc.c | 62 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 11 deletions(-)drivers/reset/reset-qcom-pdc.c +1
-1@@ -11,18 +11,26 @@#include <dt-bindings/reset/qcom,sdm845-pdc.h> -#define RPMH_PDC_SYNC_RESET 0x100 +#define RPMH_SDM845_PDC_SYNC_RESET 0x100
drivers/reset/reset-qcom-pdc.c line 24
Quoted 10 lines
drivers/reset/reset-qcom-pdc.c +5
-0+#define RPMH_SC7280_PDC_SYNC_RESET 0x1000struct qcom_pdc_reset_map {u8 bit; }; +struct qcom_pdc_reset_desc { +const struct qcom_pdc_reset_map *resets; +unsigned int offset; +size_t num_resets;
Please put num_resets next to resets and move offset before or after the block. That way we know that resets and num_resets are related because they're right next to each other.
Quoted 13 lines
drivers/reset/reset-qcom-pdc.c +4
-1+}; +struct qcom_pdc_reset_data {struct reset_controller_dev rcdev;struct regmap *regmap; +const struct qcom_pdc_reset_desc *desc; }; -static const struct regmap_config sdm845_pdc_regmap_config = { +static const struct regmap_config pdc_regmap_config = { .name ="pdc-reset" , .reg_bits =32 , .reg_stride =4 ,
PATCH 6/6 arm64: dts: qcom: sc7280: Add nodes to boot WPSS
In reply to Sibi SankarAdd miscellaneous nodes to boot the Wireless Processor Subsystem on SC7280 SoCs.
---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^
arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +143 -0
@@ -10,6 +10,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,sdm845-aoss.h> +#include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {
@@ -50,6 +52,11 @@ no-map; }; + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + cpucp_mem: memory@80b00000 { no-map; reg = <0x0 0x80b00000 0x0 0x100000>;
@@ -244,12 +251,131 @@ reg = <0 0x80000000 0 0>; }; + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + firmware { scm { compatible = "qcom,scm-sc7280", "qcom,scm"; }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -315,6 +441,11 @@ }; }; + tcsr_mutex_regs: syscon@1f40000 { + compatible = "syscon"; + reg = <0 0x01f40000 0 0x40000>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;
@@ -328,6 +459,18 @@ interrupt-controller; }; + pdc_reset: reset-controller@b5e0000 { + compatible = "qcom,sc7280-pdc-global"; + reg = <0 0x0b5e0000 0 0x20000>; + #reset-cells = <1>; + }; + + aoss_reset: reset-controller@c2a0000 { + compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; + reg = <0 0x0c2a0000 0 0x31000>; + #reset-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,
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Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS
Quoting Sibi Sankar (2021-03-08 21:51:51)
Quoted 1 line
Add miscellaneous nodes to boot the Wireless Processor Subsystem on
Maybe add (WPSS) after the name so we know they're related.
Quoted 16 lines
SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0
arch/arm64/boot/dts/qcom/sc7280.dtsi line 258
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0@@ -244,12 +251,131 @@ reg = <0 0x80000000 0 0>; }; + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + };
Is this node in the right place? I think the node above it is 'memory'? In which case 'hwlock' comes before 'memory' alphabetically.
Quoted 70 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +64
-0+ + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + firmware { scm { compatible = "qcom,scm-sc7280", "qcom,scm"; }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; +
arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel";
Do these names need to have 'master' and 'slave' in them? We're trying to avoid these terms. See Documentation/process/coding-style.rst Section 4 naming.
Quoted 16 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0+ interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +
Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS
Quoted 24 lines · Stephen Boyd
Quoting Sibi Sankar (2021-03-08 21:51:51)
Quoted 1 line
Add miscellaneous nodes to boot the Wireless Processor Subsystem on
Maybe add (WPSS) after the name so we know they're related.
Quoted 19 lines
SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0@@ -244,12 +251,131 @@ reg = <0 0x80000000 0 0>; };
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 258
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + };Is this node in the right place? I think the node above it is 'memory'? In which case 'hwlock' comes before 'memory' alphabetically.
Thanks for spotting this, as it's no longer acceptable to have a standalone "syscon" node I was asked to rewrite the binding for this a few months ago. So the tcsr_mutex should now be represented with a reg under /soc.
Quoted 76 lines
Quoted 76 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +70
-0+ + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + firmware { scm { compatible = "qcom,scm-sc7280", "qcom,scm"; }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>;
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel";Do these names need to have 'master' and 'slave' in them? We're trying to avoid these terms. See
Documentation/process/coding-style.rstSection 4 naming.
They need to match the naming in the firmware, but I would welcome a future change to something in line with the coding style and simply more descriptive.
Regards,
Bjorn
Quoted 16 lines
Quoted 16 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0+ interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +
Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS
Quoting Bjorn Andersson (2021-03-13 20:16:39)
Quoted 36 lines · Stephen Boyd
Quoted 25 lines
Quoting Sibi Sankar (2021-03-08 21:51:51)
Quoted 1 line
Add miscellaneous nodes to boot the Wireless Processor Subsystem on
Maybe add (WPSS) after the name so we know they're related.
Quoted 19 lines
SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0@@ -244,12 +251,131 @@ reg = <0 0x80000000 0 0>; };Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 258
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + };Is this node in the right place? I think the node above it is 'memory'? In which case 'hwlock' comes before 'memory' alphabetically.
Quoted 4 lines
Thanks for spotting this, as it's no longer acceptable to have a standalone "syscon" node I was asked to rewrite the binding for this a few months ago. So the
tcsr_mutexshould now be represented with a reg under /soc.
Oh nice, I wasn't aware.
Quoted 29 lines
Quoted 19 lines
Quoted 19 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +19
-0+ #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>;Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel";Do these names need to have 'master' and 'slave' in them? We're trying to avoid these terms. See
Documentation/process/coding-style.rstSection 4 naming.
Quoted 4 lines
They need to match the naming in the firmware, but I would welcome a future change to something in line with the coding style and simply more descriptive.
Sibi can this be done? I think it's still pretty early days for the firmware so hopefully the terms can be replaced with something different.
Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS
Quoted 73 lines · Stephen Boyd
Quoting Bjorn Andersson (2021-03-13 20:16:39)
Quoted 36 lines · Stephen Boyd
Quoted 25 lines
Quoting Sibi Sankar (2021-03-08 21:51:51)
Quoted 1 line
Add miscellaneous nodes to boot the Wireless Processor Subsystem on
Maybe add (WPSS) after the name so we know they're related.
Quoted 19 lines
SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0@@ -244,12 +251,131 @@ reg = <0 0x80000000 0 0>; };Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 258
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + };Is this node in the right place? I think the node above it is 'memory'? In which case 'hwlock' comes before 'memory' alphabetically.
Quoted 4 lines
Thanks for spotting this, as it's no longer acceptable to have a standalone "syscon" node I was asked to rewrite the binding for this a few months ago. So the
tcsr_mutexshould now be represented with a reg under /soc.Oh nice, I wasn't aware.
Quoted 29 lines
Quoted 28 lines
Quoted 13 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +13
-0+ #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; +arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel";Do these names need to have 'master' and 'slave' in them? We're trying to avoid these terms. See
Documentation/process/coding-style.rstSection 4 naming.
Quoted 8 lines
Quoted 4 lines
They need to match the naming in the firmware, but I would welcome a future change to something in line with the coding style and simply more descriptive.
Sibi can this be done? I think it's still pretty early days for the firmware so hopefully the terms can be replaced with something different.
I'll discuss the ask with the modem fw team and
get back.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS
Quoted 79 lines · Sibi Sankar
Quoted 78 lines · Stephen Boyd
Quoting Bjorn Andersson (2021-03-13 20:16:39)
Quoted 36 lines · Stephen Boyd
Quoted 25 lines
Quoting Sibi Sankar (2021-03-08 21:51:51)
Quoted 1 line
Add miscellaneous nodes to boot the Wireless Processor Subsystem on
Maybe add (WPSS) after the name so we know they're related.
Quoted 19 lines
SC7280 SoCs.
Signed-off-by Sibi Sankar <[email protected]>---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0@@ -244,12 +251,131 @@ reg = <0 0x80000000 0 0>; };Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 258
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + };Is this node in the right place? I think the node above it is 'memory'? In which case 'hwlock' comes before 'memory' alphabetically.
Quoted 4 lines
Thanks for spotting this, as it's no longer acceptable to have a standalone "syscon" node I was asked to rewrite the binding for this a few months ago. So the
tcsr_mutexshould now be represented with a reg under /soc.Oh nice, I wasn't aware.
Quoted 33 lines
Quoted 19 lines
Quoted 19 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +19
-0+ #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>;Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 338
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel";Do these names need to have 'master' and 'slave' in them? We're trying to avoid these terms. See
Documentation/process/coding-style.rstSection 4 naming.They need to match the naming in the firmware, but I would welcome a future change to something in line with the coding style and simply more descriptive.
Quoted 6 lines
Quoted 3 lines
Sibi can this be done? I think it's still pretty early days for the firmware so hopefully the terms can be replaced with something different.
I'll discuss the ask with the modem fw team and
get back.
Sorry for the delayed response. Looks
like it's something Qualcomm wouldn't
want to do mid-project since a number
of the fw images are re-used across
platforms. But this is something that
will be taken up on newer SoCs.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.