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Add Support for DLB v2.5

PATCH Superseded Timothy McDaniel 4 participants 174 messages Mar 16, 2021 – May 4, 2021 Arm/Amlogic Meson SoC support Page 4 of 4

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#138 lore raw

PATCH v5 20/26 event/dlb2: use new implementation of resource header

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

A temporary version of dlb_resource.h (dlb_resource_new.h) was used by the previous commits in this patch series. Merge the two files now that DLB v2.5 support has been fully added to dlb_resource.c.

---
 drivers/event/dlb2/pf/base/dlb2_osdep.h       |  2 -
 drivers/event/dlb2/pf/base/dlb2_resource.h    | 36 +++++++++
 .../event/dlb2/pf/base/dlb2_resource_new.c    |  2 +-
 .../event/dlb2/pf/base/dlb2_resource_new.h    | 73 -------------------
 drivers/event/dlb2/pf/dlb2_main.c             |  2 +-
 drivers/event/dlb2/pf/dlb2_pf.c               |  2 +-
 6 files changed, 39 insertions(+), 78 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.h
drivers/event/dlb2/pf/base/dlb2_osdep.h +0 -2
index 3b0ca84ba..cffe22f3c 100644
@@ -17,8 +17,6 @@
 #include <rte_spinlock.h>
 #include "../dlb2_main.h"
 
-/* TEMPORARY inclusion of both headers for merge */
-#include "dlb2_resource_new.h"
 #include "dlb2_resource.h"
 
 #include "../../dlb2_log.h"
drivers/event/dlb2/pf/base/dlb2_resource.h +36 -0
index 00a0b6b57..684049cd6 100644
@@ -8,6 +8,42 @@
 #include "dlb2_user.h"
 #include "dlb2_osdep_types.h"
 
+/**
+ * dlb2_resource_init() - initialize the device
+ * @hw: pointer to struct dlb2_hw.
+ * @ver: device version.
+ *
+ * This function initializes the device's software state (pointed to by the hw
+ * argument) and programs global scheduling QoS registers. This function should
+ * be called during driver initialization.
+ *
+ * The dlb2_hw struct must be unique per DLB 2.0 device and persist until the
+ * device is reset.
+ *
+ * Return:
+ * Returns 0 upon success, <0 otherwise.
+ */
+int dlb2_resource_init(struct dlb2_hw *hw, enum dlb2_hw_ver ver);
+
+/**
+ * dlb2_clr_pmcsr_disable() - power on bulk of DLB 2.0 logic
+ * @hw: dlb2_hw handle for a particular device.
+ * @ver: device version.
+ *
+ * Clearing the PMCSR must be done at initialization to make the device fully
+ * operational.
+ */
+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw, enum dlb2_hw_ver ver);
+
+/**
+ * dlb2_resource_free() - free device state memory
+ * @hw: dlb2_hw handle for a particular device.
+ *
+ * This function frees software state pointed to by dlb2_hw. This function
+ * should be called when resetting the device or unloading the driver.
+ */
+void dlb2_resource_free(struct dlb2_hw *hw);
+
 /**
  * dlb2_resource_reset() - reset in-use resources to their initial state
  * @hw: dlb2_hw handle for a particular device.
drivers/event/dlb2/pf/base/dlb2_resource_new.c +1 -1
index 927b65568..2f66b2c71 100644
@@ -11,7 +11,7 @@
 #include "dlb2_osdep_bitmap.h"
 #include "dlb2_osdep_types.h"
 #include "dlb2_regs_new.h"
-#include "dlb2_resource_new.h" /* TEMP FOR UPSTREAMPATCHES */
+#include "dlb2_resource.h"
 
 #include "../../dlb2_priv.h"
 #include "../../dlb2_inline_fns.h"
drivers/event/dlb2/pf/base/dlb2_resource_new.h deleted +0 -73

73 lines not on this page · raw message

drivers/event/dlb2/pf/dlb2_main.c +1 -1
index 5c0640b3c..bac07f097 100644
@@ -17,7 +17,7 @@
 
 #include "base/dlb2_regs_new.h"
 #include "base/dlb2_hw_types_new.h"
-#include "base/dlb2_resource_new.h"
+#include "base/dlb2_resource.h"
 #include "base/dlb2_osdep.h"
 #include "dlb2_main.h"
 #include "../dlb2_user.h"
drivers/event/dlb2/pf/dlb2_pf.c +1 -1
index 1e815f20d..880964a29 100644
@@ -40,7 +40,7 @@
 #include "dlb2_main.h"
 #include "base/dlb2_hw_types_new.h"
 #include "base/dlb2_osdep.h"
-#include "base/dlb2_resource_new.h"
+#include "base/dlb2_resource.h"
 
 static const char *event_dlb2_pf_name = RTE_STR(EVDEV_DLB2_NAME_PMD);
 
Signature · 1 line
2.23.0
#139 lore raw

PATCH v5 21/26 event/dlb2: use new implementation of resource file

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

The file dlb_resource_new.c now contains all of the low level functions required to support both DLB v2.0 and DLB v2.5, and the original file (dlb_resource.c) was removed in the previous commit, so rename dlb_resource_new.c to dlb_resource.c, and update the meson build file so that the new file is built.

---
 drivers/event/dlb2/meson.build                |    1 -
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 6205 +++++++++++++++-
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 6235 -----------------
 3 files changed, 6203 insertions(+), 6238 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.c
drivers/event/dlb2/meson.build +0 -1
index 0c848161e..f963589fd 100644
@@ -15,7 +15,6 @@ sources = files(
         'pf/dlb2_main.c',
         'pf/dlb2_pf.c',
         'pf/base/dlb2_resource.c',
-        'pf/base/dlb2_resource_new.c',
         'rte_pmd_dlb2.c',
         'dlb2_selftest.c',
 )
drivers/event/dlb2/pf/base/dlb2_resource.c +6203 -2

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drivers/event/dlb2/pf/base/dlb2_resource_new.c deleted +0 -6235

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Signature · 1 line
2.23.0

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#140 lore raw

PATCH v5 22/26 event/dlb2: use new implementation of HW types header

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

As support for DLB v2.5 was added, modifications were made to dlb_hw_types_new.h, but the old file needed to be preserved during the port in order to meet the requirement that individual patches in a series each compile successfully. Since the DLB v2.5 support is completely integrated, it is now safe to remove the old (original) file, as well as the DLB2_USE_NEW_HEADERS define that was used to control which version of the file was to be included in certain source files.
It is now safe to rename the new file, and use it unconditionally in all DLB source files.

---
 drivers/event/dlb2/pf/base/dlb2_hw_types.h    |  38 +-
 .../event/dlb2/pf/base/dlb2_hw_types_new.h    | 357 ------------------
 drivers/event/dlb2/pf/base/dlb2_resource.c    |   4 +-
 drivers/event/dlb2/pf/dlb2_main.c             |   4 +-
 drivers/event/dlb2/pf/dlb2_main.h             |   4 -
 drivers/event/dlb2/pf/dlb2_pf.c               |   4 +-
 6 files changed, 33 insertions(+), 378 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types_new.h
drivers/event/dlb2/pf/base/dlb2_hw_types.h +30 -8
index b007e1674..4a6037775 100644
@@ -2,14 +2,21 @@
  * Copyright(c) 2016-2020 Intel Corporation
  */
 
-#ifndef __DLB2_HW_TYPES_H
-#define __DLB2_HW_TYPES_H
+#ifndef __DLB2_HW_TYPES_NEW_H
+#define __DLB2_HW_TYPES_NEW_H
 
 #include "../../dlb2_priv.h"
 #include "dlb2_user.h"
 
 #include "dlb2_osdep_list.h"
 #include "dlb2_osdep_types.h"
+#include "dlb2_regs_new.h"
+
+#define DLB2_BITS_SET(x, val, mask)	(x = ((x) & ~(mask))     \
+				 | (((val) << (mask##_LOC)) & (mask)))
+#define DLB2_BITS_CLR(x, mask)	(x &= ~(mask))
+#define DLB2_BIT_SET(x, mask)	((x) |= (mask))
+#define DLB2_BITS_GET(x, mask)	(((x) & (mask)) >> (mask##_LOC))
 
 #define DLB2_MAX_NUM_VDEVS			16
 #define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS	2
@@ -141,7 +148,7 @@ struct dlb2_dir_pq_pair {
 };
 
 enum dlb2_qid_map_state {
-	/* The slot doesn't contain a valid queue mapping */
+	/* The slot does not contain a valid queue mapping */
 	DLB2_QUEUE_UNMAPPED,
 	/* The slot contains a valid queue mapping */
 	DLB2_QUEUE_MAPPED,
@@ -174,6 +181,7 @@ struct dlb2_ldb_port {
 	u32 hist_list_entry_base;
 	u32 hist_list_entry_limit;
 	u32 ref_cnt;
+	u8 cq_depth;
 	u8 init_tkn_cnt;
 	u8 num_pending_removals;
 	u8 num_mappings;
@@ -245,8 +253,15 @@ struct dlb2_hw_domain {
 	u32 avail_hist_list_entries;
 	u32 hist_list_entry_base;
 	u32 hist_list_entry_offset;
-	u32 num_ldb_credits;
-	u32 num_dir_credits;
+	union {
+		struct {
+			u32 num_ldb_credits;
+			u32 num_dir_credits;
+		};
+		struct {
+			u32 num_credits;
+		};
+	};
 	u32 num_avail_aqed_entries;
 	u32 num_used_aqed_entries;
 	struct dlb2_resource_id id;
@@ -269,8 +284,15 @@ struct dlb2_function_resources {
 	u32 num_avail_ldb_queues;
 	u32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
 	u32 num_avail_dir_pq_pairs;
-	u32 num_avail_qed_entries;
-	u32 num_avail_dqed_entries;
+	union {
+		struct {
+			u32 num_avail_qed_entries;
+			u32 num_avail_dqed_entries;
+		};
+		struct {
+			u32 num_avail_entries;
+		};
+	};
 	u32 num_avail_aqed_entries;
 	u8 locked; /* (VDEV only) */
 };
@@ -332,4 +354,4 @@ struct dlb2_hw {
 	unsigned int pasid[DLB2_MAX_NUM_VDEVS];
 };
 
-#endif /* __DLB2_HW_TYPES_H */
+#endif /* __DLB2_HW_TYPES_NEW_H */
drivers/event/dlb2/pf/base/dlb2_hw_types_new.h deleted +0 -357

357 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource.c +1 -3
index 2f66b2c71..54b0207db 100644
@@ -2,11 +2,9 @@
  * Copyright(c) 2016-2020 Intel Corporation
  */
 
-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
-
 #include "dlb2_user.h"
 
-#include "dlb2_hw_types_new.h"
+#include "dlb2_hw_types.h"
 #include "dlb2_osdep.h"
 #include "dlb2_osdep_bitmap.h"
 #include "dlb2_osdep_types.h"
drivers/event/dlb2/pf/dlb2_main.c +1 -3
index bac07f097..1f6ccf8e4 100644
@@ -13,10 +13,8 @@
 #include <rte_malloc.h>
 #include <rte_errno.h>
 
-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
-
 #include "base/dlb2_regs_new.h"
-#include "base/dlb2_hw_types_new.h"
+#include "base/dlb2_hw_types.h"
 #include "base/dlb2_resource.h"
 #include "base/dlb2_osdep.h"
 #include "dlb2_main.h"
drivers/event/dlb2/pf/dlb2_main.h +0 -4
index 892298d7a..9eeda482a 100644
@@ -12,11 +12,7 @@
 #include <rte_bus_pci.h>
 #include <rte_eal_paging.h>
 
-#ifdef DLB2_USE_NEW_HEADERS
-#include "base/dlb2_hw_types_new.h"
-#else
 #include "base/dlb2_hw_types.h"
-#endif
 #include "../dlb2_user.h"
 
 #define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5
drivers/event/dlb2/pf/dlb2_pf.c +1 -3
index 880964a29..f57dc1584 100644
@@ -32,13 +32,11 @@
 #include <rte_memory.h>
 #include <rte_string_fns.h>
 
-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
-
 #include "../dlb2_priv.h"
 #include "../dlb2_iface.h"
 #include "../dlb2_inline_fns.h"
 #include "dlb2_main.h"
-#include "base/dlb2_hw_types_new.h"
+#include "base/dlb2_hw_types.h"
 #include "base/dlb2_osdep.h"
 #include "base/dlb2_resource.h"
 
Signature · 1 line
2.23.0
#141 lore raw

PATCH v5 23/26 event/dlb2: use new combined register map

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

All references to the old register map have been removed, so it is safe to rename the new combined file that supports both DLB v2.0 and DLB v2.5. Also fixed all places where this file is included.

---
 drivers/event/dlb2/pf/base/dlb2_hw_types.h |    2 +-
 drivers/event/dlb2/pf/base/dlb2_regs.h     | 5955 +++++++++++++-------
 drivers/event/dlb2/pf/base/dlb2_regs_new.h | 4304 --------------
 drivers/event/dlb2/pf/base/dlb2_resource.c |    2 +-
 drivers/event/dlb2/pf/dlb2_main.c          |    2 +-
 5 files changed, 3869 insertions(+), 6396 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_regs_new.h
drivers/event/dlb2/pf/base/dlb2_hw_types.h +1 -1
index 4a6037775..6b8fee341 100644
@@ -10,7 +10,7 @@
 
 #include "dlb2_osdep_list.h"
 #include "dlb2_osdep_types.h"
-#include "dlb2_regs_new.h"
+#include "dlb2_regs.h"
 
 #define DLB2_BITS_SET(x, val, mask)	(x = ((x) & ~(mask))     \
 				 | (((val) << (mask##_LOC)) & (mask)))
drivers/event/dlb2/pf/base/dlb2_regs.h +3866 -2089

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drivers/event/dlb2/pf/base/dlb2_regs_new.h deleted +0 -4304

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drivers/event/dlb2/pf/base/dlb2_resource.c +1 -1
index 54b0207db..3661b940c 100644

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drivers/event/dlb2/pf/dlb2_main.c +1 -1
index 1f6ccf8e4..b6ec85b47 100644

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Signature · 1 line
2.23.0

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#142 lore raw

PATCH v5 24/26 event/dlb2: update xstats for v2.5

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

Add DLB v2.5 specific information to xstats, such as metrics for the new credit scheme.

---
 drivers/event/dlb2/dlb2_xstats.c | 41 ++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)
drivers/event/dlb2/dlb2_xstats.c +37 -4
index b62e62060..d4c8d9903 100644
@@ -9,6 +9,7 @@
 
 #include "dlb2_priv.h"
 #include "dlb2_inline_fns.h"
+#include "pf/base/dlb2_regs.h"
 
 enum dlb2_xstats_type {
 	/* common to device and port */
@@ -21,6 +22,7 @@ enum dlb2_xstats_type {
 	zero_polls,			/**< Call dequeue burst and return 0 */
 	tx_nospc_ldb_hw_credits,	/**< Insufficient LDB h/w credits */
 	tx_nospc_dir_hw_credits,	/**< Insufficient DIR h/w credits */
+	tx_nospc_hw_credits,		/**< Insufficient h/w credits */
 	tx_nospc_inflight_max,		/**< Reach the new_event_threshold */
 	tx_nospc_new_event_limit,	/**< Insufficient s/w credits */
 	tx_nospc_inflight_credits,	/**< Port has too few s/w credits */
@@ -29,6 +31,7 @@ enum dlb2_xstats_type {
 	inflight_events,
 	ldb_pool_size,
 	dir_pool_size,
+	pool_size,
 	/* port specific */
 	tx_new,				/**< Send an OP_NEW event */
 	tx_fwd,				/**< Send an OP_FORWARD event */
@@ -129,6 +132,9 @@ dlb2_device_traffic_stat_get(struct dlb2_eventdev *dlb2,
 		case tx_nospc_dir_hw_credits:
 			val += port->stats.traffic.tx_nospc_dir_hw_credits;
 			break;
+		case tx_nospc_hw_credits:
+			val += port->stats.traffic.tx_nospc_hw_credits;
+			break;
 		case tx_nospc_inflight_max:
 			val += port->stats.traffic.tx_nospc_inflight_max;
 			break;
@@ -159,6 +165,7 @@ get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,
 	case zero_polls:
 	case tx_nospc_ldb_hw_credits:
 	case tx_nospc_dir_hw_credits:
+	case tx_nospc_hw_credits:
 	case tx_nospc_inflight_max:
 	case tx_nospc_new_event_limit:
 	case tx_nospc_inflight_credits:
@@ -171,6 +178,8 @@ get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,
 		return dlb2->num_ldb_credits;
 	case dir_pool_size:
 		return dlb2->num_dir_credits;
+	case pool_size:
+		return dlb2->num_credits;
 	default: return -1;
 	}
 }
@@ -203,6 +212,9 @@ get_port_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx,
 	case tx_nospc_dir_hw_credits:
 		return ev_port->stats.traffic.tx_nospc_dir_hw_credits;
 
+	case tx_nospc_hw_credits:
+		return ev_port->stats.traffic.tx_nospc_hw_credits;
+
 	case tx_nospc_inflight_max:
 		return ev_port->stats.traffic.tx_nospc_inflight_max;
 
@@ -357,6 +369,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		"zero_polls",
 		"tx_nospc_ldb_hw_credits",
 		"tx_nospc_dir_hw_credits",
+		"tx_nospc_hw_credits",
 		"tx_nospc_inflight_max",
 		"tx_nospc_new_event_limit",
 		"tx_nospc_inflight_credits",
@@ -364,6 +377,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		"inflight_events",
 		"ldb_pool_size",
 		"dir_pool_size",
+		"pool_size",
 	};
 	static const enum dlb2_xstats_type dev_types[] = {
 		rx_ok,
@@ -375,6 +389,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		zero_polls,
 		tx_nospc_ldb_hw_credits,
 		tx_nospc_dir_hw_credits,
+		tx_nospc_hw_credits,
 		tx_nospc_inflight_max,
 		tx_nospc_new_event_limit,
 		tx_nospc_inflight_credits,
@@ -382,6 +397,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		inflight_events,
 		ldb_pool_size,
 		dir_pool_size,
+		pool_size,
 	};
 	/* Note: generated device stats are not allowed to be reset. */
 	static const uint8_t dev_reset_allowed[] = {
@@ -394,6 +410,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		0, /* zero_polls */
 		0, /* tx_nospc_ldb_hw_credits */
 		0, /* tx_nospc_dir_hw_credits */
+		0, /* tx_nospc_hw_credits */
 		0, /* tx_nospc_inflight_max */
 		0, /* tx_nospc_new_event_limit */
 		0, /* tx_nospc_inflight_credits */
@@ -401,6 +418,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		0, /* inflight_events */
 		0, /* ldb_pool_size */
 		0, /* dir_pool_size */
+		0, /* pool_size */
 	};
 	static const char * const port_stats[] = {
 		"is_configured",
@@ -415,6 +433,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		"zero_polls",
 		"tx_nospc_ldb_hw_credits",
 		"tx_nospc_dir_hw_credits",
+		"tx_nospc_hw_credits",
 		"tx_nospc_inflight_max",
 		"tx_nospc_new_event_limit",
 		"tx_nospc_inflight_credits",
@@ -448,6 +467,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		zero_polls,
 		tx_nospc_ldb_hw_credits,
 		tx_nospc_dir_hw_credits,
+		tx_nospc_hw_credits,
 		tx_nospc_inflight_max,
 		tx_nospc_new_event_limit,
 		tx_nospc_inflight_credits,
@@ -481,6 +501,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		1, /* zero_polls */
 		1, /* tx_nospc_ldb_hw_credits */
 		1, /* tx_nospc_dir_hw_credits */
+		1, /* tx_nospc_hw_credits */
 		1, /* tx_nospc_inflight_max */
 		1, /* tx_nospc_new_event_limit */
 		1, /* tx_nospc_inflight_credits */
@@ -935,8 +956,8 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
 		break;
 	case RTE_EVENT_DEV_XSTATS_PORT:
 		if (queue_port_id == -1) {
-			for (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version);
-					i++) {
+			for (i = 0;
+			     i < DLB2_MAX_NUM_PORTS(dlb2->version); i++) {
 				if (dlb2_xstats_reset_port(dlb2, i,
 							   ids, nb_ids))
 					return -EINVAL;
@@ -949,8 +970,8 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
 		break;
 	case RTE_EVENT_DEV_XSTATS_QUEUE:
 		if (queue_port_id == -1) {
-			for (i = 0; i < DLB2_MAX_NUM_QUEUES(dlb2->version);
-					i++) {
+			for (i = 0;
+			     i < DLB2_MAX_NUM_QUEUES(dlb2->version); i++) {
 				if (dlb2_xstats_reset_queue(dlb2, i,
 							    ids, nb_ids))
 					return -EINVAL;
@@ -1048,6 +1069,9 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
 	fprintf(f, "\tnum_dir_credits = %u\n",
 		dlb2->hw_rsrc_query_results.num_dir_credits);
 
+	fprintf(f, "\tnum_credits = %u\n",
+		dlb2->hw_rsrc_query_results.num_credits);
+
 	/* Port level information */
 
 	for (i = 0; i < dlb2->num_ports; i++) {
@@ -1102,6 +1126,12 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
 		fprintf(f, "\tdir_credits = %u\n",
 			p->qm_port.dir_credits);
 
+		fprintf(f, "\tcached_credits = %u\n",
+			p->qm_port.cached_credits);
+
+		fprintf(f, "\tdir_credits = %u\n",
+			p->qm_port.credits);
+
 		fprintf(f, "\tgenbit=%d, cq_idx=%d, cq_depth=%d\n",
 			p->qm_port.gen_bit,
 			p->qm_port.cq_idx,
@@ -1139,6 +1169,9 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
 		fprintf(f, "\t\ttx_nospc_dir_hw_credits %" PRIu64 "\n",
 			p->stats.traffic.tx_nospc_dir_hw_credits);
 
+		fprintf(f, "\t\ttx_nospc_hw_credits %" PRIu64 "\n",
+			p->stats.traffic.tx_nospc_hw_credits);
+
 		fprintf(f, "\t\ttx_nospc_inflight_max %" PRIu64 "\n",
 			p->stats.traffic.tx_nospc_inflight_max);
 
Signature · 1 line
2.23.0
#143 lore raw

PATCH v5 25/26 event/dlb2: move rte config defines to runtime devargs

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

The new devarg names and their default values are listed below. The defaults have not changed, and none of these parameters are accessed in the fast path.

poll_interval=1000
sw_credit_quantai=32
default_depth_thresh=256

---
 config/rte_config.h             |   4 --
 drivers/event/dlb2/dlb2.c       | 122 ++++++++++++++++++++++++++++----
 drivers/event/dlb2/dlb2_priv.h  |  14 ++++
 drivers/event/dlb2/pf/dlb2_pf.c |   5 +-
 4 files changed, 125 insertions(+), 20 deletions(-)
config/rte_config.h +0 -4
index b13c0884b..590903c07 100644
@@ -140,10 +140,6 @@
 #define RTE_LIBRTE_QEDE_FW ""
 
 /* DLB2 defines */
-#define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000
-#define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE  0
 #undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
-#define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32
-#define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256
 
 #endif /* _RTE_CONFIG_H_ */
drivers/event/dlb2/dlb2.c +107 -15

183 lines not on this page · raw message

drivers/event/dlb2/dlb2_priv.h +14 -0
index f3a9fe0aa..cf120c92d 100644
@@ -22,6 +22,11 @@
 
 #define EVDEV_DLB2_NAME_PMD dlb2_event
 
+/* Default values for command line devargs */
+#define DLB2_POLL_INTERVAL_DEFAULT 1000
+#define DLB2_SW_CREDIT_QUANTA_DEFAULT 32
+#define DLB2_DEPTH_THRESH_DEFAULT 256
+
 /*  command line arg strings */
 #define NUMA_NODE_ARG "numa_node"
 #define DLB2_MAX_NUM_EVENTS "max_num_events"
@@ -30,6 +35,9 @@
 #define DLB2_DEFER_SCHED_ARG "defer_sched"
 #define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh"
 #define DLB2_COS_ARG "cos"
+#define DLB2_POLL_INTERVAL_ARG "poll_interval"
+#define DLB2_SW_CREDIT_QUANTA_ARG "sw_credit_quanta"
+#define DLB2_DEPTH_THRESH_ARG "default_depth_thresh"
 
 /* Begin HW related defines and structs */
 
@@ -570,6 +578,9 @@ struct dlb2_eventdev {
 	bool global_dequeue_wait; /* Not using per dequeue wait if true */
 	bool defer_sched;
 	enum dlb2_cq_poll_modes poll_mode;
+	int poll_interval;
+	int sw_credit_quanta;
+	int default_depth_thresh;
 	uint8_t revision;
 	uint8_t version;
 	bool configured;
@@ -603,6 +614,9 @@ struct dlb2_devargs {
 	int defer_sched;
 	struct dlb2_qid_depth_thresholds qid_depth_thresholds;
 	enum dlb2_cos cos_id;
+	int poll_interval;
+	int sw_credit_quanta;
+	int default_depth_thresh;
 };
 
 /* End Eventdev related defines and structs */
drivers/event/dlb2/pf/dlb2_pf.c +4 -1
index f57dc1584..e9da89d65 100644
@@ -615,7 +615,10 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)
 		.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,
 		.num_dir_credits_override = -1,
 		.qid_depth_thresholds = { {0} },
-		.cos_id = DLB2_COS_DEFAULT
+		.cos_id = DLB2_COS_DEFAULT,
+		.poll_interval = DLB2_POLL_INTERVAL_DEFAULT,
+		.sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT,
+		.default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT
 	};
 	struct dlb2_eventdev *dlb2;
 
Signature · 1 line
2.23.0
#144 lore raw

PATCH v5 26/26 doc/dlb2: update documentation for v2.5

In reply to McDaniel, Timothy

From: Timothy McDaniel <[email protected]>

Update the dlb documentation for v2.5. Notable differences include the new cobined credit scheme. Also cleaned up a couple of sections, and removed a duplicate section.

---
 doc/guides/eventdevs/dlb2.rst | 153 +++++++++++++++-------------------
 1 file changed, 66 insertions(+), 87 deletions(-)
doc/guides/eventdevs/dlb2.rst +66 -87
index 94d2c77ff..0f1f25cc5 100644
@@ -1,10 +1,11 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
     Copyright(c) 2020 Intel Corporation.
 
-Driver for the Intel® Dynamic Load Balancer (DLB2)
+Driver for the Intel® Dynamic Load Balancer (DLB)
 ==================================================
 
-The DPDK dlb poll mode driver supports the Intel® Dynamic Load Balancer.
+The DPDK DLB poll mode driver supports the Intel® Dynamic Load Balancer,
+hardware versions 2.0 and 2.5.
 
 Prerequisites
 -------------
@@ -15,34 +16,34 @@ the basic DPDK environment.
 Configuration
 -------------
 
-The DLB2 PF PMD is a user-space PMD that uses VFIO to gain direct
+The DLB PF PMD is a user-space PMD that uses VFIO to gain direct
 device access. To use this operation mode, the PCIe PF device must be bound
 to a DPDK-compatible VFIO driver, such as vfio-pci.
 
 Eventdev API Notes
 ------------------
 
-The DLB2 provides the functions of a DPDK event device; specifically, it
+The DLB PMD provides the functions of a DPDK event device; specifically, it
 supports atomic, ordered, and parallel scheduling events from queues to ports.
-However, the DLB2 hardware is not a perfect match to the eventdev API. Some DLB2
+However, the DLB hardware is not a perfect match to the eventdev API. Some DLB
 features are abstracted by the PMD such as directed ports.
 
-In general the dlb PMD is designed for ease-of-use and does not require a
+In general the DLB PMD is designed for ease-of-use and does not require a
 detailed understanding of the hardware, but these details are important when
 writing high-performance code. This section describes the places where the
-eventdev API and DLB2 misalign.
+eventdev API and DLB misalign.
 
 Scheduling Domain Configuration
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-There are 32 scheduling domainis the DLB2.
+DLB supports 32 scheduling domains.
 When one is configured, it allocates load-balanced and
 directed queues, ports, credits, and other hardware resources. Some
 resource allocations are user-controlled -- the number of queues, for example
 -- and others, like credit pools (one directed and one load-balanced pool per
 scheduling domain), are not.
 
-The DLB2 is a closed system eventdev, and as such the ``nb_events_limit`` device
+The DLB is a closed system eventdev, and as such the ``nb_events_limit`` device
 setup argument and the per-port ``new_event_threshold`` argument apply as
 defined in the eventdev header file. The limit is applied to all enqueues,
 regardless of whether it will consume a directed or load-balanced credit.
@@ -67,7 +68,7 @@ If the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag is not set, schedule_type
 dictates the queue's scheduling type.
 
 The ``nb_atomic_order_sequences`` queue configuration field sets the ordered
-queue's reorder buffer size.  DLB2 has 4 groups of ordered queues, where each
+queue's reorder buffer size.  DLB has 2 groups of ordered queues, where each
 group is configured to contain either 1 queue with 1024 reorder entries, 2
 queues with 512 reorder entries, and so on down to 32 queues with 32 entries.
 
@@ -75,57 +76,22 @@ When a load-balanced queue is created, the PMD will configure a new sequence
 number group on-demand if num_sequence_numbers does not match a pre-existing
 group with available reorder buffer entries. If all sequence number groups are
 in use, no new group will be created and queue configuration will fail. (Note
-that when the PMD is used with a virtual DLB2 device, it cannot change the
+that when the PMD is used with a virtual DLB device, it cannot change the
 sequence number configuration.)
 
-The queue's ``nb_atomic_flows`` parameter is ignored by the DLB2 PMD, because
-the DLB2 does not limit the number of flows a queue can track. In the DLB2, all
-load-balanced queues can use the full 16-bit flow ID range.
-
-Load-Balanced Queues
-~~~~~~~~~~~~~~~~~~~~
-
-A load-balanced queue can support atomic and ordered scheduling, or atomic and
-unordered scheduling, but not atomic and unordered and ordered scheduling. A
-queue's scheduling types are controlled by the event queue configuration.
-
-If the user sets the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag, the
-``nb_atomic_order_sequences`` determines the supported scheduling types.
-With non-zero ``nb_atomic_order_sequences``, the queue is configured for atomic
-and ordered scheduling. In this case, ``RTE_SCHED_TYPE_PARALLEL`` scheduling is
-supported by scheduling those events as ordered events.  Note that when the
-event is dequeued, its sched_type will be ``RTE_SCHED_TYPE_ORDERED``. Else if
-``nb_atomic_order_sequences`` is zero, the queue is configured for atomic and
-unordered scheduling. In this case, ``RTE_SCHED_TYPE_ORDERED`` is unsupported.
-
-If the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag is not set, schedule_type
-dictates the queue's scheduling type.
-
-The ``nb_atomic_order_sequences`` queue configuration field sets the ordered
-queue's reorder buffer size.  DLB2 has 4 groups of ordered queues, where each
-group is configured to contain either 1 queue with 1024 reorder entries, 2
-queues with 512 reorder entries, and so on down to 32 queues with 32 entries.
-
-When a load-balanced queue is created, the PMD will configure a new sequence
-number group on-demand if num_sequence_numbers does not match a pre-existing
-group with available reorder buffer entries. If all sequence number groups are
-in use, no new group will be created and queue configuration will fail. (Note
-that when the PMD is used with a virtual DLB2 device, it cannot change the
-sequence number configuration.)
-
-The queue's ``nb_atomic_flows`` parameter is ignored by the DLB2 PMD, because
-the DLB2 does not limit the number of flows a queue can track. In the DLB2, all
+The queue's ``nb_atomic_flows`` parameter is ignored by the DLB PMD, because
+the DLB does not limit the number of flows a queue can track. In the DLB, all
 load-balanced queues can use the full 16-bit flow ID range.
 
 Load-balanced and Directed Ports
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-DLB2 ports come in two flavors: load-balanced and directed. The eventdev API
+DLB ports come in two flavors: load-balanced and directed. The eventdev API
 does not have the same concept, but it has a similar one: ports and queues that
 are singly-linked (i.e. linked to a single queue or port, respectively).
 
 The ``rte_event_dev_info_get()`` function reports the number of available
-event ports and queues (among other things). For the DLB2 PMD, max_event_ports
+event ports and queues (among other things). For the DLB PMD, max_event_ports
 and max_event_queues report the number of available load-balanced ports and
 queues, and max_single_link_event_port_queue_pairs reports the number of
 available directed ports and queues.
@@ -151,31 +117,38 @@ only be linked to a single directed queue (and vice versa), and that link
 cannot change after the eventdev is started.
 
 The eventdev API does not have a directed scheduling type. To support directed
-traffic, the dlb PMD detects when an event is being sent to a directed queue
+traffic, the DLB PMD detects when an event is being sent to a directed queue
 and overrides its scheduling type. Note that the originally selected scheduling
 type (atomic, ordered, or parallel) is not preserved, and an event's sched_type
 will be set to ``RTE_SCHED_TYPE_ATOMIC`` when it is dequeued from a directed
 port.
 
+Finally, even though all 3 event types are supported on the same QID by
+converting unordered events to ordered, such use should be discouraged as much
+as possible, since mixing types on the same queue uses valuable reorder
+resources, and orders events which do not require ordering.
+
 Flow ID
 ~~~~~~~
 
 The flow ID field is preserved in the event when it is scheduled in the
-DLB2.
+DLB.
 
 Hardware Credits
 ~~~~~~~~~~~~~~~~
 
-DLB2 uses a hardware credit scheme to prevent software from overflowing hardware
+DLB uses a hardware credit scheme to prevent software from overflowing hardware
 event storage, with each unit of storage represented by a credit. A port spends
 a credit to enqueue an event, and hardware refills the ports with credits as the
-events are scheduled to ports. Refills come from credit pools, and each port is
-a member of a load-balanced credit pool and a directed credit pool. The
-load-balanced credits are used to enqueue to load-balanced queues, and directed
-credits are used for directed queues.
+events are scheduled to ports. Refills come from credit pools.
 
-A DLB2 eventdev contains one load-balanced and one directed credit pool. These
-pools' sizes are controlled by the nb_events_limit field in struct
+For DLB v2.5, there is a single credit pool used for both load balanced and
+directed traffic.
+
+For DLB v2.0, each port is a member of both a load-balanced credit pool and a
+directed credit pool. The load-balanced credits are used to enqueue to
+load-balanced queues, and directed credits are used for directed queues.
+These pools' sizes are controlled by the nb_events_limit field in struct
 rte_event_dev_config. The load-balanced pool is sized to contain
 nb_events_limit credits, and the directed pool is sized to contain
 nb_events_limit/4 credits. The directed pool size can be overridden with the
@@ -183,7 +156,7 @@ num_dir_credits vdev argument, like so:
 
     .. code-block:: console
 
-       --vdev=dlb1_event,num_dir_credits=<value>
+       --vdev=dlb2_event,num_dir_credits=<value>
 
 This can be used if the default allocation is too low or too high for the
 specific application needs. The PMD also supports a vdev arg that limits the
@@ -191,17 +164,17 @@ max_num_events reported by rte_event_dev_info_get():
 
     .. code-block:: console
 
-       --vdev=dlb1_event,max_num_events=<value>
+       --vdev=dlb2_event,max_num_events=<value>
 
 By default, max_num_events is reported as the total available load-balanced
-credits. If multiple DLB2-based applications are being used, it may be desirable
+credits. If multiple DLB-based applications are being used, it may be desirable
 to control how many load-balanced credits each application uses, particularly
 when application(s) are written to configure nb_events_limit equal to the
 reported max_num_events.
 
 Each port is a member of both credit pools. A port's credit allocation is
 defined by its low watermark, high watermark, and refill quanta. These three
-parameters are calculated by the dlb PMD like so:
+parameters are calculated by the DLB PMD like so:
 
 - The load-balanced high watermark is set to the port's enqueue_depth.
   The directed high watermark is set to the minimum of the enqueue_depth and
@@ -220,16 +193,16 @@ order to reach the limit.
 
 If a port attempts to enqueue and has no credits available, the enqueue
 operation will fail and the application must retry the enqueue. Credits are
-replenished asynchronously by the DLB2 hardware.
+replenished asynchronously by the DLB hardware.
 
 Software Credits
 ~~~~~~~~~~~~~~~~
 
-The DLB2 is a "closed system" event dev, and the DLB2 PMD layers a software
+The DLB is a "closed system" event dev, and the DLB PMD layers a software
 credit scheme on top of the hardware credit scheme in order to comply with
 the per-port backpressure described in the eventdev API.
 
-The DLB2's hardware scheme is local to a queue/pipeline stage: a port spends a
+The DLB's hardware scheme is local to a queue/pipeline stage: a port spends a
 credit when it enqueues to a queue, and credits are later replenished after the
 events are dequeued and released.
 
@@ -249,8 +222,8 @@ credits are used to enqueue to a load-balanced queue, and directed credits are
 used to enqueue to a directed queue.
 
 The out-of-credit situations are typically transient, and an eventdev
-application using the DLB2 ought to retry its enqueues if they fail.
-If enqueue fails, DLB2 PMD sets rte_errno as follows:
+application using the DLB ought to retry its enqueues if they fail.
+If enqueue fails, DLB PMD sets rte_errno as follows:
 
 - -ENOSPC: Credit exhaustion (either hardware or software)
 - -EINVAL: Invalid argument, such as port ID, queue ID, or sched_type.
@@ -272,21 +245,27 @@ the port's dequeue_depth).
 Priority
 ~~~~~~~~
 
-The DLB2 supports event priority and per-port queue service priority, as
-described in the eventdev header file. The DLB2 does not support 'global' event
+The DLB supports event priority and per-port queue service priority, as
+described in the eventdev header file. The DLB does not support 'global' event
 queue priority established at queue creation time.
 
-DLB2 supports 8 event and queue service priority levels. For both priority
-types, the PMD uses the upper three bits of the priority field to determine the
-DLB2 priority, discarding the 5 least significant bits. The 5 least significant
-event priority bits are not preserved when an event is enqueued.
+DLB supports 4 event and queue service priority levels. For both priority types,
+the PMD uses the upper three bits of the priority field to determine the DLB
+priority, discarding the 5 least significant bits. But least significant bit out
+of 3 priority bits is effectively ignored for binning into 4 priorities. The
+discarded 5 least significant event priority bits are not preserved when an event
+is enqueued.
+
+Note that event priority only works within the same event type.
+When atomic and ordered or unordered events are enqueued to same QID, priority
+across the types is always equal, and both types are served in a round robin manner.
 
 Reconfiguration
 ~~~~~~~~~~~~~~~
 
 The Eventdev API allows one to reconfigure a device, its ports, and its queues
 by first stopping the device, calling the configuration function(s), then
-restarting the device. The DLB2 does not support configuring an individual queue
+restarting the device. The DLB does not support configuring an individual queue
 or port without first reconfiguring the entire device, however, so there are
 certain reconfiguration sequences that are valid in the eventdev API but not
 supported by the PMD.
@@ -317,9 +296,9 @@ before its ports or queues can be.
 Deferred Scheduling
 ~~~~~~~~~~~~~~~~~~~
 
-The DLB2 PMD's default behavior for managing a CQ is to "pop" the CQ once per
+The DLB PMD's default behavior for managing a CQ is to "pop" the CQ once per
 dequeued event before returning from rte_event_dequeue_burst(). This frees the
-corresponding entries in the CQ, which enables the DLB2 to schedule more events
+corresponding entries in the CQ, which enables the DLB to schedule more events
 to it.
 
 To support applications seeking finer-grained scheduling control -- for example
@@ -333,12 +312,12 @@ To enable deferred scheduling, use the defer_sched vdev argument like so:
 
     .. code-block:: console
 
-       --vdev=dlb1_event,defer_sched=on
+       --vdev=dlb2_event,defer_sched=on
 
 Atomic Inflights Allocation
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-In the last stage prior to scheduling an atomic event to a CQ, DLB2 holds the
+In the last stage prior to scheduling an atomic event to a CQ, DLB holds the
 inflight event in a temporary buffer that is divided among load-balanced
 queues. If a queue's atomic buffer storage fills up, this can result in
 head-of-line-blocking. For example:
@@ -361,12 +340,12 @@ increase a vdev's per-queue atomic-inflight allocation to (for example) 64:
 
     .. code-block:: console
 
-       --vdev=dlb1_event,atm_inflights=64
+       --vdev=dlb2_event,atm_inflights=64
 
 QID Depth Threshold
 ~~~~~~~~~~~~~~~~~~~
 
-DLB2 supports setting and tracking queue depth thresholds. Hardware uses
+DLB supports setting and tracking queue depth thresholds. Hardware uses
 the thresholds to track how full a queue is compared to its threshold.
 Four buckets are used
 
@@ -375,7 +354,7 @@ Four buckets are used
 - Greater than 75%, but less than or equal to 100% of depth threshold
 - Greater than 100% of depth thresholds
 
-Per queue threshold metrics are tracked in the DLB2 xstats, and are also
+Per queue threshold metrics are tracked in the DLB xstats, and are also
 returned in the impl_opaque field of each received event.
 
 The per qid threshold can be specified as part of the device args, and
@@ -391,12 +370,12 @@ shown below.
 Class of service
 ~~~~~~~~~~~~~~~~
 
-DLB2 supports provisioning the DLB2 bandwidth into 4 classes of service.
+DLB supports provisioning the DLB bandwidth into 4 classes of service.
 
-- Class 4 corresponds to 40% of the DLB2 hardware bandwidth
-- Class 3 corresponds to 30% of the DLB2 hardware bandwidth
-- Class 2 corresponds to 20% of the DLB2 hardware bandwidth
-- Class 1 corresponds to 10% of the DLB2 hardware bandwidth
+- Class 4 corresponds to 40% of the DLB hardware bandwidth
+- Class 3 corresponds to 30% of the DLB hardware bandwidth
+- Class 2 corresponds to 20% of the DLB hardware bandwidth
+- Class 1 corresponds to 10% of the DLB hardware bandwidth
 - Class 0 corresponds to don't care
 
 The classes are applied globally to the set of ports contained in this
Signature · 1 line
2.23.0
#145 lore raw

Re: [dpdk-dev] [PATCH v5 00/26] Add DLB v2.5

In reply to McDaniel, Timothy
Quoted 40 lines · Timothy

From: Timothy McDaniel <[email protected]>

This patch series adds support for DLB v2.5 to the current DLB V2.0 PMD. The resulting PMD supports both hardware versions.

The main differences between the DLB v2.5 and v2.0 hardware are:
- Number of queues/ports
- DLB v2.5 uses a combined credit pool, whereas DLB v2.0 splits credits into 2 pools, a directed credit pool and a load balanced credit pool.
- Different register maps, with different bit names and offsets

In order to support both hardware versions with the same PMD, and avoid code duplication, the file dlb2_resource.c required a complete rewrite. This required some creative staging of the changes in order to keep the individual patches relatively small, while also meeting the requirement that all individual patches in the set compile cleanly.

To accomplish this, a few temporary files are used:

dlb2_hw_types_new.h
dlb2_resources_new.h
dlb2_resources_new.c

As dlb2_resources_new.c is populated with the new combined v2.0/v2.5 low level logic, the corresponding old code is removed from dlb2_resource.c, thus allowing both the original and new code to continue to compile and link cleanly. Once all of the code has been migrated to the new model, the old versions of the files are removed, and the new versions are renamed, effectively replacing the old original files.

As you review the code, you can ignore the code deletions from dlb2_resource.c, as that file continues to shrink as the new corresponding logic is added to dlb2_resource_new.c.

Quoted 5 lines

Changes since V4:
1) restore original PMD name (dlb2)
2) resore original PMD source location (drivers/event/dlb2)
3) restore documentation, such that it references dlb2_event, instead of dlb_event

Applied the changes are some update in git comment. Also updated the release notes like below

(quoted diff) +0 -0

b/doc/guides/rel_notes/release_21_05.rst
index 428615e4f..58f796b7e 100644

doc/guides/rel_notes/release_21_05.rst +4 -0
@@ -273,6 +273,10 @@ New Features
   * Added support for crypto adapter forward mode in octeontx2 event and crypto
     device driver.
 
+* **Updated Intel DLB2 driver.**
+
+  * Added support for v2.5 device.
+
 
 
 
Quoted 90 lines

Changes since V3:
1) Moved minor cleanup to its own patch. This included
a) remove FPGA references
b) eliminate duplicate macros/defines in hw_types
c) don't include dlb2_mbox.h
d) delete unused defines.macros (SMON, INT, ...)
2) Changed DLB V2.x and V2.x to simply v2.x, where v is lower case
3) Updated 20.11 release notes to remove reference to dlb2 doc, since it is now named dlb.rst
4) Updated commit message/header text, as requested

Changes since V2:
1) fix commit headers
2) fix commit message repeated words
3) remove FPGA reference
4) split out new v2.5 register definitions into separate patch
5) fixed documentation to use DLB and dlb_event exclusively, instead of the old names such as dlb1_event, dlb2_event, DLB2, ... Final doc updates are done in patch that performs device rename from DLB2 tosimply DLB
6) use component event/dlb at commit which changes device name and all subsequent commits
7) Move all DLB constants out of config/rte_config.h except QUELL_STATS, which is used in the fastpath. Exposed these as devarg command line parameters
8) Removed "TEMPORARY" comment leftover in dlb2_osdep.h
9) squashed 20-21 and 22-23 since they were logically the same as 19-20, which was requested to be squashed
10) delete old dlb2.rst - dlb.rst has been updated for v2.0 and v2.1

Changes since V1:
1) Simplified subject text for all patches
2) correct typos/spelling
3) remove FPGA references
4) remove stale sysconf() references
5) fixed patches that had compilation issues
6) updated release notes
7) renamed dlb device from dlb2_event to dlb_event
8) moved dlb2 directory to dlb,to match name change
9) fixed other cases where "dlb2" was being used externally

Timothy McDaniel (26):
event/dlb2: minor code cleanup
event/dlb2: add v2.5 probe
event/dlb2: add v2.5 HW register definitions event/dlb2: add v2.5 HW init
event/dlb2: add v2.5 get resources event/dlb2: add v2.5 create sched domain event/dlb2: add v2.5 domain reset
event/dlb2: add v2.5 create ldb queue event/dlb2: add v2.5 create ldb port event/dlb2: add v2.5 create dir port event/dlb2: add v2.5 create dir queue event/dlb2: add v2.5 map qid
event/dlb2: add v2.5 unmap queue
event/dlb2: add v2.5 start domain
event/dlb2: add v2.5 credit scheme event/dlb2: add v2.5 queue depth functions event/dlb2: add v2.5 finish map/unmap event/dlb2: add v2.5 sparse cq mode event/dlb2: add v2.5 sequence number management event/dlb2: use new implementation of resource header event/dlb2: use new implementation of resource file event/dlb2: use new implementation of HW types header event/dlb2: use new combined register map event/dlb2: update xstats for v2.5 event/dlb2: move rte config defines to runtime devargs doc/dlb2: update documentation for v2.5

 config/rte_config.h                        |    4 -
 doc/guides/eventdevs/dlb2.rst              |  153 +-
 drivers/event/dlb2/dlb2.c                  |  550 +-
 drivers/event/dlb2/dlb2_priv.h             |  170 +-
 drivers/event/dlb2/dlb2_user.h             |   27 +-
 drivers/event/dlb2/dlb2_xstats.c           |   70 +-
 drivers/event/dlb2/pf/base/dlb2_hw_types.h |  106 +-
 drivers/event/dlb2/pf/base/dlb2_mbox.h     |  596 --
 drivers/event/dlb2/pf/base/dlb2_osdep.h    |    2 +
 drivers/event/dlb2/pf/base/dlb2_regs.h     | 5955 +++++++++++++-------
 drivers/event/dlb2/pf/base/dlb2_resource.c | 3278 ++++++-----
 drivers/event/dlb2/pf/base/dlb2_resource.h |   28 +-
 drivers/event/dlb2/pf/dlb2_main.c          |   37 +-
 drivers/event/dlb2/pf/dlb2_pf.c            |   67 +-
 14 files changed, 6445 insertions(+), 4598 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_mbox.h

--
2.23.0

#146 lore raw

PATCH 2/25 event/dlb2: add DLB v2.5 probe-time hardware init

In reply to Timothy McDaniel

This commit adds support for DLB v2.5 probe-time hardware init, and sets up a framework for incorporating the remaining changes required to support DLB v2.5.

DLB v2.0 and DLB v2.5 are similar in many respects, but their register offsets and definitions are different. As a result of these, differences, the low level hardware functions must take the devicei version into consideration. This requires that the hardware version be passed to many of the low level functions, so that the PMD can take the appropriate action based on the device version.

To ease the transition and keep the individual patches small, three temporary files are added in this commit. These files have "new" in their names. The files with "new" contain changes specific to a consolidated PMD that supports both DLB v2.0 and DLB 2.5. Their sister files of the same name (minus "new") contain the old DLB v2.0 specific code. The intent is to remove code from the original files as that code is ported to the combined DLB 2.0/2.5 PMD model and added to the "new" files in a series of commits. At end of the patch series, the old files will be empty and the "new" files will have the logic needed to implement a single PMD that supports both DLB v2.0 and DLB v2.5. At that time, the original DLB v2.0 specific files will be deleted, and the "new" files will be renamed and replace them.

---
 drivers/event/dlb2/dlb2_priv.h                |    5 +
 drivers/event/dlb2/meson.build                |    1 +
 .../event/dlb2/pf/base/dlb2_hw_types_new.h    |  362 ++
 drivers/event/dlb2/pf/base/dlb2_mbox.h        |    1 -
 drivers/event/dlb2/pf/base/dlb2_osdep.h       |    4 +
 drivers/event/dlb2/pf/base/dlb2_regs_new.h    | 4412 +++++++++++++++++
 drivers/event/dlb2/pf/base/dlb2_resource.c    |  180 +-
 drivers/event/dlb2/pf/base/dlb2_resource.h    |   36 -
 .../event/dlb2/pf/base/dlb2_resource_new.c    |  271 +
 .../event/dlb2/pf/base/dlb2_resource_new.h    |   73 +
 drivers/event/dlb2/pf/dlb2_main.c             |   41 +-
 drivers/event/dlb2/pf/dlb2_main.h             |    4 +
 drivers/event/dlb2/pf/dlb2_pf.c               |    6 +-
 13 files changed, 5165 insertions(+), 231 deletions(-)
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types_new.h
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_regs_new.h
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.c
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.h
drivers/event/dlb2/dlb2_priv.h +5 -0
index b6de8d937..ad663a38e 100644
@@ -116,6 +116,11 @@
 #define EV_TO_DLB2_PRIO(x) ((x) >> 5)
 #define DLB2_TO_EV_PRIO(x) ((x) << 5)
 
+enum dlb2_hw_ver {
+	DLB2_HW_VER_2,
+	DLB2_HW_VER_2_5,
+};
+
 enum dlb2_hw_port_types {
 	DLB2_LDB_PORT,
 	DLB2_DIR_PORT,
drivers/event/dlb2/meson.build +1 -0
index f22638b8e..bded07e06 100644
@@ -14,6 +14,7 @@ sources = files('dlb2.c',
 		'pf/dlb2_main.c',
 		'pf/dlb2_pf.c',
 		'pf/base/dlb2_resource.c',
+		'pf/base/dlb2_resource_new.c',
 		'rte_pmd_dlb2.c',
 		'dlb2_selftest.c'
 )
drivers/event/dlb2/pf/base/dlb2_hw_types_new.h new file +362 -0

362 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_mbox.h +0 -1
index ce462c089..c6a562f13 100644
@@ -6,7 +6,6 @@
 #define __DLB2_BASE_DLB2_MBOX_H
 
 #include "dlb2_osdep_types.h"
-#include "dlb2_regs.h"
 
 #define DLB2_MBOX_INTERFACE_VERSION 1
 
drivers/event/dlb2/pf/base/dlb2_osdep.h +4 -0
index c4c34eba5..747f680b9 100644
@@ -16,7 +16,11 @@
 #include <rte_log.h>
 #include <rte_spinlock.h>
 #include "../dlb2_main.h"
+
+/* TEMPORARY inclusion of both headers for merge */
+#include "dlb2_resource_new.h"
 #include "dlb2_resource.h"
+
 #include "../../dlb2_log.h"
 #include "../../dlb2_user.h"
 
drivers/event/dlb2/pf/base/dlb2_regs_new.h new file +4412 -0

2,602 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource.c +1 -179

180 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource.h +0 -36
index 503fdf317..2e13193bb 100644

Lines of this file are not shown. View the raw message.

drivers/event/dlb2/pf/base/dlb2_resource_new.c new file +271 -0

271 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource_new.h new file +73 -0

73 lines not on this page · raw message

drivers/event/dlb2/pf/dlb2_main.c +28 -13

41 lines not on this page · raw message

drivers/event/dlb2/pf/dlb2_main.h +4 -0
index f3bee71fb..01a24e8a4 100644

Lines of this file are not shown. View the raw message.

drivers/event/dlb2/pf/dlb2_pf.c +4 -2
index a937d0f9c..9b40e5eb3 100644

Lines of this file are not shown. View the raw message.

The rest of this diff is not shown. View the raw message.

Signature · 1 line
2.23.0

Part of the diff is not shown here. View the raw message.

#147 lore raw

Re: [dpdk-dev] [EXT] [PATCH 02/25] event/dlb2: add DLB v2.5 probe-time hardware init

Quoted 4 lines

-----Original Message-----
From: Timothy McDaniel <[email protected]>
Sent: Wednesday, March 17, 2021 3:49 AM
To: [email protected]

Quoted 8 lines

Cc: Jerin Jacob Kollanukkaran <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Pavan Nikhilesh Bhagavatula <[email protected]>; [email protected]; [email protected]; [email protected]
Subject: [EXT] [PATCH 02/25] event/dlb2: add DLB v2.5 probe-time hardware init

Please simplify subject in all the patches like
event/dlb2: add v2.5 HW init

Quoted 8 lines

----------------------------------------------------------------------
This commit adds support for DLB v2.5 probe-time hardware init, and sets up a framework for incorporating the remaining changes required to support DLB v2.5.

DLB v2.0 and DLB v2.5 are similar in many respects, but their register offsets and definitions are different. As a result of these, differences, the low level hardware functions must take the devicei

s/devicei/device

Quoted 38 lines

version into consideration. This requires that the hardware version be passed to many of the low level functions, so that the PMD can take the appropriate action based on the device version.

To ease the transition and keep the individual patches small, three temporary files are added in this commit. These files have "new" in their names. The files with "new" contain changes specific to a consolidated PMD that supports both DLB v2.0 and DLB 2.5. Their sister files of the same name (minus "new") contain the old DLB v2.0 specific code. The intent is to remove code from the original files as that code is ported to the combined DLB 2.0/2.5 PMD model and added to the "new" files in a series of commits. At end of the patch series, the old files will be empty and the "new" files will have the logic needed to implement a single PMD that supports both DLB v2.0 and DLB v2.5. At that time, the original DLB v2.0 specific files will be deleted, and the "new" files will be renamed and replace them.

---
 drivers/event/dlb2/dlb2_priv.h                |    5 +
 drivers/event/dlb2/meson.build                |    1 +
 .../event/dlb2/pf/base/dlb2_hw_types_new.h    |  362 ++
 drivers/event/dlb2/pf/base/dlb2_mbox.h        |    1 -
 drivers/event/dlb2/pf/base/dlb2_osdep.h       |    4 +
 drivers/event/dlb2/pf/base/dlb2_regs_new.h    | 4412 +++++++++++++++++
 drivers/event/dlb2/pf/base/dlb2_resource.c    |  180 +-
 drivers/event/dlb2/pf/base/dlb2_resource.h    |   36 -
 .../event/dlb2/pf/base/dlb2_resource_new.c    |  271 +
 .../event/dlb2/pf/base/dlb2_resource_new.h    |   73 +
 drivers/event/dlb2/pf/dlb2_main.c             |   41 +-
 drivers/event/dlb2/pf/dlb2_main.h             |    4 +
 drivers/event/dlb2/pf/dlb2_pf.c               |    6 +-
 13 files changed, 5165 insertions(+), 231 deletions(-)
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types_new.h
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_regs_new.h
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.c
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.h
Quoted 1 line

+#ifdef FPGA

Don't do this. Either detect the FPGA presence or make it devargs

drivers/event/dlb2/pf/base/dlb2_hw_types_new.h

Quoted 7 lines
drivers/event/dlb2/pf/base/dlb2_hw_types_new.h new file +7 -0
+#define DLB2_HZ					2000000
+#else
+#define DLB2_HZ					800000000
+#endif
+
+
+/* TEMPORARY inclusion of both headers for merge */

Please make sure to remove this comments in sub sequent patches.

drivers/event/dlb2/pf/dlb2_main.h line 15

Quoted 6 lines

b/drivers/event/dlb2/pf/dlb2_main.h
index f3bee71fb..01a24e8a4 100644

drivers/event/dlb2/pf/dlb2_main.h +0 -0
@@ -15,7 +15,11 @@
 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))

Please use DPDK APIs for this.

Quoted 1 line
drivers/event/dlb2/pf/dlb2_main.h +0 -0
 #endif
#148 lore raw

Re: [dpdk-dev] [EXT] [PATCH 02/25] event/dlb2: add DLB v2.5 probe-time hardware init

Quoted 30 lines

-----Original Message-----
From: Jerin Jacob Kollanukkaran <[email protected]>
Sent: Sunday, March 21, 2021 5:30 AM
To: McDaniel, Timothy <[email protected]>; [email protected]
Cc: Van Haaren, Harry <[email protected]>; [email protected]; [email protected]; Rao, Nikhil <[email protected]>; Carrillo, Erik G <[email protected]>; Gujjar, Abhinandan S <[email protected]>; Pavan Nikhilesh Bhagavatula <[email protected]>; [email protected]; mattias.ronnblom <[email protected]>; Mccarthy, Peter <[email protected]>
Subject: RE: [EXT] [PATCH 02/25] event/dlb2: add DLB v2.5 probe-time hardware init

Quoted 4 lines

-----Original Message-----
From: Timothy McDaniel <[email protected]>
Sent: Wednesday, March 17, 2021 3:49 AM
To: [email protected]

Quoted 8 lines

Cc: Jerin Jacob Kollanukkaran <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Pavan Nikhilesh Bhagavatula <[email protected]>; [email protected]; [email protected]; [email protected]
Subject: [EXT] [PATCH 02/25] event/dlb2: add DLB v2.5 probe-time hardware init

Quoted 3 lines

Please simplify subject in all the patches like
event/dlb2: add v2.5 HW init

Will do

Quoted 6 lines
Quoted 6 lines

----------------------------------------------------------------------
This commit adds support for DLB v2.5 probe-time hardware init, and sets up a framework for incorporating the remaining changes required to support DLB v2.5.

Quoted 7 lines
Quoted 3 lines

DLB v2.0 and DLB v2.5 are similar in many respects, but their register offsets and definitions are different. As a result of these, differences, the low level hardware functions must take the devicei

s/devicei/device

fixed

Quoted 42 lines
Quoted 38 lines

version into consideration. This requires that the hardware version be passed to many of the low level functions, so that the PMD can take the appropriate action based on the device version.

To ease the transition and keep the individual patches small, three temporary files are added in this commit. These files have "new" in their names. The files with "new" contain changes specific to a consolidated PMD that supports both DLB v2.0 and DLB 2.5. Their sister files of the same name (minus "new") contain the old DLB v2.0 specific code. The intent is to remove code from the original files as that code is ported to the combined DLB 2.0/2.5 PMD model and added to the "new" files in a series of commits. At end of the patch series, the old files will be empty and the "new" files will have the logic needed to implement a single PMD that supports both DLB v2.0 and DLB v2.5. At that time, the original DLB v2.0 specific files will be deleted, and the "new" files will be renamed and replace them.

---
 drivers/event/dlb2/dlb2_priv.h                |    5 +
 drivers/event/dlb2/meson.build                |    1 +
 .../event/dlb2/pf/base/dlb2_hw_types_new.h    |  362 ++
 drivers/event/dlb2/pf/base/dlb2_mbox.h        |    1 -
 drivers/event/dlb2/pf/base/dlb2_osdep.h       |    4 +
 drivers/event/dlb2/pf/base/dlb2_regs_new.h    | 4412 +++++++++++++++++
 drivers/event/dlb2/pf/base/dlb2_resource.c    |  180 +-
 drivers/event/dlb2/pf/base/dlb2_resource.h    |   36 -
 .../event/dlb2/pf/base/dlb2_resource_new.c    |  271 +
 .../event/dlb2/pf/base/dlb2_resource_new.h    |   73 +
 drivers/event/dlb2/pf/dlb2_main.c             |   41 +-
 drivers/event/dlb2/pf/dlb2_main.h             |    4 +
 drivers/event/dlb2/pf/dlb2_pf.c               |    6 +-
 13 files changed, 5165 insertions(+), 231 deletions(-)
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types_new.h
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_regs_new.h
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.c
 create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.h
Quoted 1 line

+#ifdef FPGA

Don't do this. Either detect the FPGA presence or make it devargs

Quoted 8 lines

drivers/event/dlb2/pf/base/dlb2_hw_types_new.h

Quoted 7 lines
drivers/event/dlb2/pf/base/dlb2_hw_types_new.h new file +7 -0
+#define DLB2_HZ					2000000
+#else
+#define DLB2_HZ					800000000
+#endif
+
+
+/* TEMPORARY inclusion of both headers for merge */

fixed

Quoted 3 lines

Please make sure to remove this comments in sub sequent patches.

will do

Quoted 9 lines

drivers/event/dlb2/pf/dlb2_main.h line 15

Quoted 6 lines

b/drivers/event/dlb2/pf/dlb2_main.h
index f3bee71fb..01a24e8a4 100644

drivers/event/dlb2/pf/dlb2_main.h +0 -0
@@ -15,7 +15,11 @@
 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))

Please use DPDK APIs for this.

done

Quoted 1 line
Quoted 1 line
drivers/event/dlb2/pf/dlb2_main.h +0 -0
 #endif
#149 lore raw

PATCH 3/25 event/dlb2: add DLB v2.5 support to get_resources

In reply to Timothy McDaniel

DLB v2.5 uses a new credit scheme, where directed and load balanced credits are unified, instead of having separate directed and load balanced credit pools.

---
 drivers/event/dlb2/dlb2.c                     | 20 ++++--
 drivers/event/dlb2/dlb2_user.h                | 14 +++-
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 48 --------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 66 +++++++++++++++++++
 4 files changed, 92 insertions(+), 56 deletions(-)
drivers/event/dlb2/dlb2.c +14 -6
index 826b68121..769bcb8af 100644
@@ -132,17 +132,25 @@ dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)
 	evdev_dlb2_default_info.max_event_ports =
 		dlb2->hw_rsrc_query_results.num_ldb_ports;
 
-	evdev_dlb2_default_info.max_num_events =
-		dlb2->hw_rsrc_query_results.num_ldb_credits;
-
+	if (dlb2->version == DLB2_HW_V2_5) {
+		evdev_dlb2_default_info.max_num_events =
+			dlb2->hw_rsrc_query_results.num_credits;
+	} else {
+		evdev_dlb2_default_info.max_num_events =
+			dlb2->hw_rsrc_query_results.num_ldb_credits;
+	}
 	/* Save off values used when creating the scheduling domain. */
 
 	handle->info.num_sched_domains =
 		dlb2->hw_rsrc_query_results.num_sched_domains;
 
-	handle->info.hw_rsrc_max.nb_events_limit =
-		dlb2->hw_rsrc_query_results.num_ldb_credits;
-
+	if (dlb2->version == DLB2_HW_V2_5) {
+		handle->info.hw_rsrc_max.nb_events_limit =
+			dlb2->hw_rsrc_query_results.num_credits;
+	} else {
+		handle->info.hw_rsrc_max.nb_events_limit =
+			dlb2->hw_rsrc_query_results.num_ldb_credits;
+	}
 	handle->info.hw_rsrc_max.num_queues =
 		dlb2->hw_rsrc_query_results.num_ldb_queues +
 		dlb2->hw_rsrc_query_results.num_dir_ports;
drivers/event/dlb2/dlb2_user.h +12 -2
index f4bda7822..b7d125dec 100644
@@ -195,9 +195,12 @@ struct dlb2_create_sched_domain_args {
  *	contiguous range of history list entries.
  * - num_ldb_credits: Amount of available load-balanced QE storage.
  * - num_dir_credits: Amount of available directed QE storage.
+ * - response.status: Detailed error code. In certain cases, such as if the
+ *	ioctl request arg is invalid, the driver won't set status.
  */
 struct dlb2_get_num_resources_args {
 	/* Output parameters */
+	struct dlb2_cmd_response response;
 	__u32 num_sched_domains;
 	__u32 num_ldb_queues;
 	__u32 num_ldb_ports;
@@ -206,8 +209,15 @@ struct dlb2_get_num_resources_args {
 	__u32 num_atomic_inflights;
 	__u32 num_hist_list_entries;
 	__u32 max_contiguous_hist_list_entries;
-	__u32 num_ldb_credits;
-	__u32 num_dir_credits;
+	union {
+		struct {
+			__u32 num_ldb_credits;
+			__u32 num_dir_credits;
+		};
+		struct {
+			__u32 num_credits;
+		};
+	};
 };
 
 /*
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -48

54 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource_new.c +66 -0

69 lines not on this page · raw message

Signature · 1 line
2.23.0
#150 lore raw

PATCH 4/25 event/dlb2: add DLB v2.5 support to create sched domain

In reply to Timothy McDaniel

Update domain creation logic to account for DLB v2.5 credit scheme, new register map, and new register access macros.

---
 drivers/event/dlb2/dlb2_user.h                |  13 +-
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 645 ----------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 696 ++++++++++++++++++
 3 files changed, 707 insertions(+), 647 deletions(-)
drivers/event/dlb2/dlb2_user.h +11 -2
index b7d125dec..9760e9bda 100644
@@ -18,6 +18,7 @@ enum dlb2_error {
 	DLB2_ST_LDB_QUEUES_UNAVAILABLE,
 	DLB2_ST_LDB_CREDITS_UNAVAILABLE,
 	DLB2_ST_DIR_CREDITS_UNAVAILABLE,
+	DLB2_ST_CREDITS_UNAVAILABLE,
 	DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE,
 	DLB2_ST_INVALID_DOMAIN_ID,
 	DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION,
@@ -57,6 +58,7 @@ static const char dlb2_error_strings[][128] = {
 	"DLB2_ST_LDB_QUEUES_UNAVAILABLE",
 	"DLB2_ST_LDB_CREDITS_UNAVAILABLE",
 	"DLB2_ST_DIR_CREDITS_UNAVAILABLE",
+	"DLB2_ST_CREDITS_UNAVAILABLE",
 	"DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE",
 	"DLB2_ST_INVALID_DOMAIN_ID",
 	"DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION",
@@ -170,8 +172,15 @@ struct dlb2_create_sched_domain_args {
 	__u32 num_dir_ports;
 	__u32 num_atomic_inflights;
 	__u32 num_hist_list_entries;
-	__u32 num_ldb_credits;
-	__u32 num_dir_credits;
+	union {
+		struct {
+			__u32 num_ldb_credits;
+			__u32 num_dir_credits;
+		};
+		struct {
+			__u32 num_credits;
+		};
+	};
 	__u8 cos_strict;
 	__u8 padding1[3];
 };
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -645

657 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource_new.c +696 -0

699 lines not on this page · raw message

Signature · 1 line
2.23.0
#151 lore raw

Re: [dpdk-dev] [PATCH 04/25] event/dlb2: add DLB v2.5 support to create sched domain

Quoted 11 lines · Timothy McDaniel

Update domain creation logic to account for DLB v2.5 credit scheme, new register map, and new register access macros.

---
 drivers/event/dlb2/dlb2_user.h                |  13 +-
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 645 ----------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 696 ++++++++++++++++++

Please use git mv foo bar to avoid creating such big diff. Wherever possible use git mv to reduce the diff in the patch.

Quoted 1,410 lines
 3 files changed, 707 insertions(+), 647 deletions(-)
drivers/event/dlb2/dlb2_user.h +11 -2
index b7d125dec..9760e9bda 100644
@@ -18,6 +18,7 @@ enum dlb2_error {
        DLB2_ST_LDB_QUEUES_UNAVAILABLE,
        DLB2_ST_LDB_CREDITS_UNAVAILABLE,
        DLB2_ST_DIR_CREDITS_UNAVAILABLE,
+       DLB2_ST_CREDITS_UNAVAILABLE,
        DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE,
        DLB2_ST_INVALID_DOMAIN_ID,
        DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION,
@@ -57,6 +58,7 @@ static const char dlb2_error_strings[][128] = {
        "DLB2_ST_LDB_QUEUES_UNAVAILABLE",
        "DLB2_ST_LDB_CREDITS_UNAVAILABLE",
        "DLB2_ST_DIR_CREDITS_UNAVAILABLE",
+       "DLB2_ST_CREDITS_UNAVAILABLE",
        "DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE",
        "DLB2_ST_INVALID_DOMAIN_ID",
        "DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION",
@@ -170,8 +172,15 @@ struct dlb2_create_sched_domain_args {
        __u32 num_dir_ports;
        __u32 num_atomic_inflights;
        __u32 num_hist_list_entries;
-       __u32 num_ldb_credits;
-       __u32 num_dir_credits;
+       union {
+               struct {
+                       __u32 num_ldb_credits;
+                       __u32 num_dir_credits;
+               };
+               struct {
+                       __u32 num_credits;
+               };
+       };
        __u8 cos_strict;
        __u8 padding1[3];
 };
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -645
index 5b8723aaf..5d296f725 100644
@@ -33,21 +33,6 @@
 #define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \
        DLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)
 
-static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)
-{
-       int i;
-
-       dlb2_list_init_head(&domain->used_ldb_queues);
-       dlb2_list_init_head(&domain->used_dir_pq_pairs);
-       dlb2_list_init_head(&domain->avail_ldb_queues);
-       dlb2_list_init_head(&domain->avail_dir_pq_pairs);
-
-       for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
-               dlb2_list_init_head(&domain->used_ldb_ports[i]);
-       for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
-               dlb2_list_init_head(&domain->avail_ldb_ports[i]);
-}
-
 void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)
 {
        union dlb2_chp_cfg_chp_csr_ctrl r0;
@@ -70,636 +55,6 @@ void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)
        DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);
 }
 
-static void dlb2_configure_domain_credits(struct dlb2_hw *hw,
-                                         struct dlb2_hw_domain *domain)
-{
-       union dlb2_chp_cfg_ldb_vas_crd r0 = { {0} };
-       union dlb2_chp_cfg_dir_vas_crd r1 = { {0} };
-
-       r0.field.count = domain->num_ldb_credits;
-
-       DLB2_CSR_WR(hw, DLB2_CHP_CFG_LDB_VAS_CRD(domain->id.phys_id), r0.val);
-
-       r1.field.count = domain->num_dir_credits;
-
-       DLB2_CSR_WR(hw, DLB2_CHP_CFG_DIR_VAS_CRD(domain->id.phys_id), r1.val);
-}
-
-static struct dlb2_ldb_port *
-dlb2_get_next_ldb_port(struct dlb2_hw *hw,
-                      struct dlb2_function_resources *rsrcs,
-                      u32 domain_id,
-                      u32 cos_id)
-{
-       struct dlb2_list_entry *iter;
-       struct dlb2_ldb_port *port;
-       RTE_SET_USED(iter);
-       /*
-        * To reduce the odds of consecutive load-balanced ports mapping to the
-        * same queue(s), the driver attempts to allocate ports whose neighbors
-        * are owned by a different domain.
-        */
-       DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
-               u32 next, prev;
-               u32 phys_id;
-
-               phys_id = port->id.phys_id;
-               next = phys_id + 1;
-               prev = phys_id - 1;
-
-               if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
-                       next = 0;
-               if (phys_id == 0)
-                       prev = DLB2_MAX_NUM_LDB_PORTS - 1;
-
-               if (!hw->rsrcs.ldb_ports[next].owned ||
-                   hw->rsrcs.ldb_ports[next].domain_id.phys_id == domain_id)
-                       continue;
-
-               if (!hw->rsrcs.ldb_ports[prev].owned ||
-                   hw->rsrcs.ldb_ports[prev].domain_id.phys_id == domain_id)
-                       continue;
-
-               return port;
-       }
-
-       /*
-        * Failing that, the driver looks for a port with one neighbor owned by
-        * a different domain and the other unallocated.
-        */
-       DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
-               u32 next, prev;
-               u32 phys_id;
-
-               phys_id = port->id.phys_id;
-               next = phys_id + 1;
-               prev = phys_id - 1;
-
-               if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
-                       next = 0;
-               if (phys_id == 0)
-                       prev = DLB2_MAX_NUM_LDB_PORTS - 1;
-
-               if (!hw->rsrcs.ldb_ports[prev].owned &&
-                   hw->rsrcs.ldb_ports[next].owned &&
-                   hw->rsrcs.ldb_ports[next].domain_id.phys_id != domain_id)
-                       return port;
-
-               if (!hw->rsrcs.ldb_ports[next].owned &&
-                   hw->rsrcs.ldb_ports[prev].owned &&
-                   hw->rsrcs.ldb_ports[prev].domain_id.phys_id != domain_id)
-                       return port;
-       }
-
-       /*
-        * Failing that, the driver looks for a port with both neighbors
-        * unallocated.
-        */
-       DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
-               u32 next, prev;
-               u32 phys_id;
-
-               phys_id = port->id.phys_id;
-               next = phys_id + 1;
-               prev = phys_id - 1;
-
-               if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
-                       next = 0;
-               if (phys_id == 0)
-                       prev = DLB2_MAX_NUM_LDB_PORTS - 1;
-
-               if (!hw->rsrcs.ldb_ports[prev].owned &&
-                   !hw->rsrcs.ldb_ports[next].owned)
-                       return port;
-       }
-
-       /* If all else fails, the driver returns the next available port. */
-       return DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_ports[cos_id],
-                                  typeof(*port));
-}
-
-static int __dlb2_attach_ldb_ports(struct dlb2_hw *hw,
-                                  struct dlb2_function_resources *rsrcs,
-                                  struct dlb2_hw_domain *domain,
-                                  u32 num_ports,
-                                  u32 cos_id,
-                                  struct dlb2_cmd_response *resp)
-{
-       unsigned int i;
-
-       if (rsrcs->num_avail_ldb_ports[cos_id] < num_ports) {
-               resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       for (i = 0; i < num_ports; i++) {
-               struct dlb2_ldb_port *port;
-
-               port = dlb2_get_next_ldb_port(hw, rsrcs,
-                                             domain->id.phys_id, cos_id);
-               if (port == NULL) {
-                       DLB2_HW_ERR(hw,
-                                   "[%s()] Internal error: domain validation failed\n",
-                                   __func__);
-                       return -EFAULT;
-               }
-
-               dlb2_list_del(&rsrcs->avail_ldb_ports[cos_id],
-                             &port->func_list);
-
-               port->domain_id = domain->id;
-               port->owned = true;
-
-               dlb2_list_add(&domain->avail_ldb_ports[cos_id],
-                             &port->domain_list);
-       }
-
-       rsrcs->num_avail_ldb_ports[cos_id] -= num_ports;
-
-       return 0;
-}
-
-static int dlb2_attach_ldb_ports(struct dlb2_hw *hw,
-                                struct dlb2_function_resources *rsrcs,
-                                struct dlb2_hw_domain *domain,
-                                struct dlb2_create_sched_domain_args *args,
-                                struct dlb2_cmd_response *resp)
-{
-       unsigned int i, j;
-       int ret;
-
-       if (args->cos_strict) {
-               for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-                       u32 num = args->num_cos_ldb_ports[i];
-
-                       /* Allocate ports from specific classes-of-service */
-                       ret = __dlb2_attach_ldb_ports(hw,
-                                                     rsrcs,
-                                                     domain,
-                                                     num,
-                                                     i,
-                                                     resp);
-                       if (ret)
-                               return ret;
-               }
-       } else {
-               unsigned int k;
-               u32 cos_id;
-
-               /*
-                * Attempt to allocate from specific class-of-service, but
-                * fallback to the other classes if that fails.
-                */
-               for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-                       for (j = 0; j < args->num_cos_ldb_ports[i]; j++) {
-                               for (k = 0; k < DLB2_NUM_COS_DOMAINS; k++) {
-                                       cos_id = (i + k) % DLB2_NUM_COS_DOMAINS;
-
-                                       ret = __dlb2_attach_ldb_ports(hw,
-                                                                     rsrcs,
-                                                                     domain,
-                                                                     1,
-                                                                     cos_id,
-                                                                     resp);
-                                       if (ret == 0)
-                                               break;
-                               }
-
-                               if (ret < 0)
-                                       return ret;
-                       }
-               }
-       }
-
-       /* Allocate num_ldb_ports from any class-of-service */
-       for (i = 0; i < args->num_ldb_ports; i++) {
-               for (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) {
-                       ret = __dlb2_attach_ldb_ports(hw,
-                                                     rsrcs,
-                                                     domain,
-                                                     1,
-                                                     j,
-                                                     resp);
-                       if (ret == 0)
-                               break;
-               }
-
-               if (ret < 0)
-                       return ret;
-       }
-
-       return 0;
-}
-
-static int dlb2_attach_dir_ports(struct dlb2_hw *hw,
-                                struct dlb2_function_resources *rsrcs,
-                                struct dlb2_hw_domain *domain,
-                                u32 num_ports,
-                                struct dlb2_cmd_response *resp)
-{
-       unsigned int i;
-
-       if (rsrcs->num_avail_dir_pq_pairs < num_ports) {
-               resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       for (i = 0; i < num_ports; i++) {
-               struct dlb2_dir_pq_pair *port;
-
-               port = DLB2_FUNC_LIST_HEAD(rsrcs->avail_dir_pq_pairs,
-                                          typeof(*port));
-               if (port == NULL) {
-                       DLB2_HW_ERR(hw,
-                                   "[%s()] Internal error: domain validation failed\n",
-                                   __func__);
-                       return -EFAULT;
-               }
-
-               dlb2_list_del(&rsrcs->avail_dir_pq_pairs, &port->func_list);
-
-               port->domain_id = domain->id;
-               port->owned = true;
-
-               dlb2_list_add(&domain->avail_dir_pq_pairs, &port->domain_list);
-       }
-
-       rsrcs->num_avail_dir_pq_pairs -= num_ports;
-
-       return 0;
-}
-
-static int dlb2_attach_ldb_credits(struct dlb2_function_resources *rsrcs,
-                                  struct dlb2_hw_domain *domain,
-                                  u32 num_credits,
-                                  struct dlb2_cmd_response *resp)
-{
-       if (rsrcs->num_avail_qed_entries < num_credits) {
-               resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       rsrcs->num_avail_qed_entries -= num_credits;
-       domain->num_ldb_credits += num_credits;
-       return 0;
-}
-
-static int dlb2_attach_dir_credits(struct dlb2_function_resources *rsrcs,
-                                  struct dlb2_hw_domain *domain,
-                                  u32 num_credits,
-                                  struct dlb2_cmd_response *resp)
-{
-       if (rsrcs->num_avail_dqed_entries < num_credits) {
-               resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       rsrcs->num_avail_dqed_entries -= num_credits;
-       domain->num_dir_credits += num_credits;
-       return 0;
-}
-
-static int dlb2_attach_atomic_inflights(struct dlb2_function_resources *rsrcs,
-                                       struct dlb2_hw_domain *domain,
-                                       u32 num_atomic_inflights,
-                                       struct dlb2_cmd_response *resp)
-{
-       if (rsrcs->num_avail_aqed_entries < num_atomic_inflights) {
-               resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       rsrcs->num_avail_aqed_entries -= num_atomic_inflights;
-       domain->num_avail_aqed_entries += num_atomic_inflights;
-       return 0;
-}
-
-static int
-dlb2_attach_domain_hist_list_entries(struct dlb2_function_resources *rsrcs,
-                                    struct dlb2_hw_domain *domain,
-                                    u32 num_hist_list_entries,
-                                    struct dlb2_cmd_response *resp)
-{
-       struct dlb2_bitmap *bitmap;
-       int base;
-
-       if (num_hist_list_entries) {
-               bitmap = rsrcs->avail_hist_list_entries;
-
-               base = dlb2_bitmap_find_set_bit_range(bitmap,
-                                                     num_hist_list_entries);
-               if (base < 0)
-                       goto error;
-
-               domain->total_hist_list_entries = num_hist_list_entries;
-               domain->avail_hist_list_entries = num_hist_list_entries;
-               domain->hist_list_entry_base = base;
-               domain->hist_list_entry_offset = 0;
-
-               dlb2_bitmap_clear_range(bitmap, base, num_hist_list_entries);
-       }
-       return 0;
-
-error:
-       resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
-       return -EINVAL;
-}
-
-static int dlb2_attach_ldb_queues(struct dlb2_hw *hw,
-                                 struct dlb2_function_resources *rsrcs,
-                                 struct dlb2_hw_domain *domain,
-                                 u32 num_queues,
-                                 struct dlb2_cmd_response *resp)
-{
-       unsigned int i;
-
-       if (rsrcs->num_avail_ldb_queues < num_queues) {
-               resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       for (i = 0; i < num_queues; i++) {
-               struct dlb2_ldb_queue *queue;
-
-               queue = DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_queues,
-                                           typeof(*queue));
-               if (queue == NULL) {
-                       DLB2_HW_ERR(hw,
-                                   "[%s()] Internal error: domain validation failed\n",
-                                   __func__);
-                       return -EFAULT;
-               }
-
-               dlb2_list_del(&rsrcs->avail_ldb_queues, &queue->func_list);
-
-               queue->domain_id = domain->id;
-               queue->owned = true;
-
-               dlb2_list_add(&domain->avail_ldb_queues, &queue->domain_list);
-       }
-
-       rsrcs->num_avail_ldb_queues -= num_queues;
-
-       return 0;
-}
-
-static int
-dlb2_domain_attach_resources(struct dlb2_hw *hw,
-                            struct dlb2_function_resources *rsrcs,
-                            struct dlb2_hw_domain *domain,
-                            struct dlb2_create_sched_domain_args *args,
-                            struct dlb2_cmd_response *resp)
-{
-       int ret;
-
-       ret = dlb2_attach_ldb_queues(hw,
-                                    rsrcs,
-                                    domain,
-                                    args->num_ldb_queues,
-                                    resp);
-       if (ret < 0)
-               return ret;
-
-       ret = dlb2_attach_ldb_ports(hw,
-                                   rsrcs,
-                                   domain,
-                                   args,
-                                   resp);
-       if (ret < 0)
-               return ret;
-
-       ret = dlb2_attach_dir_ports(hw,
-                                   rsrcs,
-                                   domain,
-                                   args->num_dir_ports,
-                                   resp);
-       if (ret < 0)
-               return ret;
-
-       ret = dlb2_attach_ldb_credits(rsrcs,
-                                     domain,
-                                     args->num_ldb_credits,
-                                     resp);
-       if (ret < 0)
-               return ret;
-
-       ret = dlb2_attach_dir_credits(rsrcs,
-                                     domain,
-                                     args->num_dir_credits,
-                                     resp);
-       if (ret < 0)
-               return ret;
-
-       ret = dlb2_attach_domain_hist_list_entries(rsrcs,
-                                                  domain,
-                                                  args->num_hist_list_entries,
-                                                  resp);
-       if (ret < 0)
-               return ret;
-
-       ret = dlb2_attach_atomic_inflights(rsrcs,
-                                          domain,
-                                          args->num_atomic_inflights,
-                                          resp);
-       if (ret < 0)
-               return ret;
-
-       dlb2_configure_domain_credits(hw, domain);
-
-       domain->configured = true;
-
-       domain->started = false;
-
-       rsrcs->num_avail_domains--;
-
-       return 0;
-}
-
-static int
-dlb2_verify_create_sched_dom_args(struct dlb2_function_resources *rsrcs,
-                                 struct dlb2_create_sched_domain_args *args,
-                                 struct dlb2_cmd_response *resp)
-{
-       u32 num_avail_ldb_ports, req_ldb_ports;
-       struct dlb2_bitmap *avail_hl_entries;
-       unsigned int max_contig_hl_range;
-       int i;
-
-       avail_hl_entries = rsrcs->avail_hist_list_entries;
-
-       max_contig_hl_range = dlb2_bitmap_longest_set_range(avail_hl_entries);
-
-       num_avail_ldb_ports = 0;
-       req_ldb_ports = 0;
-       for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-               num_avail_ldb_ports += rsrcs->num_avail_ldb_ports[i];
-
-               req_ldb_ports += args->num_cos_ldb_ports[i];
-       }
-
-       req_ldb_ports += args->num_ldb_ports;
-
-       if (rsrcs->num_avail_domains < 1) {
-               resp->status = DLB2_ST_DOMAIN_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       if (rsrcs->num_avail_ldb_queues < args->num_ldb_queues) {
-               resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       if (req_ldb_ports > num_avail_ldb_ports) {
-               resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       for (i = 0; args->cos_strict && i < DLB2_NUM_COS_DOMAINS; i++) {
-               if (args->num_cos_ldb_ports[i] >
-                   rsrcs->num_avail_ldb_ports[i]) {
-                       resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
-                       return -EINVAL;
-               }
-       }
-
-       if (args->num_ldb_queues > 0 && req_ldb_ports == 0) {
-               resp->status = DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES;
-               return -EINVAL;
-       }
-
-       if (rsrcs->num_avail_dir_pq_pairs < args->num_dir_ports) {
-               resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       if (rsrcs->num_avail_qed_entries < args->num_ldb_credits) {
-               resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       if (rsrcs->num_avail_dqed_entries < args->num_dir_credits) {
-               resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       if (rsrcs->num_avail_aqed_entries < args->num_atomic_inflights) {
-               resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       if (max_contig_hl_range < args->num_hist_list_entries) {
-               resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static void
-dlb2_log_create_sched_domain_args(struct dlb2_hw *hw,
-                                 struct dlb2_create_sched_domain_args *args,
-                                 bool vdev_req,
-                                 unsigned int vdev_id)
-{
-       DLB2_HW_DBG(hw, "DLB2 create sched domain arguments:\n");
-       if (vdev_req)
-               DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-       DLB2_HW_DBG(hw, "\tNumber of LDB queues:          %d\n",
-                   args->num_ldb_queues);
-       DLB2_HW_DBG(hw, "\tNumber of LDB ports (any CoS): %d\n",
-                   args->num_ldb_ports);
-       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 0):   %d\n",
-                   args->num_cos_ldb_ports[0]);
-       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 1):   %d\n",
-                   args->num_cos_ldb_ports[1]);
-       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 2):   %d\n",
-                   args->num_cos_ldb_ports[1]);
-       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 3):   %d\n",
-                   args->num_cos_ldb_ports[1]);
-       DLB2_HW_DBG(hw, "\tStrict CoS allocation:         %d\n",
-                   args->cos_strict);
-       DLB2_HW_DBG(hw, "\tNumber of DIR ports:           %d\n",
-                   args->num_dir_ports);
-       DLB2_HW_DBG(hw, "\tNumber of ATM inflights:       %d\n",
-                   args->num_atomic_inflights);
-       DLB2_HW_DBG(hw, "\tNumber of hist list entries:   %d\n",
-                   args->num_hist_list_entries);
-       DLB2_HW_DBG(hw, "\tNumber of LDB credits:         %d\n",
-                   args->num_ldb_credits);
-       DLB2_HW_DBG(hw, "\tNumber of DIR credits:         %d\n",
-                   args->num_dir_credits);
-}
-
-/**
- * dlb2_hw_create_sched_domain() - Allocate and initialize a DLB scheduling
- *     domain and its resources.
- * @hw:        Contains the current state of the DLB2 hardware.
- * @args: User-provided arguments.
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int dlb2_hw_create_sched_domain(struct dlb2_hw *hw,
-                               struct dlb2_create_sched_domain_args *args,
-                               struct dlb2_cmd_response *resp,
-                               bool vdev_req,
-                               unsigned int vdev_id)
-{
-       struct dlb2_function_resources *rsrcs;
-       struct dlb2_hw_domain *domain;
-       int ret;
-
-       rsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;
-
-       dlb2_log_create_sched_domain_args(hw, args, vdev_req, vdev_id);
-
-       /*
-        * Verify that hardware resources are available before attempting to
-        * satisfy the request. This simplifies the error unwinding code.
-        */
-       ret = dlb2_verify_create_sched_dom_args(rsrcs, args, resp);
-       if (ret)
-               return ret;
-
-       domain = DLB2_FUNC_LIST_HEAD(rsrcs->avail_domains, typeof(*domain));
-       if (domain == NULL) {
-               DLB2_HW_ERR(hw,
-                           "[%s():%d] Internal error: no available domains\n",
-                           __func__, __LINE__);
-               return -EFAULT;
-       }
-
-       if (domain->configured) {
-               DLB2_HW_ERR(hw,
-                           "[%s()] Internal error: avail_domains contains configured domains.\n",
-                           __func__);
-               return -EFAULT;
-       }
-
-       dlb2_init_domain_rsrc_lists(domain);
-
-       ret = dlb2_domain_attach_resources(hw, rsrcs, domain, args, resp);
-       if (ret < 0) {
-               DLB2_HW_ERR(hw,
-                           "[%s()] Internal error: failed to verify args.\n",
-                           __func__);
-
-               return ret;
-       }
-
-       dlb2_list_del(&rsrcs->avail_domains, &domain->func_list);
-
-       dlb2_list_add(&rsrcs->used_domains, &domain->func_list);
-
-       resp->id = (vdev_req) ? domain->id.virt_id : domain->id.phys_id;
-       resp->status = 0;
-
-       return 0;
-}
-
 /*
  * The PF driver cannot assume that a register write will affect subsequent HCW
  * writes. To ensure a write completes, the driver must read back a CSR. This
drivers/event/dlb2/pf/base/dlb2_resource_new.c +696 -1
index b0fd37a55..4d679a0a9 100644
@@ -335,3 +335,699 @@ int dlb2_hw_get_num_resources(struct dlb2_hw *hw,
        }
        return 0;
 }
+
+static void dlb2_configure_domain_credits_v2_5(struct dlb2_hw *hw,
+                                              struct dlb2_hw_domain *domain)
+{
+       u32 reg = 0;
+
+       DLB2_BITS_SET(reg, domain->num_credits, DLB2_CHP_CFG_LDB_VAS_CRD_COUNT);
+       DLB2_CSR_WR(hw, DLB2_CHP_CFG_VAS_CRD(domain->id.phys_id), reg);
+}
+
+static void dlb2_configure_domain_credits_v2(struct dlb2_hw *hw,
+                                            struct dlb2_hw_domain *domain)
+{
+       u32 reg = 0;
+
+       DLB2_BITS_SET(reg, domain->num_ldb_credits,
+                     DLB2_CHP_CFG_LDB_VAS_CRD_COUNT);
+       DLB2_CSR_WR(hw, DLB2_CHP_CFG_LDB_VAS_CRD(domain->id.phys_id), reg);
+
+       reg = 0;
+       DLB2_BITS_SET(reg, domain->num_dir_credits,
+                     DLB2_CHP_CFG_DIR_VAS_CRD_COUNT);
+       DLB2_CSR_WR(hw, DLB2_CHP_CFG_DIR_VAS_CRD(domain->id.phys_id), reg);
+}
+
+static void dlb2_configure_domain_credits(struct dlb2_hw *hw,
+                                         struct dlb2_hw_domain *domain)
+{
+       if (hw->ver == DLB2_HW_V2)
+               dlb2_configure_domain_credits_v2(hw, domain);
+       else
+               dlb2_configure_domain_credits_v2_5(hw, domain);
+}
+
+static int dlb2_attach_credits(struct dlb2_function_resources *rsrcs,
+                              struct dlb2_hw_domain *domain,
+                              u32 num_credits,
+                              struct dlb2_cmd_response *resp)
+{
+       if (rsrcs->num_avail_entries < num_credits) {
+               resp->status = DLB2_ST_CREDITS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       rsrcs->num_avail_entries -= num_credits;
+       domain->num_credits += num_credits;
+       return 0;
+}
+
+static struct dlb2_ldb_port *
+dlb2_get_next_ldb_port(struct dlb2_hw *hw,
+                      struct dlb2_function_resources *rsrcs,
+                      u32 domain_id,
+                      u32 cos_id)
+{
+       struct dlb2_list_entry *iter;
+       struct dlb2_ldb_port *port;
+       RTE_SET_USED(iter);
+
+       /*
+        * To reduce the odds of consecutive load-balanced ports mapping to the
+        * same queue(s), the driver attempts to allocate ports whose neighbors
+        * are owned by a different domain.
+        */
+       DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
+               u32 next, prev;
+               u32 phys_id;
+
+               phys_id = port->id.phys_id;
+               next = phys_id + 1;
+               prev = phys_id - 1;
+
+               if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
+                       next = 0;
+               if (phys_id == 0)
+                       prev = DLB2_MAX_NUM_LDB_PORTS - 1;
+
+               if (!hw->rsrcs.ldb_ports[next].owned ||
+                   hw->rsrcs.ldb_ports[next].domain_id.phys_id == domain_id)
+                       continue;
+
+               if (!hw->rsrcs.ldb_ports[prev].owned ||
+                   hw->rsrcs.ldb_ports[prev].domain_id.phys_id == domain_id)
+                       continue;
+
+               return port;
+       }
+
+       /*
+        * Failing that, the driver looks for a port with one neighbor owned by
+        * a different domain and the other unallocated.
+        */
+       DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
+               u32 next, prev;
+               u32 phys_id;
+
+               phys_id = port->id.phys_id;
+               next = phys_id + 1;
+               prev = phys_id - 1;
+
+               if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
+                       next = 0;
+               if (phys_id == 0)
+                       prev = DLB2_MAX_NUM_LDB_PORTS - 1;
+
+               if (!hw->rsrcs.ldb_ports[prev].owned &&
+                   hw->rsrcs.ldb_ports[next].owned &&
+                   hw->rsrcs.ldb_ports[next].domain_id.phys_id != domain_id)
+                       return port;
+
+               if (!hw->rsrcs.ldb_ports[next].owned &&
+                   hw->rsrcs.ldb_ports[prev].owned &&
+                   hw->rsrcs.ldb_ports[prev].domain_id.phys_id != domain_id)
+                       return port;
+       }
+
+       /*
+        * Failing that, the driver looks for a port with both neighbors
+        * unallocated.
+        */
+       DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
+               u32 next, prev;
+               u32 phys_id;
+
+               phys_id = port->id.phys_id;
+               next = phys_id + 1;
+               prev = phys_id - 1;
+
+               if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
+                       next = 0;
+               if (phys_id == 0)
+                       prev = DLB2_MAX_NUM_LDB_PORTS - 1;
+
+               if (!hw->rsrcs.ldb_ports[prev].owned &&
+                   !hw->rsrcs.ldb_ports[next].owned)
+                       return port;
+       }
+
+       /* If all else fails, the driver returns the next available port. */
+       return DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_ports[cos_id],
+                                  typeof(*port));
+}
+
+static int __dlb2_attach_ldb_ports(struct dlb2_hw *hw,
+                                  struct dlb2_function_resources *rsrcs,
+                                  struct dlb2_hw_domain *domain,
+                                  u32 num_ports,
+                                  u32 cos_id,
+                                  struct dlb2_cmd_response *resp)
+{
+       unsigned int i;
+
+       if (rsrcs->num_avail_ldb_ports[cos_id] < num_ports) {
+               resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       for (i = 0; i < num_ports; i++) {
+               struct dlb2_ldb_port *port;
+
+               port = dlb2_get_next_ldb_port(hw, rsrcs,
+                                             domain->id.phys_id, cos_id);
+               if (port == NULL) {
+                       DLB2_HW_ERR(hw,
+                                   "[%s()] Internal error: domain validation failed\n",
+                                   __func__);
+                       return -EFAULT;
+               }
+
+               dlb2_list_del(&rsrcs->avail_ldb_ports[cos_id],
+                             &port->func_list);
+
+               port->domain_id = domain->id;
+               port->owned = true;
+
+               dlb2_list_add(&domain->avail_ldb_ports[cos_id],
+                             &port->domain_list);
+       }
+
+       rsrcs->num_avail_ldb_ports[cos_id] -= num_ports;
+
+       return 0;
+}
+
+
+static int dlb2_attach_ldb_ports(struct dlb2_hw *hw,
+                                struct dlb2_function_resources *rsrcs,
+                                struct dlb2_hw_domain *domain,
+                                struct dlb2_create_sched_domain_args *args,
+                                struct dlb2_cmd_response *resp)
+{
+       unsigned int i, j;
+       int ret;
+
+       if (args->cos_strict) {
+               for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+                       u32 num = args->num_cos_ldb_ports[i];
+
+                       /* Allocate ports from specific classes-of-service */
+                       ret = __dlb2_attach_ldb_ports(hw,
+                                                     rsrcs,
+                                                     domain,
+                                                     num,
+                                                     i,
+                                                     resp);
+                       if (ret)
+                               return ret;
+               }
+       } else {
+               unsigned int k;
+               u32 cos_id;
+
+               /*
+                * Attempt to allocate from specific class-of-service, but
+                * fallback to the other classes if that fails.
+                */
+               for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+                       for (j = 0; j < args->num_cos_ldb_ports[i]; j++) {
+                               for (k = 0; k < DLB2_NUM_COS_DOMAINS; k++) {
+                                       cos_id = (i + k) % DLB2_NUM_COS_DOMAINS;
+
+                                       ret = __dlb2_attach_ldb_ports(hw,
+                                                                     rsrcs,
+                                                                     domain,
+                                                                     1,
+                                                                     cos_id,
+                                                                     resp);
+                                       if (ret == 0)
+                                               break;
+                               }
+
+                               if (ret)
+                                       return ret;
+                       }
+               }
+       }
+
+       /* Allocate num_ldb_ports from any class-of-service */
+       for (i = 0; i < args->num_ldb_ports; i++) {
+               for (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) {
+                       ret = __dlb2_attach_ldb_ports(hw,
+                                                     rsrcs,
+                                                     domain,
+                                                     1,
+                                                     j,
+                                                     resp);
+                       if (ret == 0)
+                               break;
+               }
+
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+static int dlb2_attach_dir_ports(struct dlb2_hw *hw,
+                                struct dlb2_function_resources *rsrcs,
+                                struct dlb2_hw_domain *domain,
+                                u32 num_ports,
+                                struct dlb2_cmd_response *resp)
+{
+       unsigned int i;
+
+       if (rsrcs->num_avail_dir_pq_pairs < num_ports) {
+               resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       for (i = 0; i < num_ports; i++) {
+               struct dlb2_dir_pq_pair *port;
+
+               port = DLB2_FUNC_LIST_HEAD(rsrcs->avail_dir_pq_pairs,
+                                          typeof(*port));
+               if (port == NULL) {
+                       DLB2_HW_ERR(hw,
+                                   "[%s()] Internal error: domain validation failed\n",
+                                   __func__);
+                       return -EFAULT;
+               }
+
+               dlb2_list_del(&rsrcs->avail_dir_pq_pairs, &port->func_list);
+
+               port->domain_id = domain->id;
+               port->owned = true;
+
+               dlb2_list_add(&domain->avail_dir_pq_pairs, &port->domain_list);
+       }
+
+       rsrcs->num_avail_dir_pq_pairs -= num_ports;
+
+       return 0;
+}
+
+static int dlb2_attach_ldb_credits(struct dlb2_function_resources *rsrcs,
+                                  struct dlb2_hw_domain *domain,
+                                  u32 num_credits,
+                                  struct dlb2_cmd_response *resp)
+{
+       if (rsrcs->num_avail_qed_entries < num_credits) {
+               resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       rsrcs->num_avail_qed_entries -= num_credits;
+       domain->num_ldb_credits += num_credits;
+       return 0;
+}
+
+static int dlb2_attach_dir_credits(struct dlb2_function_resources *rsrcs,
+                                  struct dlb2_hw_domain *domain,
+                                  u32 num_credits,
+                                  struct dlb2_cmd_response *resp)
+{
+       if (rsrcs->num_avail_dqed_entries < num_credits) {
+               resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       rsrcs->num_avail_dqed_entries -= num_credits;
+       domain->num_dir_credits += num_credits;
+       return 0;
+}
+
+
+static int dlb2_attach_atomic_inflights(struct dlb2_function_resources *rsrcs,
+                                       struct dlb2_hw_domain *domain,
+                                       u32 num_atomic_inflights,
+                                       struct dlb2_cmd_response *resp)
+{
+       if (rsrcs->num_avail_aqed_entries < num_atomic_inflights) {
+               resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       rsrcs->num_avail_aqed_entries -= num_atomic_inflights;
+       domain->num_avail_aqed_entries += num_atomic_inflights;
+       return 0;
+}
+
+static int
+dlb2_attach_domain_hist_list_entries(struct dlb2_function_resources *rsrcs,
+                                    struct dlb2_hw_domain *domain,
+                                    u32 num_hist_list_entries,
+                                    struct dlb2_cmd_response *resp)
+{
+       struct dlb2_bitmap *bitmap;
+       int base;
+
+       if (num_hist_list_entries) {
+               bitmap = rsrcs->avail_hist_list_entries;
+
+               base = dlb2_bitmap_find_set_bit_range(bitmap,
+                                                     num_hist_list_entries);
+               if (base < 0)
+                       goto error;
+
+               domain->total_hist_list_entries = num_hist_list_entries;
+               domain->avail_hist_list_entries = num_hist_list_entries;
+               domain->hist_list_entry_base = base;
+               domain->hist_list_entry_offset = 0;
+
+               dlb2_bitmap_clear_range(bitmap, base, num_hist_list_entries);
+       }
+       return 0;
+
+error:
+       resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
+       return -EINVAL;
+}
+
+static int dlb2_attach_ldb_queues(struct dlb2_hw *hw,
+                                 struct dlb2_function_resources *rsrcs,
+                                 struct dlb2_hw_domain *domain,
+                                 u32 num_queues,
+                                 struct dlb2_cmd_response *resp)
+{
+       unsigned int i;
+
+       if (rsrcs->num_avail_ldb_queues < num_queues) {
+               resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       for (i = 0; i < num_queues; i++) {
+               struct dlb2_ldb_queue *queue;
+
+               queue = DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_queues,
+                                           typeof(*queue));
+               if (queue == NULL) {
+                       DLB2_HW_ERR(hw,
+                                   "[%s()] Internal error: domain validation failed\n",
+                                   __func__);
+                       return -EFAULT;
+               }
+
+               dlb2_list_del(&rsrcs->avail_ldb_queues, &queue->func_list);
+
+               queue->domain_id = domain->id;
+               queue->owned = true;
+
+               dlb2_list_add(&domain->avail_ldb_queues, &queue->domain_list);
+       }
+
+       rsrcs->num_avail_ldb_queues -= num_queues;
+
+       return 0;
+}
+
+static int
+dlb2_domain_attach_resources(struct dlb2_hw *hw,
+                            struct dlb2_function_resources *rsrcs,
+                            struct dlb2_hw_domain *domain,
+                            struct dlb2_create_sched_domain_args *args,
+                            struct dlb2_cmd_response *resp)
+{
+       int ret;
+
+       ret = dlb2_attach_ldb_queues(hw,
+                                    rsrcs,
+                                    domain,
+                                    args->num_ldb_queues,
+                                    resp);
+       if (ret)
+               return ret;
+
+       ret = dlb2_attach_ldb_ports(hw,
+                                   rsrcs,
+                                   domain,
+                                   args,
+                                   resp);
+       if (ret)
+               return ret;
+
+       ret = dlb2_attach_dir_ports(hw,
+                                   rsrcs,
+                                   domain,
+                                   args->num_dir_ports,
+                                   resp);
+       if (ret)
+               return ret;
+
+       if (hw->ver == DLB2_HW_V2) {
+               ret = dlb2_attach_ldb_credits(rsrcs,
+                                             domain,
+                                             args->num_ldb_credits,
+                                             resp);
+               if (ret)
+                       return ret;
+
+               ret = dlb2_attach_dir_credits(rsrcs,
+                                             domain,
+                                             args->num_dir_credits,
+                                             resp);
+               if (ret)
+                       return ret;
+       } else {  /* DLB 2.5 */
+               ret = dlb2_attach_credits(rsrcs,
+                                         domain,
+                                         args->num_credits,
+                                         resp);
+               if (ret)
+                       return ret;
+       }
+
+       ret = dlb2_attach_domain_hist_list_entries(rsrcs,
+                                                  domain,
+                                                  args->num_hist_list_entries,
+                                                  resp);
+       if (ret)
+               return ret;
+
+       ret = dlb2_attach_atomic_inflights(rsrcs,
+                                          domain,
+                                          args->num_atomic_inflights,
+                                          resp);
+       if (ret)
+               return ret;
+
+       dlb2_configure_domain_credits(hw, domain);
+
+       domain->configured = true;
+
+       domain->started = false;
+
+       rsrcs->num_avail_domains--;
+
+       return 0;
+}
+
+static int
+dlb2_verify_create_sched_dom_args(struct dlb2_function_resources *rsrcs,
+                                 struct dlb2_create_sched_domain_args *args,
+                                 struct dlb2_cmd_response *resp,
+                                 struct dlb2_hw *hw,
+                                 struct dlb2_hw_domain **out_domain)
+{
+       u32 num_avail_ldb_ports, req_ldb_ports;
+       struct dlb2_bitmap *avail_hl_entries;
+       unsigned int max_contig_hl_range;
+       struct dlb2_hw_domain *domain;
+       int i;
+
+       avail_hl_entries = rsrcs->avail_hist_list_entries;
+
+       max_contig_hl_range = dlb2_bitmap_longest_set_range(avail_hl_entries);
+
+       num_avail_ldb_ports = 0;
+       req_ldb_ports = 0;
+       for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+               num_avail_ldb_ports += rsrcs->num_avail_ldb_ports[i];
+
+               req_ldb_ports += args->num_cos_ldb_ports[i];
+       }
+
+       req_ldb_ports += args->num_ldb_ports;
+
+       if (rsrcs->num_avail_domains < 1) {
+               resp->status = DLB2_ST_DOMAIN_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       domain = DLB2_FUNC_LIST_HEAD(rsrcs->avail_domains, typeof(*domain));
+       if (domain == NULL) {
+               resp->status = DLB2_ST_DOMAIN_UNAVAILABLE;
+               return -EFAULT;
+       }
+
+       if (rsrcs->num_avail_ldb_queues < args->num_ldb_queues) {
+               resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       if (req_ldb_ports > num_avail_ldb_ports) {
+               resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       for (i = 0; args->cos_strict && i < DLB2_NUM_COS_DOMAINS; i++) {
+               if (args->num_cos_ldb_ports[i] >
+                   rsrcs->num_avail_ldb_ports[i]) {
+                       resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+                       return -EINVAL;
+               }
+       }
+
+       if (args->num_ldb_queues > 0 && req_ldb_ports == 0) {
+               resp->status = DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES;
+               return -EINVAL;
+       }
+
+       if (rsrcs->num_avail_dir_pq_pairs < args->num_dir_ports) {
+               resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
+               return -EINVAL;
+       }
+       if (hw->ver == DLB2_HW_V2_5) {
+               if (rsrcs->num_avail_entries < args->num_credits) {
+                       resp->status = DLB2_ST_CREDITS_UNAVAILABLE;
+                       return -EINVAL;
+               }
+       } else {
+               if (rsrcs->num_avail_qed_entries < args->num_ldb_credits) {
+                       resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
+                       return -EINVAL;
+               }
+               if (rsrcs->num_avail_dqed_entries < args->num_dir_credits) {
+                       resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
+                       return -EINVAL;
+               }
+       }
+
+       if (rsrcs->num_avail_aqed_entries < args->num_atomic_inflights) {
+               resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       if (max_contig_hl_range < args->num_hist_list_entries) {
+               resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
+               return -EINVAL;
+       }
+
+       *out_domain = domain;
+
+       return 0;
+}
+
+static void
+dlb2_log_create_sched_domain_args(struct dlb2_hw *hw,
+                                 struct dlb2_create_sched_domain_args *args,
+                                 bool vdev_req,
+                                 unsigned int vdev_id)
+{
+       DLB2_HW_DBG(hw, "DLB2 create sched domain arguments:\n");
+       if (vdev_req)
+               DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
+       DLB2_HW_DBG(hw, "\tNumber of LDB queues:          %d\n",
+                   args->num_ldb_queues);
+       DLB2_HW_DBG(hw, "\tNumber of LDB ports (any CoS): %d\n",
+                   args->num_ldb_ports);
+       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 0):   %d\n",
+                   args->num_cos_ldb_ports[0]);
+       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 1):   %d\n",
+                   args->num_cos_ldb_ports[1]);
+       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 2):   %d\n",
+                   args->num_cos_ldb_ports[2]);
+       DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 3):   %d\n",
+                   args->num_cos_ldb_ports[3]);
+       DLB2_HW_DBG(hw, "\tStrict CoS allocation:         %d\n",
+                   args->cos_strict);
+       DLB2_HW_DBG(hw, "\tNumber of DIR ports:           %d\n",
+                   args->num_dir_ports);
+       DLB2_HW_DBG(hw, "\tNumber of ATM inflights:       %d\n",
+                   args->num_atomic_inflights);
+       DLB2_HW_DBG(hw, "\tNumber of hist list entries:   %d\n",
+                   args->num_hist_list_entries);
+       if (hw->ver == DLB2_HW_V2) {
+               DLB2_HW_DBG(hw, "\tNumber of LDB credits:         %d\n",
+                           args->num_ldb_credits);
+               DLB2_HW_DBG(hw, "\tNumber of DIR credits:         %d\n",
+                           args->num_dir_credits);
+       } else {
+               DLB2_HW_DBG(hw, "\tNumber of credits:         %d\n",
+                           args->num_credits);
+       }
+}
+
+/**
+ * dlb2_hw_create_sched_domain() - create a scheduling domain
+ * @hw: dlb2_hw handle for a particular device.
+ * @args: scheduling domain creation arguments.
+ * @resp: response structure.
+ * @vdev_req: indicates whether this request came from a vdev.
+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.
+ *
+ * This function creates a scheduling domain containing the resources specified
+ * in args. The individual resources (queues, ports, credits) can be configured
+ * after creating a scheduling domain.
+ *
+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual
+ * device.
+ *
+ * Return:
+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is
+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id
+ * contains the domain ID.
+ *
+ * resp->id contains a virtual ID if vdev_req is true.
+ *
+ * Errors:
+ * EINVAL - A requested resource is unavailable, or the requested domain name
+ *         is already in use.
+ * EFAULT - Internal error (resp->status not set).
+ */
+int dlb2_hw_create_sched_domain(struct dlb2_hw *hw,
+                               struct dlb2_create_sched_domain_args *args,
+                               struct dlb2_cmd_response *resp,
+                               bool vdev_req,
+                               unsigned int vdev_id)
+{
+       struct dlb2_function_resources *rsrcs;
+       struct dlb2_hw_domain *domain;
+       int ret;
+
+       rsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;
+
+       dlb2_log_create_sched_domain_args(hw, args, vdev_req, vdev_id);
+
+       /*
+        * Verify that hardware resources are available before attempting to
+        * satisfy the request. This simplifies the error unwinding code.
+        */
+       ret = dlb2_verify_create_sched_dom_args(rsrcs, args, resp, hw, &domain);
+       if (ret)
+               return ret;
+
+       dlb2_init_domain_rsrc_lists(domain);
+
+       ret = dlb2_domain_attach_resources(hw, rsrcs, domain, args, resp);
+       if (ret) {
+               DLB2_HW_ERR(hw,
+                           "[%s()] Internal error: failed to verify args.\n",
+                           __func__);
+
+               return ret;
+       }
+
+       dlb2_list_del(&rsrcs->avail_domains, &domain->func_list);
+
+       dlb2_list_add(&rsrcs->used_domains, &domain->func_list);
+
+       resp->id = (vdev_req) ? domain->id.virt_id : domain->id.phys_id;
+       resp->status = 0;
+
+       return 0;
+}
--

2.23.0

#152 lore raw

PATCH 5/25 event/dlb2: add DLB v2.5 support to domain reset

In reply to Timothy McDaniel

Convert to new register map and new register access macros.

---
 .../event/dlb2/pf/base/dlb2_hw_types_new.h    |    1 +
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 1494 ----------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 2551 +++++++++++++++++
 3 files changed, 2552 insertions(+), 1494 deletions(-)
drivers/event/dlb2/pf/base/dlb2_hw_types_new.h +1 -0
index d58aa94ad..0f418ef5d 100644
@@ -187,6 +187,7 @@ struct dlb2_ldb_port {
 	u32 hist_list_entry_base;
 	u32 hist_list_entry_limit;
 	u32 ref_cnt;
+	u8 cq_depth;
 	u8 init_tkn_cnt;
 	u8 num_pending_removals;
 	u8 num_mappings;
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -1494

1,530 lines not on this page · raw message

drivers/event/dlb2/pf/base/dlb2_resource_new.c +2551 -0

1,463 lines not on this page · raw message

The rest of this diff is not shown. View the raw message.

Signature · 1 line
2.23.0

Part of the diff is not shown here. View the raw message.

#153 lore raw

PATCH 6/25 event/dlb2: add DLB V2.5 support to create ldb queue

In reply to Timothy McDaniel

Updated low level hardware functions to add DLB 2.5 support for creating load balanced queues.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 397 ------------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 391 +++++++++++++++++
 2 files changed, 391 insertions(+), 397 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -397
index 830c74d0a..5a8251ee0 100644
@@ -1150,403 +1150,6 @@ unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)
 	return num;
 }
 
-
-static void dlb2_configure_ldb_queue(struct dlb2_hw *hw,
-				     struct dlb2_hw_domain *domain,
-				     struct dlb2_ldb_queue *queue,
-				     struct dlb2_create_ldb_queue_args *args,
-				     bool vdev_req,
-				     unsigned int vdev_id)
-{
-	union dlb2_sys_vf_ldb_vqid_v r0 = { {0} };
-	union dlb2_sys_vf_ldb_vqid2qid r1 = { {0} };
-	union dlb2_sys_ldb_qid2vqid r2 = { {0} };
-	union dlb2_sys_ldb_vasqid_v r3 = { {0} };
-	union dlb2_lsp_qid_ldb_infl_lim r4 = { {0} };
-	union dlb2_lsp_qid_aqed_active_lim r5 = { {0} };
-	union dlb2_aqed_pipe_qid_hid_width r6 = { {0} };
-	union dlb2_sys_ldb_qid_its r7 = { {0} };
-	union dlb2_lsp_qid_atm_depth_thrsh r8 = { {0} };
-	union dlb2_lsp_qid_naldb_depth_thrsh r9 = { {0} };
-	union dlb2_aqed_pipe_qid_fid_lim r10 = { {0} };
-	union dlb2_chp_ord_qid_sn_map r11 = { {0} };
-	union dlb2_sys_ldb_qid_cfg_v r12 = { {0} };
-	union dlb2_sys_ldb_qid_v r13 = { {0} };
-
-	struct dlb2_sn_group *sn_group;
-	unsigned int offs;
-
-	/* QID write permissions are turned on when the domain is started */
-	r3.field.vasqid_v = 0;
-
-	offs = domain->id.phys_id * DLB2_MAX_NUM_LDB_QUEUES +
-		queue->id.phys_id;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_VASQID_V(offs), r3.val);
-
-	/*
-	 * Unordered QIDs get 4K inflights, ordered get as many as the number
-	 * of sequence numbers.
-	 */
-	r4.field.limit = args->num_qid_inflights;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), r4.val);
-
-	r5.field.limit = queue->aqed_limit;
-
-	if (r5.field.limit > DLB2_MAX_NUM_AQED_ENTRIES)
-		r5.field.limit = DLB2_MAX_NUM_AQED_ENTRIES;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID_AQED_ACTIVE_LIM(queue->id.phys_id),
-		    r5.val);
-
-	switch (args->lock_id_comp_level) {
-	case 64:
-		r6.field.compress_code = 1;
-		break;
-	case 128:
-		r6.field.compress_code = 2;
-		break;
-	case 256:
-		r6.field.compress_code = 3;
-		break;
-	case 512:
-		r6.field.compress_code = 4;
-		break;
-	case 1024:
-		r6.field.compress_code = 5;
-		break;
-	case 2048:
-		r6.field.compress_code = 6;
-		break;
-	case 4096:
-		r6.field.compress_code = 7;
-		break;
-	case 0:
-	case 65536:
-		r6.field.compress_code = 0;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_AQED_PIPE_QID_HID_WIDTH(queue->id.phys_id),
-		    r6.val);
-
-	/* Don't timestamp QEs that pass through this queue */
-	r7.field.qid_its = 0;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_SYS_LDB_QID_ITS(queue->id.phys_id),
-		    r7.val);
-
-	r8.field.thresh = args->depth_threshold;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID_ATM_DEPTH_THRSH(queue->id.phys_id),
-		    r8.val);
-
-	r9.field.thresh = args->depth_threshold;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID_NALDB_DEPTH_THRSH(queue->id.phys_id),
-		    r9.val);
-
-	/*
-	 * This register limits the number of inflight flows a queue can have
-	 * at one time.  It has an upper bound of 2048, but can be
-	 * over-subscribed. 512 is chosen so that a single queue doesn't use
-	 * the entire atomic storage, but can use a substantial portion if
-	 * needed.
-	 */
-	r10.field.qid_fid_limit = 512;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_AQED_PIPE_QID_FID_LIM(queue->id.phys_id),
-		    r10.val);
-
-	/* Configure SNs */
-	sn_group = &hw->rsrcs.sn_groups[queue->sn_group];
-	r11.field.mode = sn_group->mode;
-	r11.field.slot = queue->sn_slot;
-	r11.field.grp  = sn_group->id;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_ORD_QID_SN_MAP(queue->id.phys_id), r11.val);
-
-	r12.field.sn_cfg_v = (args->num_sequence_numbers != 0);
-	r12.field.fid_cfg_v = (args->num_atomic_inflights != 0);
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_CFG_V(queue->id.phys_id), r12.val);
-
-	if (vdev_req) {
-		offs = vdev_id * DLB2_MAX_NUM_LDB_QUEUES + queue->id.virt_id;
-
-		r0.field.vqid_v = 1;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VQID_V(offs), r0.val);
-
-		r1.field.qid = queue->id.phys_id;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VQID2QID(offs), r1.val);
-
-		r2.field.vqid = queue->id.virt_id;
-
-		DLB2_CSR_WR(hw,
-			    DLB2_SYS_LDB_QID2VQID(queue->id.phys_id),
-			    r2.val);
-	}
-
-	r13.field.qid_v = 1;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_V(queue->id.phys_id), r13.val);
-}
-
-static int
-dlb2_ldb_queue_attach_to_sn_group(struct dlb2_hw *hw,
-				  struct dlb2_ldb_queue *queue,
-				  struct dlb2_create_ldb_queue_args *args)
-{
-	int slot = -1;
-	int i;
-
-	queue->sn_cfg_valid = false;
-
-	if (args->num_sequence_numbers == 0)
-		return 0;
-
-	for (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {
-		struct dlb2_sn_group *group = &hw->rsrcs.sn_groups[i];
-
-		if (group->sequence_numbers_per_queue ==
-		    args->num_sequence_numbers &&
-		    !dlb2_sn_group_full(group)) {
-			slot = dlb2_sn_group_alloc_slot(group);
-			if (slot >= 0)
-				break;
-		}
-	}
-
-	if (slot == -1) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: no sequence number slots available\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	queue->sn_cfg_valid = true;
-	queue->sn_group = i;
-	queue->sn_slot = slot;
-	return 0;
-}
-
-static int
-dlb2_ldb_queue_attach_resources(struct dlb2_hw *hw,
-				struct dlb2_hw_domain *domain,
-				struct dlb2_ldb_queue *queue,
-				struct dlb2_create_ldb_queue_args *args)
-{
-	int ret;
-
-	ret = dlb2_ldb_queue_attach_to_sn_group(hw, queue, args);
-	if (ret)
-		return ret;
-
-	/* Attach QID inflights */
-	queue->num_qid_inflights = args->num_qid_inflights;
-
-	/* Attach atomic inflights */
-	queue->aqed_limit = args->num_atomic_inflights;
-
-	domain->num_avail_aqed_entries -= args->num_atomic_inflights;
-	domain->num_used_aqed_entries += args->num_atomic_inflights;
-
-	return 0;
-}
-
-static int
-dlb2_verify_create_ldb_queue_args(struct dlb2_hw *hw,
-				  u32 domain_id,
-				  struct dlb2_create_ldb_queue_args *args,
-				  struct dlb2_cmd_response *resp,
-				  bool vdev_req,
-				  unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	int i;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	if (domain->started) {
-		resp->status = DLB2_ST_DOMAIN_STARTED;
-		return -EINVAL;
-	}
-
-	if (dlb2_list_empty(&domain->avail_ldb_queues)) {
-		resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
-		return -EINVAL;
-	}
-
-	if (args->num_sequence_numbers) {
-		for (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {
-			struct dlb2_sn_group *group = &hw->rsrcs.sn_groups[i];
-
-			if (group->sequence_numbers_per_queue ==
-			    args->num_sequence_numbers &&
-			    !dlb2_sn_group_full(group))
-				break;
-		}
-
-		if (i == DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS) {
-			resp->status = DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE;
-			return -EINVAL;
-		}
-	}
-
-	if (args->num_qid_inflights > 4096) {
-		resp->status = DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION;
-		return -EINVAL;
-	}
-
-	/* Inflights must be <= number of sequence numbers if ordered */
-	if (args->num_sequence_numbers != 0 &&
-	    args->num_qid_inflights > args->num_sequence_numbers) {
-		resp->status = DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION;
-		return -EINVAL;
-	}
-
-	if (domain->num_avail_aqed_entries < args->num_atomic_inflights) {
-		resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
-		return -EINVAL;
-	}
-
-	if (args->num_atomic_inflights &&
-	    args->lock_id_comp_level != 0 &&
-	    args->lock_id_comp_level != 64 &&
-	    args->lock_id_comp_level != 128 &&
-	    args->lock_id_comp_level != 256 &&
-	    args->lock_id_comp_level != 512 &&
-	    args->lock_id_comp_level != 1024 &&
-	    args->lock_id_comp_level != 2048 &&
-	    args->lock_id_comp_level != 4096 &&
-	    args->lock_id_comp_level != 65536) {
-		resp->status = DLB2_ST_INVALID_LOCK_ID_COMP_LEVEL;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static void
-dlb2_log_create_ldb_queue_args(struct dlb2_hw *hw,
-			       u32 domain_id,
-			       struct dlb2_create_ldb_queue_args *args,
-			       bool vdev_req,
-			       unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 create load-balanced queue arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID:                  %d\n",
-		    domain_id);
-	DLB2_HW_DBG(hw, "\tNumber of sequence numbers: %d\n",
-		    args->num_sequence_numbers);
-	DLB2_HW_DBG(hw, "\tNumber of QID inflights:    %d\n",
-		    args->num_qid_inflights);
-	DLB2_HW_DBG(hw, "\tNumber of ATM inflights:    %d\n",
-		    args->num_atomic_inflights);
-}
-
-/**
- * dlb2_hw_create_ldb_queue() - Allocate and initialize a DLB LDB queue.
- * @hw:	Contains the current state of the DLB2 hardware.
- * @domain_id: Domain ID
- * @args: User-provided arguments.
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int dlb2_hw_create_ldb_queue(struct dlb2_hw *hw,
-			     u32 domain_id,
-			     struct dlb2_create_ldb_queue_args *args,
-			     struct dlb2_cmd_response *resp,
-			     bool vdev_req,
-			     unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_queue *queue;
-	int ret;
-
-	dlb2_log_create_ldb_queue_args(hw, domain_id, args, vdev_req, vdev_id);
-
-	/*
-	 * Verify that hardware resources are available before attempting to
-	 * satisfy the request. This simplifies the error unwinding code.
-	 */
-	ret = dlb2_verify_create_ldb_queue_args(hw,
-						domain_id,
-						args,
-						resp,
-						vdev_req,
-						vdev_id);
-	if (ret)
-		return ret;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: domain not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	queue = DLB2_DOM_LIST_HEAD(domain->avail_ldb_queues, typeof(*queue));
-	if (queue == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: no available ldb queues\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	ret = dlb2_ldb_queue_attach_resources(hw, domain, queue, args);
-	if (ret < 0) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: failed to attach the ldb queue resources\n",
-			    __func__, __LINE__);
-		return ret;
-	}
-
-	dlb2_configure_ldb_queue(hw, domain, queue, args, vdev_req, vdev_id);
-
-	queue->num_mappings = 0;
-
-	queue->configured = true;
-
-	/*
-	 * Configuration succeeded, so move the resource from the 'avail' to
-	 * the 'used' list.
-	 */
-	dlb2_list_del(&domain->avail_ldb_queues, &queue->domain_list);
-
-	dlb2_list_add(&domain->used_ldb_queues, &queue->domain_list);
-
-	resp->status = 0;
-	resp->id = (vdev_req) ? queue->id.virt_id : queue->id.phys_id;
-
-	return 0;
-}
-
 int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)
 {
 	if (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)
drivers/event/dlb2/pf/base/dlb2_resource_new.c +391 -0

394 lines not on this page · raw message

Signature · 1 line
2.23.0
#154 lore raw

PATCH 7/25 event/dlb2: add DLB v2.5 support to create ldb port

In reply to Timothy McDaniel

Update create ldb port low level code to account for new register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 490 ------------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 471 +++++++++++++++++
 2 files changed, 471 insertions(+), 490 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -490
index 5a8251ee0..d6ff7f6d9 100644
@@ -1217,496 +1217,6 @@ int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,
 	return 0;
 }
 
-static void dlb2_ldb_port_configure_pp(struct dlb2_hw *hw,
-				       struct dlb2_hw_domain *domain,
-				       struct dlb2_ldb_port *port,
-				       bool vdev_req,
-				       unsigned int vdev_id)
-{
-	union dlb2_sys_ldb_pp2vas r0 = { {0} };
-	union dlb2_sys_ldb_pp_v r4 = { {0} };
-
-	r0.field.vas = domain->id.phys_id;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_PP2VAS(port->id.phys_id), r0.val);
-
-	if (vdev_req) {
-		union dlb2_sys_vf_ldb_vpp2pp r1 = { {0} };
-		union dlb2_sys_ldb_pp2vdev r2 = { {0} };
-		union dlb2_sys_vf_ldb_vpp_v r3 = { {0} };
-		unsigned int offs;
-		u32 virt_id;
-
-		/*
-		 * DLB uses producer port address bits 17:12 to determine the
-		 * producer port ID. In Scalable IOV mode, PP accesses come
-		 * through the PF MMIO window for the physical producer port,
-		 * so for translation purposes the virtual and physical port
-		 * IDs are equal.
-		 */
-		if (hw->virt_mode == DLB2_VIRT_SRIOV)
-			virt_id = port->id.virt_id;
-		else
-			virt_id = port->id.phys_id;
-
-		r1.field.pp = port->id.phys_id;
-
-		offs = vdev_id * DLB2_MAX_NUM_LDB_PORTS + virt_id;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP2PP(offs), r1.val);
-
-		r2.field.vdev = vdev_id;
-
-		DLB2_CSR_WR(hw,
-			    DLB2_SYS_LDB_PP2VDEV(port->id.phys_id),
-			    r2.val);
-
-		r3.field.vpp_v = 1;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP_V(offs), r3.val);
-	}
-
-	r4.field.pp_v = 1;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_SYS_LDB_PP_V(port->id.phys_id),
-		    r4.val);
-}
-
-static int dlb2_ldb_port_configure_cq(struct dlb2_hw *hw,
-				      struct dlb2_hw_domain *domain,
-				      struct dlb2_ldb_port *port,
-				      uintptr_t cq_dma_base,
-				      struct dlb2_create_ldb_port_args *args,
-				      bool vdev_req,
-				      unsigned int vdev_id)
-{
-	union dlb2_sys_ldb_cq_addr_l r0 = { {0} };
-	union dlb2_sys_ldb_cq_addr_u r1 = { {0} };
-	union dlb2_sys_ldb_cq2vf_pf_ro r2 = { {0} };
-	union dlb2_chp_ldb_cq_tkn_depth_sel r3 = { {0} };
-	union dlb2_lsp_cq_ldb_tkn_depth_sel r4 = { {0} };
-	union dlb2_chp_hist_list_lim r5 = { {0} };
-	union dlb2_chp_hist_list_base r6 = { {0} };
-	union dlb2_lsp_cq_ldb_infl_lim r7 = { {0} };
-	union dlb2_chp_hist_list_push_ptr r8 = { {0} };
-	union dlb2_chp_hist_list_pop_ptr r9 = { {0} };
-	union dlb2_sys_ldb_cq_at r10 = { {0} };
-	union dlb2_sys_ldb_cq_pasid r11 = { {0} };
-	union dlb2_chp_ldb_cq2vas r12 = { {0} };
-	union dlb2_lsp_cq2priov r13 = { {0} };
-
-	/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */
-	r0.field.addr_l = cq_dma_base >> 6;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_L(port->id.phys_id), r0.val);
-
-	r1.field.addr_u = cq_dma_base >> 32;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_U(port->id.phys_id), r1.val);
-
-	/*
-	 * 'ro' == relaxed ordering. This setting allows DLB2 to write
-	 * cache lines out-of-order (but QEs within a cache line are always
-	 * updated in-order).
-	 */
-	r2.field.vf = vdev_id;
-	r2.field.is_pf = !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV);
-	r2.field.ro = 1;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ2VF_PF_RO(port->id.phys_id), r2.val);
-
-	if (args->cq_depth <= 8) {
-		r3.field.token_depth_select = 1;
-	} else if (args->cq_depth == 16) {
-		r3.field.token_depth_select = 2;
-	} else if (args->cq_depth == 32) {
-		r3.field.token_depth_select = 3;
-	} else if (args->cq_depth == 64) {
-		r3.field.token_depth_select = 4;
-	} else if (args->cq_depth == 128) {
-		r3.field.token_depth_select = 5;
-	} else if (args->cq_depth == 256) {
-		r3.field.token_depth_select = 6;
-	} else if (args->cq_depth == 512) {
-		r3.field.token_depth_select = 7;
-	} else if (args->cq_depth == 1024) {
-		r3.field.token_depth_select = 8;
-	} else {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: invalid CQ depth\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(port->id.phys_id),
-		    r3.val);
-
-	/*
-	 * To support CQs with depth less than 8, program the token count
-	 * register with a non-zero initial value. Operations such as domain
-	 * reset must take this initial value into account when quiescing the
-	 * CQ.
-	 */
-	port->init_tkn_cnt = 0;
-
-	if (args->cq_depth < 8) {
-		union dlb2_lsp_cq_ldb_tkn_cnt r14 = { {0} };
-
-		port->init_tkn_cnt = 8 - args->cq_depth;
-
-		r14.field.token_count = port->init_tkn_cnt;
-
-		DLB2_CSR_WR(hw,
-			    DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),
-			    r14.val);
-	} else {
-		DLB2_CSR_WR(hw,
-			    DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),
-			    DLB2_LSP_CQ_LDB_TKN_CNT_RST);
-	}
-
-	r4.field.token_depth_select = r3.field.token_depth_select;
-	r4.field.ignore_depth = 0;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(port->id.phys_id),
-		    r4.val);
-
-	/* Reset the CQ write pointer */
-	DLB2_CSR_WR(hw,
-		    DLB2_CHP_LDB_CQ_WPTR(port->id.phys_id),
-		    DLB2_CHP_LDB_CQ_WPTR_RST);
-
-	r5.field.limit = port->hist_list_entry_limit - 1;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_LIM(port->id.phys_id), r5.val);
-
-	r6.field.base = port->hist_list_entry_base;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_BASE(port->id.phys_id), r6.val);
-
-	/*
-	 * The inflight limit sets a cap on the number of QEs for which this CQ
-	 * can owe completions at one time.
-	 */
-	r7.field.limit = args->cq_history_list_size;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_INFL_LIM(port->id.phys_id), r7.val);
-
-	r8.field.push_ptr = r6.field.base;
-	r8.field.generation = 0;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_CHP_HIST_LIST_PUSH_PTR(port->id.phys_id),
-		    r8.val);
-
-	r9.field.pop_ptr = r6.field.base;
-	r9.field.generation = 0;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_POP_PTR(port->id.phys_id), r9.val);
-
-	/*
-	 * Address translation (AT) settings: 0: untranslated, 2: translated
-	 * (see ATS spec regarding Address Type field for more details)
-	 */
-	r10.field.cq_at = 0;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_AT(port->id.phys_id), r10.val);
-
-	if (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {
-		r11.field.pasid = hw->pasid[vdev_id];
-		r11.field.fmt2 = 1;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_SYS_LDB_CQ_PASID(port->id.phys_id),
-		    r11.val);
-
-	r12.field.cq2vas = domain->id.phys_id;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_LDB_CQ2VAS(port->id.phys_id), r12.val);
-
-	/* Disable the port's QID mappings */
-	r13.field.v = 0;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port->id.phys_id), r13.val);
-
-	return 0;
-}
-
-static int dlb2_configure_ldb_port(struct dlb2_hw *hw,
-				   struct dlb2_hw_domain *domain,
-				   struct dlb2_ldb_port *port,
-				   uintptr_t cq_dma_base,
-				   struct dlb2_create_ldb_port_args *args,
-				   bool vdev_req,
-				   unsigned int vdev_id)
-{
-	int ret, i;
-
-	port->hist_list_entry_base = domain->hist_list_entry_base +
-				     domain->hist_list_entry_offset;
-	port->hist_list_entry_limit = port->hist_list_entry_base +
-				      args->cq_history_list_size;
-
-	domain->hist_list_entry_offset += args->cq_history_list_size;
-	domain->avail_hist_list_entries -= args->cq_history_list_size;
-
-	ret = dlb2_ldb_port_configure_cq(hw,
-					 domain,
-					 port,
-					 cq_dma_base,
-					 args,
-					 vdev_req,
-					 vdev_id);
-	if (ret < 0)
-		return ret;
-
-	dlb2_ldb_port_configure_pp(hw,
-				   domain,
-				   port,
-				   vdev_req,
-				   vdev_id);
-
-	dlb2_ldb_port_cq_enable(hw, port);
-
-	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++)
-		port->qid_map[i].state = DLB2_QUEUE_UNMAPPED;
-	port->num_mappings = 0;
-
-	port->enabled = true;
-
-	port->configured = true;
-
-	return 0;
-}
-
-static void
-dlb2_log_create_ldb_port_args(struct dlb2_hw *hw,
-			      u32 domain_id,
-			      uintptr_t cq_dma_base,
-			      struct dlb2_create_ldb_port_args *args,
-			      bool vdev_req,
-			      unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 create load-balanced port arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID:                 %d\n",
-		    domain_id);
-	DLB2_HW_DBG(hw, "\tCQ depth:                  %d\n",
-		    args->cq_depth);
-	DLB2_HW_DBG(hw, "\tCQ hist list size:         %d\n",
-		    args->cq_history_list_size);
-	DLB2_HW_DBG(hw, "\tCQ base address:           0x%lx\n",
-		    cq_dma_base);
-	DLB2_HW_DBG(hw, "\tCoS ID:                    %u\n", args->cos_id);
-	DLB2_HW_DBG(hw, "\tStrict CoS allocation:     %u\n",
-		    args->cos_strict);
-}
-
-static int
-dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,
-				 u32 domain_id,
-				 uintptr_t cq_dma_base,
-				 struct dlb2_create_ldb_port_args *args,
-				 struct dlb2_cmd_response *resp,
-				 bool vdev_req,
-				 unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	int i;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	if (domain->started) {
-		resp->status = DLB2_ST_DOMAIN_STARTED;
-		return -EINVAL;
-	}
-
-	if (args->cos_id >= DLB2_NUM_COS_DOMAINS) {
-		resp->status = DLB2_ST_INVALID_COS_ID;
-		return -EINVAL;
-	}
-
-	if (args->cos_strict) {
-		if (dlb2_list_empty(&domain->avail_ldb_ports[args->cos_id])) {
-			resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
-			return -EINVAL;
-		}
-	} else {
-		for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-			if (!dlb2_list_empty(&domain->avail_ldb_ports[i]))
-				break;
-		}
-
-		if (i == DLB2_NUM_COS_DOMAINS) {
-			resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
-			return -EINVAL;
-		}
-	}
-
-	/* Check cache-line alignment */
-	if ((cq_dma_base & 0x3F) != 0) {
-		resp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;
-		return -EINVAL;
-	}
-
-	if (args->cq_depth != 1 &&
-	    args->cq_depth != 2 &&
-	    args->cq_depth != 4 &&
-	    args->cq_depth != 8 &&
-	    args->cq_depth != 16 &&
-	    args->cq_depth != 32 &&
-	    args->cq_depth != 64 &&
-	    args->cq_depth != 128 &&
-	    args->cq_depth != 256 &&
-	    args->cq_depth != 512 &&
-	    args->cq_depth != 1024) {
-		resp->status = DLB2_ST_INVALID_CQ_DEPTH;
-		return -EINVAL;
-	}
-
-	/* The history list size must be >= 1 */
-	if (!args->cq_history_list_size) {
-		resp->status = DLB2_ST_INVALID_HIST_LIST_DEPTH;
-		return -EINVAL;
-	}
-
-	if (args->cq_history_list_size > domain->avail_hist_list_entries) {
-		resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-
-/**
- * dlb2_hw_create_ldb_port() - Allocate and initialize a load-balanced port and
- *	its resources.
- * @hw:	Contains the current state of the DLB2 hardware.
- * @domain_id: Domain ID
- * @args: User-provided arguments.
- * @cq_dma_base: Base DMA address for consumer queue memory
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int dlb2_hw_create_ldb_port(struct dlb2_hw *hw,
-			    u32 domain_id,
-			    struct dlb2_create_ldb_port_args *args,
-			    uintptr_t cq_dma_base,
-			    struct dlb2_cmd_response *resp,
-			    bool vdev_req,
-			    unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_port *port;
-	int ret, cos_id, i;
-
-	dlb2_log_create_ldb_port_args(hw,
-				      domain_id,
-				      cq_dma_base,
-				      args,
-				      vdev_req,
-				      vdev_id);
-
-	/*
-	 * Verify that hardware resources are available before attempting to
-	 * satisfy the request. This simplifies the error unwinding code.
-	 */
-	ret = dlb2_verify_create_ldb_port_args(hw,
-					       domain_id,
-					       cq_dma_base,
-					       args,
-					       resp,
-					       vdev_req,
-					       vdev_id);
-	if (ret)
-		return ret;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: domain not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	if (args->cos_strict) {
-		cos_id = args->cos_id;
-
-		port = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[cos_id],
-					  typeof(*port));
-	} else {
-		int idx;
-
-		for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-			idx = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS;
-
-			port = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[idx],
-						  typeof(*port));
-			if (port)
-				break;
-		}
-
-		cos_id = idx;
-	}
-
-	if (port == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: no available ldb ports\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	if (port->configured) {
-		DLB2_HW_ERR(hw,
-			    "[%s()] Internal error: avail_ldb_ports contains configured ports.\n",
-			    __func__);
-		return -EFAULT;
-	}
-
-	ret = dlb2_configure_ldb_port(hw,
-				      domain,
-				      port,
-				      cq_dma_base,
-				      args,
-				      vdev_req,
-				      vdev_id);
-	if (ret < 0)
-		return ret;
-
-	/*
-	 * Configuration succeeded, so move the resource from the 'avail' to
-	 * the 'used' list.
-	 */
-	dlb2_list_del(&domain->avail_ldb_ports[cos_id], &port->domain_list);
-
-	dlb2_list_add(&domain->used_ldb_ports[cos_id], &port->domain_list);
-
-	resp->status = 0;
-	resp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;
-
-	return 0;
-}
-
 static void
 dlb2_log_create_dir_port_args(struct dlb2_hw *hw,
 			      u32 domain_id,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +471 -0

474 lines not on this page · raw message

Signature · 1 line
2.23.0
#155 lore raw

PATCH 8/25 event/dlb2: add DLB v2.5 support to create dir port

In reply to Timothy McDaniel

Updated low level hardware functions to account for new register map and access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 426 ------------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 414 +++++++++++++++++
 2 files changed, 414 insertions(+), 426 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -426
index d6ff7f6d9..2442327d3 100644
@@ -66,18 +66,6 @@ static inline void dlb2_flush_csr(struct dlb2_hw *hw)
 	DLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);
 }
 
-static void dlb2_dir_port_cq_enable(struct dlb2_hw *hw,
-				    struct dlb2_dir_pq_pair *port)
-{
-	union dlb2_lsp_cq_dir_dsbl reg;
-
-	reg.field.disabled = 0;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ_DIR_DSBL(port->id.phys_id), reg.val);
-
-	dlb2_flush_csr(hw);
-}
-
 static u32 dlb2_dir_queue_depth(struct dlb2_hw *hw,
 				struct dlb2_dir_pq_pair *queue)
 {
@@ -1217,25 +1205,6 @@ int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,
 	return 0;
 }
 
-static void
-dlb2_log_create_dir_port_args(struct dlb2_hw *hw,
-			      u32 domain_id,
-			      uintptr_t cq_dma_base,
-			      struct dlb2_create_dir_port_args *args,
-			      bool vdev_req,
-			      unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 create directed port arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID:                 %d\n",
-		    domain_id);
-	DLB2_HW_DBG(hw, "\tCQ depth:                  %d\n",
-		    args->cq_depth);
-	DLB2_HW_DBG(hw, "\tCQ base address:           0x%lx\n",
-		    cq_dma_base);
-}
-
 static struct dlb2_dir_pq_pair *
 dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,
 			    u32 id,
@@ -1257,401 +1226,6 @@ dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,
 	return NULL;
 }
 
-static int
-dlb2_verify_create_dir_port_args(struct dlb2_hw *hw,
-				 u32 domain_id,
-				 uintptr_t cq_dma_base,
-				 struct dlb2_create_dir_port_args *args,
-				 struct dlb2_cmd_response *resp,
-				 bool vdev_req,
-				 unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	if (domain->started) {
-		resp->status = DLB2_ST_DOMAIN_STARTED;
-		return -EINVAL;
-	}
-
-	/*
-	 * If the user claims the queue is already configured, validate
-	 * the queue ID, its domain, and whether the queue is configured.
-	 */
-	if (args->queue_id != -1) {
-		struct dlb2_dir_pq_pair *queue;
-
-		queue = dlb2_get_domain_used_dir_pq(hw,
-						    args->queue_id,
-						    vdev_req,
-						    domain);
-
-		if (queue == NULL || queue->domain_id.phys_id !=
-				domain->id.phys_id ||
-				!queue->queue_configured) {
-			resp->status = DLB2_ST_INVALID_DIR_QUEUE_ID;
-			return -EINVAL;
-		}
-	}
-
-	/*
-	 * If the port's queue is not configured, validate that a free
-	 * port-queue pair is available.
-	 */
-	if (args->queue_id == -1 &&
-	    dlb2_list_empty(&domain->avail_dir_pq_pairs)) {
-		resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
-		return -EINVAL;
-	}
-
-	/* Check cache-line alignment */
-	if ((cq_dma_base & 0x3F) != 0) {
-		resp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;
-		return -EINVAL;
-	}
-
-	if (args->cq_depth != 1 &&
-	    args->cq_depth != 2 &&
-	    args->cq_depth != 4 &&
-	    args->cq_depth != 8 &&
-	    args->cq_depth != 16 &&
-	    args->cq_depth != 32 &&
-	    args->cq_depth != 64 &&
-	    args->cq_depth != 128 &&
-	    args->cq_depth != 256 &&
-	    args->cq_depth != 512 &&
-	    args->cq_depth != 1024) {
-		resp->status = DLB2_ST_INVALID_CQ_DEPTH;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static void dlb2_dir_port_configure_pp(struct dlb2_hw *hw,
-				       struct dlb2_hw_domain *domain,
-				       struct dlb2_dir_pq_pair *port,
-				       bool vdev_req,
-				       unsigned int vdev_id)
-{
-	union dlb2_sys_dir_pp2vas r0 = { {0} };
-	union dlb2_sys_dir_pp_v r4 = { {0} };
-
-	r0.field.vas = domain->id.phys_id;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_PP2VAS(port->id.phys_id), r0.val);
-
-	if (vdev_req) {
-		union dlb2_sys_vf_dir_vpp2pp r1 = { {0} };
-		union dlb2_sys_dir_pp2vdev r2 = { {0} };
-		union dlb2_sys_vf_dir_vpp_v r3 = { {0} };
-		unsigned int offs;
-		u32 virt_id;
-
-		/*
-		 * DLB uses producer port address bits 17:12 to determine the
-		 * producer port ID. In Scalable IOV mode, PP accesses come
-		 * through the PF MMIO window for the physical producer port,
-		 * so for translation purposes the virtual and physical port
-		 * IDs are equal.
-		 */
-		if (hw->virt_mode == DLB2_VIRT_SRIOV)
-			virt_id = port->id.virt_id;
-		else
-			virt_id = port->id.phys_id;
-
-		r1.field.pp = port->id.phys_id;
-
-		offs = vdev_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) + virt_id;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP2PP(offs), r1.val);
-
-		r2.field.vdev = vdev_id;
-
-		DLB2_CSR_WR(hw,
-			    DLB2_SYS_DIR_PP2VDEV(port->id.phys_id),
-			    r2.val);
-
-		r3.field.vpp_v = 1;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP_V(offs), r3.val);
-	}
-
-	r4.field.pp_v = 1;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_SYS_DIR_PP_V(port->id.phys_id),
-		    r4.val);
-}
-
-static int dlb2_dir_port_configure_cq(struct dlb2_hw *hw,
-				      struct dlb2_hw_domain *domain,
-				      struct dlb2_dir_pq_pair *port,
-				      uintptr_t cq_dma_base,
-				      struct dlb2_create_dir_port_args *args,
-				      bool vdev_req,
-				      unsigned int vdev_id)
-{
-	union dlb2_sys_dir_cq_addr_l r0 = { {0} };
-	union dlb2_sys_dir_cq_addr_u r1 = { {0} };
-	union dlb2_sys_dir_cq2vf_pf_ro r2 = { {0} };
-	union dlb2_chp_dir_cq_tkn_depth_sel r3 = { {0} };
-	union dlb2_lsp_cq_dir_tkn_depth_sel_dsi r4 = { {0} };
-	union dlb2_sys_dir_cq_fmt r9 = { {0} };
-	union dlb2_sys_dir_cq_at r10 = { {0} };
-	union dlb2_sys_dir_cq_pasid r11 = { {0} };
-	union dlb2_chp_dir_cq2vas r12 = { {0} };
-
-	/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */
-	r0.field.addr_l = cq_dma_base >> 6;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_L(port->id.phys_id), r0.val);
-
-	r1.field.addr_u = cq_dma_base >> 32;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_U(port->id.phys_id), r1.val);
-
-	/*
-	 * 'ro' == relaxed ordering. This setting allows DLB2 to write
-	 * cache lines out-of-order (but QEs within a cache line are always
-	 * updated in-order).
-	 */
-	r2.field.vf = vdev_id;
-	r2.field.is_pf = !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV);
-	r2.field.ro = 1;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ2VF_PF_RO(port->id.phys_id), r2.val);
-
-	if (args->cq_depth <= 8) {
-		r3.field.token_depth_select = 1;
-	} else if (args->cq_depth == 16) {
-		r3.field.token_depth_select = 2;
-	} else if (args->cq_depth == 32) {
-		r3.field.token_depth_select = 3;
-	} else if (args->cq_depth == 64) {
-		r3.field.token_depth_select = 4;
-	} else if (args->cq_depth == 128) {
-		r3.field.token_depth_select = 5;
-	} else if (args->cq_depth == 256) {
-		r3.field.token_depth_select = 6;
-	} else if (args->cq_depth == 512) {
-		r3.field.token_depth_select = 7;
-	} else if (args->cq_depth == 1024) {
-		r3.field.token_depth_select = 8;
-	} else {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: invalid CQ depth\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(port->id.phys_id),
-		    r3.val);
-
-	/*
-	 * To support CQs with depth less than 8, program the token count
-	 * register with a non-zero initial value. Operations such as domain
-	 * reset must take this initial value into account when quiescing the
-	 * CQ.
-	 */
-	port->init_tkn_cnt = 0;
-
-	if (args->cq_depth < 8) {
-		union dlb2_lsp_cq_dir_tkn_cnt r13 = { {0} };
-
-		port->init_tkn_cnt = 8 - args->cq_depth;
-
-		r13.field.count = port->init_tkn_cnt;
-
-		DLB2_CSR_WR(hw,
-			    DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),
-			    r13.val);
-	} else {
-		DLB2_CSR_WR(hw,
-			    DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),
-			    DLB2_LSP_CQ_DIR_TKN_CNT_RST);
-	}
-
-	r4.field.token_depth_select = r3.field.token_depth_select;
-	r4.field.disable_wb_opt = 0;
-	r4.field.ignore_depth = 0;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(port->id.phys_id),
-		    r4.val);
-
-	/* Reset the CQ write pointer */
-	DLB2_CSR_WR(hw,
-		    DLB2_CHP_DIR_CQ_WPTR(port->id.phys_id),
-		    DLB2_CHP_DIR_CQ_WPTR_RST);
-
-	/* Virtualize the PPID */
-	r9.field.keep_pf_ppid = 0;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_FMT(port->id.phys_id), r9.val);
-
-	/*
-	 * Address translation (AT) settings: 0: untranslated, 2: translated
-	 * (see ATS spec regarding Address Type field for more details)
-	 */
-	r10.field.cq_at = 0;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_AT(port->id.phys_id), r10.val);
-
-	if (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {
-		r11.field.pasid = hw->pasid[vdev_id];
-		r11.field.fmt2 = 1;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_SYS_DIR_CQ_PASID(port->id.phys_id),
-		    r11.val);
-
-	r12.field.cq2vas = domain->id.phys_id;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_DIR_CQ2VAS(port->id.phys_id), r12.val);
-
-	return 0;
-}
-
-static int dlb2_configure_dir_port(struct dlb2_hw *hw,
-				   struct dlb2_hw_domain *domain,
-				   struct dlb2_dir_pq_pair *port,
-				   uintptr_t cq_dma_base,
-				   struct dlb2_create_dir_port_args *args,
-				   bool vdev_req,
-				   unsigned int vdev_id)
-{
-	int ret;
-
-	ret = dlb2_dir_port_configure_cq(hw,
-					 domain,
-					 port,
-					 cq_dma_base,
-					 args,
-					 vdev_req,
-					 vdev_id);
-
-	if (ret < 0)
-		return ret;
-
-	dlb2_dir_port_configure_pp(hw,
-				   domain,
-				   port,
-				   vdev_req,
-				   vdev_id);
-
-	dlb2_dir_port_cq_enable(hw, port);
-
-	port->enabled = true;
-
-	port->port_configured = true;
-
-	return 0;
-}
-
-/**
- * dlb2_hw_create_dir_port() - Allocate and initialize a DLB directed port
- *	and queue. The port/queue pair have the same ID and name.
- * @hw:	Contains the current state of the DLB2 hardware.
- * @domain_id: Domain ID
- * @args: User-provided arguments.
- * @cq_dma_base: Base DMA address for consumer queue memory
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int dlb2_hw_create_dir_port(struct dlb2_hw *hw,
-			    u32 domain_id,
-			    struct dlb2_create_dir_port_args *args,
-			    uintptr_t cq_dma_base,
-			    struct dlb2_cmd_response *resp,
-			    bool vdev_req,
-			    unsigned int vdev_id)
-{
-	struct dlb2_dir_pq_pair *port;
-	struct dlb2_hw_domain *domain;
-	int ret;
-
-	dlb2_log_create_dir_port_args(hw,
-				      domain_id,
-				      cq_dma_base,
-				      args,
-				      vdev_req,
-				      vdev_id);
-
-	/*
-	 * Verify that hardware resources are available before attempting to
-	 * satisfy the request. This simplifies the error unwinding code.
-	 */
-	ret = dlb2_verify_create_dir_port_args(hw,
-					       domain_id,
-					       cq_dma_base,
-					       args,
-					       resp,
-					       vdev_req,
-					       vdev_id);
-	if (ret)
-		return ret;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (args->queue_id != -1)
-		port = dlb2_get_domain_used_dir_pq(hw,
-						   args->queue_id,
-						   vdev_req,
-						   domain);
-	else
-		port = DLB2_DOM_LIST_HEAD(domain->avail_dir_pq_pairs,
-					  typeof(*port));
-	if (port == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: no available dir ports\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	ret = dlb2_configure_dir_port(hw,
-				      domain,
-				      port,
-				      cq_dma_base,
-				      args,
-				      vdev_req,
-				      vdev_id);
-	if (ret < 0)
-		return ret;
-
-	/*
-	 * Configuration succeeded, so move the resource from the 'avail' to
-	 * the 'used' list (if it's not already there).
-	 */
-	if (args->queue_id == -1) {
-		dlb2_list_del(&domain->avail_dir_pq_pairs, &port->domain_list);
-
-		dlb2_list_add(&domain->used_dir_pq_pairs, &port->domain_list);
-	}
-
-	resp->status = 0;
-	resp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;
-
-	return 0;
-}
-
 static void dlb2_configure_dir_queue(struct dlb2_hw *hw,
 				     struct dlb2_hw_domain *domain,
 				     struct dlb2_dir_pq_pair *queue,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +414 -0

417 lines not on this page · raw message

Signature · 1 line
2.23.0
#156 lore raw

PATCH 9/25 event/dlb2: add DLB v2.5 support to create dir queue

In reply to Timothy McDaniel

Updated low level hardware functions to account for new register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 213 ------------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 201 +++++++++++++++++
 2 files changed, 201 insertions(+), 213 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -213
index 2442327d3..d9284812a 100644
@@ -1226,219 +1226,6 @@ dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,
 	return NULL;
 }
 
-static void dlb2_configure_dir_queue(struct dlb2_hw *hw,
-				     struct dlb2_hw_domain *domain,
-				     struct dlb2_dir_pq_pair *queue,
-				     struct dlb2_create_dir_queue_args *args,
-				     bool vdev_req,
-				     unsigned int vdev_id)
-{
-	union dlb2_sys_dir_vasqid_v r0 = { {0} };
-	union dlb2_sys_dir_qid_its r1 = { {0} };
-	union dlb2_lsp_qid_dir_depth_thrsh r2 = { {0} };
-	union dlb2_sys_dir_qid_v r5 = { {0} };
-
-	unsigned int offs;
-
-	/* QID write permissions are turned on when the domain is started */
-	r0.field.vasqid_v = 0;
-
-	offs = domain->id.phys_id * DLB2_MAX_NUM_DIR_QUEUES(hw->ver) +
-		queue->id.phys_id;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_VASQID_V(offs), r0.val);
-
-	/* Don't timestamp QEs that pass through this queue */
-	r1.field.qid_its = 0;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_SYS_DIR_QID_ITS(queue->id.phys_id),
-		    r1.val);
-
-	r2.field.thresh = args->depth_threshold;
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID_DIR_DEPTH_THRSH(queue->id.phys_id),
-		    r2.val);
-
-	if (vdev_req) {
-		union dlb2_sys_vf_dir_vqid_v r3 = { {0} };
-		union dlb2_sys_vf_dir_vqid2qid r4 = { {0} };
-
-		offs = vdev_id * DLB2_MAX_NUM_DIR_QUEUES(hw->ver)
-			+ queue->id.virt_id;
-
-		r3.field.vqid_v = 1;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VQID_V(offs), r3.val);
-
-		r4.field.qid = queue->id.phys_id;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VQID2QID(offs), r4.val);
-	}
-
-	r5.field.qid_v = 1;
-
-	DLB2_CSR_WR(hw, DLB2_SYS_DIR_QID_V(queue->id.phys_id), r5.val);
-
-	queue->queue_configured = true;
-}
-
-static void
-dlb2_log_create_dir_queue_args(struct dlb2_hw *hw,
-			       u32 domain_id,
-			       struct dlb2_create_dir_queue_args *args,
-			       bool vdev_req,
-			       unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 create directed queue arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID: %d\n", domain_id);
-	DLB2_HW_DBG(hw, "\tPort ID:   %d\n", args->port_id);
-}
-
-static int
-dlb2_verify_create_dir_queue_args(struct dlb2_hw *hw,
-				  u32 domain_id,
-				  struct dlb2_create_dir_queue_args *args,
-				  struct dlb2_cmd_response *resp,
-				  bool vdev_req,
-				  unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	if (domain->started) {
-		resp->status = DLB2_ST_DOMAIN_STARTED;
-		return -EINVAL;
-	}
-
-	/*
-	 * If the user claims the port is already configured, validate the port
-	 * ID, its domain, and whether the port is configured.
-	 */
-	if (args->port_id != -1) {
-		struct dlb2_dir_pq_pair *port;
-
-		port = dlb2_get_domain_used_dir_pq(hw,
-						   args->port_id,
-						   vdev_req,
-						   domain);
-
-		if (port == NULL || port->domain_id.phys_id !=
-				domain->id.phys_id || !port->port_configured) {
-			resp->status = DLB2_ST_INVALID_PORT_ID;
-			return -EINVAL;
-		}
-	}
-
-	/*
-	 * If the queue's port is not configured, validate that a free
-	 * port-queue pair is available.
-	 */
-	if (args->port_id == -1 &&
-	    dlb2_list_empty(&domain->avail_dir_pq_pairs)) {
-		resp->status = DLB2_ST_DIR_QUEUES_UNAVAILABLE;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/**
- * dlb2_hw_create_dir_queue() - Allocate and initialize a DLB DIR queue.
- * @hw:	Contains the current state of the DLB2 hardware.
- * @domain_id: Domain ID
- * @args: User-provided arguments.
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int dlb2_hw_create_dir_queue(struct dlb2_hw *hw,
-			     u32 domain_id,
-			     struct dlb2_create_dir_queue_args *args,
-			     struct dlb2_cmd_response *resp,
-			     bool vdev_req,
-			     unsigned int vdev_id)
-{
-	struct dlb2_dir_pq_pair *queue;
-	struct dlb2_hw_domain *domain;
-	int ret;
-
-	dlb2_log_create_dir_queue_args(hw, domain_id, args, vdev_req, vdev_id);
-
-	/*
-	 * Verify that hardware resources are available before attempting to
-	 * satisfy the request. This simplifies the error unwinding code.
-	 */
-	ret = dlb2_verify_create_dir_queue_args(hw,
-						domain_id,
-						args,
-						resp,
-						vdev_req,
-						vdev_id);
-	if (ret)
-		return ret;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: domain not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	if (args->port_id != -1)
-		queue = dlb2_get_domain_used_dir_pq(hw,
-						    args->port_id,
-						    vdev_req,
-						    domain);
-	else
-		queue = DLB2_DOM_LIST_HEAD(domain->avail_dir_pq_pairs,
-					   typeof(*queue));
-	if (queue == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: no available dir queues\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	dlb2_configure_dir_queue(hw, domain, queue, args, vdev_req, vdev_id);
-
-	/*
-	 * Configuration succeeded, so move the resource from the 'avail' to
-	 * the 'used' list (if it's not already there).
-	 */
-	if (args->port_id == -1) {
-		dlb2_list_del(&domain->avail_dir_pq_pairs,
-			      &queue->domain_list);
-
-		dlb2_list_add(&domain->used_dir_pq_pairs,
-			      &queue->domain_list);
-	}
-
-	resp->status = 0;
-
-	resp->id = (vdev_req) ? queue->id.virt_id : queue->id.phys_id;
-
-	return 0;
-}
-
 static bool
 dlb2_port_find_slot_with_pending_map_queue(struct dlb2_ldb_port *port,
 					   struct dlb2_ldb_queue *queue,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +201 -0

204 lines not on this page · raw message

Signature · 1 line
2.23.0
#157 lore raw

PATCH 10/25 event/dlb2: add DLB v2.5 support to map qid

In reply to Timothy McDaniel

Update low level hardware functions to account for new register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 355 ---------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 418 ++++++++++++++++++
 2 files changed, 418 insertions(+), 355 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -355
index d9284812a..4fa867c3f 100644
@@ -1246,68 +1246,6 @@ dlb2_port_find_slot_with_pending_map_queue(struct dlb2_ldb_port *port,
 	return (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);
 }
 
-static void dlb2_ldb_port_change_qid_priority(struct dlb2_hw *hw,
-					      struct dlb2_ldb_port *port,
-					      int slot,
-					      struct dlb2_map_qid_args *args)
-{
-	union dlb2_lsp_cq2priov r0;
-
-	/* Read-modify-write the priority and valid bit register */
-	r0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(port->id.phys_id));
-
-	r0.field.v |= 1 << slot;
-	r0.field.prio |= (args->priority & 0x7) << slot * 3;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port->id.phys_id), r0.val);
-
-	dlb2_flush_csr(hw);
-
-	port->qid_map[slot].priority = args->priority;
-}
-
-static int dlb2_verify_map_qid_slot_available(struct dlb2_ldb_port *port,
-					      struct dlb2_ldb_queue *queue,
-					      struct dlb2_cmd_response *resp)
-{
-	enum dlb2_qid_map_state state;
-	int i;
-
-	/* Unused slot available? */
-	if (port->num_mappings < DLB2_MAX_NUM_QIDS_PER_LDB_CQ)
-		return 0;
-
-	/*
-	 * If the queue is already mapped (from the application's perspective),
-	 * this is simply a priority update.
-	 */
-	state = DLB2_QUEUE_MAPPED;
-	if (dlb2_port_find_slot_queue(port, state, queue, &i))
-		return 0;
-
-	state = DLB2_QUEUE_MAP_IN_PROG;
-	if (dlb2_port_find_slot_queue(port, state, queue, &i))
-		return 0;
-
-	if (dlb2_port_find_slot_with_pending_map_queue(port, queue, &i))
-		return 0;
-
-	/*
-	 * If the slot contains an unmap in progress, it's considered
-	 * available.
-	 */
-	state = DLB2_QUEUE_UNMAP_IN_PROG;
-	if (dlb2_port_find_slot(port, state, &i))
-		return 0;
-
-	state = DLB2_QUEUE_UNMAPPED;
-	if (dlb2_port_find_slot(port, state, &i))
-		return 0;
-
-	resp->status = DLB2_ST_NO_QID_SLOTS_AVAILABLE;
-	return -EINVAL;
-}
-
 static struct dlb2_ldb_queue *
 dlb2_get_domain_ldb_queue(u32 id,
 			  bool vdev_req,
@@ -1356,299 +1294,6 @@ dlb2_get_domain_used_ldb_port(u32 id,
 	return NULL;
 }
 
-static int dlb2_verify_map_qid_args(struct dlb2_hw *hw,
-				    u32 domain_id,
-				    struct dlb2_map_qid_args *args,
-				    struct dlb2_cmd_response *resp,
-				    bool vdev_req,
-				    unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_port *port;
-	struct dlb2_ldb_queue *queue;
-	int id;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	id = args->port_id;
-
-	port = dlb2_get_domain_used_ldb_port(id, vdev_req, domain);
-
-	if (port == NULL || !port->configured) {
-		resp->status = DLB2_ST_INVALID_PORT_ID;
-		return -EINVAL;
-	}
-
-	if (args->priority >= DLB2_QID_PRIORITIES) {
-		resp->status = DLB2_ST_INVALID_PRIORITY;
-		return -EINVAL;
-	}
-
-	queue = dlb2_get_domain_ldb_queue(args->qid, vdev_req, domain);
-
-	if (queue == NULL || !queue->configured) {
-		resp->status = DLB2_ST_INVALID_QID;
-		return -EINVAL;
-	}
-
-	if (queue->domain_id.phys_id != domain->id.phys_id) {
-		resp->status = DLB2_ST_INVALID_QID;
-		return -EINVAL;
-	}
-
-	if (port->domain_id.phys_id != domain->id.phys_id) {
-		resp->status = DLB2_ST_INVALID_PORT_ID;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static void dlb2_log_map_qid(struct dlb2_hw *hw,
-			     u32 domain_id,
-			     struct dlb2_map_qid_args *args,
-			     bool vdev_req,
-			     unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 map QID arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID: %d\n",
-		    domain_id);
-	DLB2_HW_DBG(hw, "\tPort ID:   %d\n",
-		    args->port_id);
-	DLB2_HW_DBG(hw, "\tQueue ID:  %d\n",
-		    args->qid);
-	DLB2_HW_DBG(hw, "\tPriority:  %d\n",
-		    args->priority);
-}
-
-int dlb2_hw_map_qid(struct dlb2_hw *hw,
-		    u32 domain_id,
-		    struct dlb2_map_qid_args *args,
-		    struct dlb2_cmd_response *resp,
-		    bool vdev_req,
-		    unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_queue *queue;
-	enum dlb2_qid_map_state st;
-	struct dlb2_ldb_port *port;
-	int ret, i, id;
-	u8 prio;
-
-	dlb2_log_map_qid(hw, domain_id, args, vdev_req, vdev_id);
-
-	/*
-	 * Verify that hardware resources are available before attempting to
-	 * satisfy the request. This simplifies the error unwinding code.
-	 */
-	ret = dlb2_verify_map_qid_args(hw,
-				       domain_id,
-				       args,
-				       resp,
-				       vdev_req,
-				       vdev_id);
-	if (ret)
-		return ret;
-
-	prio = args->priority;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: domain not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	id = args->port_id;
-
-	port = dlb2_get_domain_used_ldb_port(id, vdev_req, domain);
-	if (port == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	queue = dlb2_get_domain_ldb_queue(args->qid, vdev_req, domain);
-	if (queue == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: queue not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	/*
-	 * If there are any outstanding detach operations for this port,
-	 * attempt to complete them. This may be necessary to free up a QID
-	 * slot for this requested mapping.
-	 */
-	if (port->num_pending_removals)
-		dlb2_domain_finish_unmap_port(hw, domain, port);
-
-	ret = dlb2_verify_map_qid_slot_available(port, queue, resp);
-	if (ret)
-		return ret;
-
-	/* Hardware requires disabling the CQ before mapping QIDs. */
-	if (port->enabled)
-		dlb2_ldb_port_cq_disable(hw, port);
-
-	/*
-	 * If this is only a priority change, don't perform the full QID->CQ
-	 * mapping procedure
-	 */
-	st = DLB2_QUEUE_MAPPED;
-	if (dlb2_port_find_slot_queue(port, st, queue, &i)) {
-		if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-			DLB2_HW_ERR(hw,
-				    "[%s():%d] Internal error: port slot tracking failed\n",
-				    __func__, __LINE__);
-			return -EFAULT;
-		}
-
-		if (prio != port->qid_map[i].priority) {
-			dlb2_ldb_port_change_qid_priority(hw, port, i, args);
-			DLB2_HW_DBG(hw, "DLB2 map: priority change\n");
-		}
-
-		st = DLB2_QUEUE_MAPPED;
-		ret = dlb2_port_slot_state_transition(hw, port, queue, i, st);
-		if (ret)
-			return ret;
-
-		goto map_qid_done;
-	}
-
-	st = DLB2_QUEUE_UNMAP_IN_PROG;
-	if (dlb2_port_find_slot_queue(port, st, queue, &i)) {
-		if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-			DLB2_HW_ERR(hw,
-				    "[%s():%d] Internal error: port slot tracking failed\n",
-				    __func__, __LINE__);
-			return -EFAULT;
-		}
-
-		if (prio != port->qid_map[i].priority) {
-			dlb2_ldb_port_change_qid_priority(hw, port, i, args);
-			DLB2_HW_DBG(hw, "DLB2 map: priority change\n");
-		}
-
-		st = DLB2_QUEUE_MAPPED;
-		ret = dlb2_port_slot_state_transition(hw, port, queue, i, st);
-		if (ret)
-			return ret;
-
-		goto map_qid_done;
-	}
-
-	/*
-	 * If this is a priority change on an in-progress mapping, don't
-	 * perform the full QID->CQ mapping procedure.
-	 */
-	st = DLB2_QUEUE_MAP_IN_PROG;
-	if (dlb2_port_find_slot_queue(port, st, queue, &i)) {
-		if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-			DLB2_HW_ERR(hw,
-				    "[%s():%d] Internal error: port slot tracking failed\n",
-				    __func__, __LINE__);
-			return -EFAULT;
-		}
-
-		port->qid_map[i].priority = prio;
-
-		DLB2_HW_DBG(hw, "DLB2 map: priority change only\n");
-
-		goto map_qid_done;
-	}
-
-	/*
-	 * If this is a priority change on a pending mapping, update the
-	 * pending priority
-	 */
-	if (dlb2_port_find_slot_with_pending_map_queue(port, queue, &i)) {
-		if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-			DLB2_HW_ERR(hw,
-				    "[%s():%d] Internal error: port slot tracking failed\n",
-				    __func__, __LINE__);
-			return -EFAULT;
-		}
-
-		port->qid_map[i].pending_priority = prio;
-
-		DLB2_HW_DBG(hw, "DLB2 map: priority change only\n");
-
-		goto map_qid_done;
-	}
-
-	/*
-	 * If all the CQ's slots are in use, then there's an unmap in progress
-	 * (guaranteed by dlb2_verify_map_qid_slot_available()), so add this
-	 * mapping to pending_map and return. When the removal is completed for
-	 * the slot's current occupant, this mapping will be performed.
-	 */
-	if (!dlb2_port_find_slot(port, DLB2_QUEUE_UNMAPPED, &i)) {
-		if (dlb2_port_find_slot(port, DLB2_QUEUE_UNMAP_IN_PROG, &i)) {
-			enum dlb2_qid_map_state st;
-
-			if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-				DLB2_HW_ERR(hw,
-					    "[%s():%d] Internal error: port slot tracking failed\n",
-					    __func__, __LINE__);
-				return -EFAULT;
-			}
-
-			port->qid_map[i].pending_qid = queue->id.phys_id;
-			port->qid_map[i].pending_priority = prio;
-
-			st = DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP;
-
-			ret = dlb2_port_slot_state_transition(hw, port, queue,
-							      i, st);
-			if (ret)
-				return ret;
-
-			DLB2_HW_DBG(hw, "DLB2 map: map pending removal\n");
-
-			goto map_qid_done;
-		}
-	}
-
-	/*
-	 * If the domain has started, a special "dynamic" CQ->queue mapping
-	 * procedure is required in order to safely update the CQ<->QID tables.
-	 * The "static" procedure cannot be used when traffic is flowing,
-	 * because the CQ<->QID tables cannot be updated atomically and the
-	 * scheduler won't see the new mapping unless the queue's if_status
-	 * changes, which isn't guaranteed.
-	 */
-	ret = dlb2_ldb_port_map_qid(hw, domain, port, queue, prio);
-
-	/* If ret is less than zero, it's due to an internal error */
-	if (ret < 0)
-		return ret;
-
-map_qid_done:
-	if (port->enabled)
-		dlb2_ldb_port_cq_enable(hw, port);
-
-	resp->status = 0;
-
-	return 0;
-}
-
 static void dlb2_log_unmap_qid(struct dlb2_hw *hw,
 			       u32 domain_id,
 			       struct dlb2_unmap_qid_args *args,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +418 -0

421 lines not on this page · raw message

Signature · 1 line
2.23.0
#158 lore raw

PATCH 11/25 event/dlb2: add DLB v2.5 support to unmap queue

In reply to Timothy McDaniel

Update low level functions to account for new register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 331 ------------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 298 ++++++++++++++++
 2 files changed, 298 insertions(+), 331 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -331
index 4fa867c3f..02c2836ad 100644
@@ -1226,26 +1226,6 @@ dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,
 	return NULL;
 }
 
-static bool
-dlb2_port_find_slot_with_pending_map_queue(struct dlb2_ldb_port *port,
-					   struct dlb2_ldb_queue *queue,
-					   int *slot)
-{
-	int i;
-
-	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
-		struct dlb2_ldb_port_qid_map *map = &port->qid_map[i];
-
-		if (map->state == DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP &&
-		    map->pending_qid == queue->id.phys_id)
-			break;
-	}
-
-	*slot = i;
-
-	return (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);
-}
-
 static struct dlb2_ldb_queue *
 dlb2_get_domain_ldb_queue(u32 id,
 			  bool vdev_req,
@@ -1266,317 +1246,6 @@ dlb2_get_domain_ldb_queue(u32 id,
 	return NULL;
 }
 
-static struct dlb2_ldb_port *
-dlb2_get_domain_used_ldb_port(u32 id,
-			      bool vdev_req,
-			      struct dlb2_hw_domain *domain)
-{
-	struct dlb2_list_entry *iter;
-	struct dlb2_ldb_port *port;
-	int i;
-	RTE_SET_USED(iter);
-
-	if (id >= DLB2_MAX_NUM_LDB_PORTS)
-		return NULL;
-
-	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)
-			if ((!vdev_req && port->id.phys_id == id) ||
-			    (vdev_req && port->id.virt_id == id))
-				return port;
-
-		DLB2_DOM_LIST_FOR(domain->avail_ldb_ports[i], port, iter)
-			if ((!vdev_req && port->id.phys_id == id) ||
-			    (vdev_req && port->id.virt_id == id))
-				return port;
-	}
-
-	return NULL;
-}
-
-static void dlb2_log_unmap_qid(struct dlb2_hw *hw,
-			       u32 domain_id,
-			       struct dlb2_unmap_qid_args *args,
-			       bool vdev_req,
-			       unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 unmap QID arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID: %d\n",
-		    domain_id);
-	DLB2_HW_DBG(hw, "\tPort ID:   %d\n",
-		    args->port_id);
-	DLB2_HW_DBG(hw, "\tQueue ID:  %d\n",
-		    args->qid);
-	if (args->qid < DLB2_MAX_NUM_LDB_QUEUES)
-		DLB2_HW_DBG(hw, "\tQueue's num mappings:  %d\n",
-			    hw->rsrcs.ldb_queues[args->qid].num_mappings);
-}
-
-static int dlb2_verify_unmap_qid_args(struct dlb2_hw *hw,
-				      u32 domain_id,
-				      struct dlb2_unmap_qid_args *args,
-				      struct dlb2_cmd_response *resp,
-				      bool vdev_req,
-				      unsigned int vdev_id)
-{
-	enum dlb2_qid_map_state state;
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_queue *queue;
-	struct dlb2_ldb_port *port;
-	int slot;
-	int id;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	id = args->port_id;
-
-	port = dlb2_get_domain_used_ldb_port(id, vdev_req, domain);
-
-	if (port == NULL || !port->configured) {
-		resp->status = DLB2_ST_INVALID_PORT_ID;
-		return -EINVAL;
-	}
-
-	if (port->domain_id.phys_id != domain->id.phys_id) {
-		resp->status = DLB2_ST_INVALID_PORT_ID;
-		return -EINVAL;
-	}
-
-	queue = dlb2_get_domain_ldb_queue(args->qid, vdev_req, domain);
-
-	if (queue == NULL || !queue->configured) {
-		DLB2_HW_ERR(hw, "[%s()] Can't unmap unconfigured queue %d\n",
-			    __func__, args->qid);
-		resp->status = DLB2_ST_INVALID_QID;
-		return -EINVAL;
-	}
-
-	/*
-	 * Verify that the port has the queue mapped. From the application's
-	 * perspective a queue is mapped if it is actually mapped, the map is
-	 * in progress, or the map is blocked pending an unmap.
-	 */
-	state = DLB2_QUEUE_MAPPED;
-	if (dlb2_port_find_slot_queue(port, state, queue, &slot))
-		return 0;
-
-	state = DLB2_QUEUE_MAP_IN_PROG;
-	if (dlb2_port_find_slot_queue(port, state, queue, &slot))
-		return 0;
-
-	if (dlb2_port_find_slot_with_pending_map_queue(port, queue, &slot))
-		return 0;
-
-	resp->status = DLB2_ST_INVALID_QID;
-	return -EINVAL;
-}
-
-int dlb2_hw_unmap_qid(struct dlb2_hw *hw,
-		      u32 domain_id,
-		      struct dlb2_unmap_qid_args *args,
-		      struct dlb2_cmd_response *resp,
-		      bool vdev_req,
-		      unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_queue *queue;
-	enum dlb2_qid_map_state st;
-	struct dlb2_ldb_port *port;
-	bool unmap_complete;
-	int i, ret, id;
-
-	dlb2_log_unmap_qid(hw, domain_id, args, vdev_req, vdev_id);
-
-	/*
-	 * Verify that hardware resources are available before attempting to
-	 * satisfy the request. This simplifies the error unwinding code.
-	 */
-	ret = dlb2_verify_unmap_qid_args(hw,
-					 domain_id,
-					 args,
-					 resp,
-					 vdev_req,
-					 vdev_id);
-	if (ret)
-		return ret;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: domain not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	id = args->port_id;
-
-	port = dlb2_get_domain_used_ldb_port(id, vdev_req, domain);
-	if (port == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	queue = dlb2_get_domain_ldb_queue(args->qid, vdev_req, domain);
-	if (queue == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: queue not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	/*
-	 * If the queue hasn't been mapped yet, we need to update the slot's
-	 * state and re-enable the queue's inflights.
-	 */
-	st = DLB2_QUEUE_MAP_IN_PROG;
-	if (dlb2_port_find_slot_queue(port, st, queue, &i)) {
-		if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-			DLB2_HW_ERR(hw,
-				    "[%s():%d] Internal error: port slot tracking failed\n",
-				    __func__, __LINE__);
-			return -EFAULT;
-		}
-
-		/*
-		 * Since the in-progress map was aborted, re-enable the QID's
-		 * inflights.
-		 */
-		if (queue->num_pending_additions == 0)
-			dlb2_ldb_queue_set_inflight_limit(hw, queue);
-
-		st = DLB2_QUEUE_UNMAPPED;
-		ret = dlb2_port_slot_state_transition(hw, port, queue, i, st);
-		if (ret)
-			return ret;
-
-		goto unmap_qid_done;
-	}
-
-	/*
-	 * If the queue mapping is on hold pending an unmap, we simply need to
-	 * update the slot's state.
-	 */
-	if (dlb2_port_find_slot_with_pending_map_queue(port, queue, &i)) {
-		if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-			DLB2_HW_ERR(hw,
-				    "[%s():%d] Internal error: port slot tracking failed\n",
-				    __func__, __LINE__);
-			return -EFAULT;
-		}
-
-		st = DLB2_QUEUE_UNMAP_IN_PROG;
-		ret = dlb2_port_slot_state_transition(hw, port, queue, i, st);
-		if (ret)
-			return ret;
-
-		goto unmap_qid_done;
-	}
-
-	st = DLB2_QUEUE_MAPPED;
-	if (!dlb2_port_find_slot_queue(port, st, queue, &i)) {
-		DLB2_HW_ERR(hw,
-			    "[%s()] Internal error: no available CQ slots\n",
-			    __func__);
-		return -EFAULT;
-	}
-
-	if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port slot tracking failed\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	/*
-	 * QID->CQ mapping removal is an asynchronous procedure. It requires
-	 * stopping the DLB2 from scheduling this CQ, draining all inflights
-	 * from the CQ, then unmapping the queue from the CQ. This function
-	 * simply marks the port as needing the queue unmapped, and (if
-	 * necessary) starts the unmapping worker thread.
-	 */
-	dlb2_ldb_port_cq_disable(hw, port);
-
-	st = DLB2_QUEUE_UNMAP_IN_PROG;
-	ret = dlb2_port_slot_state_transition(hw, port, queue, i, st);
-	if (ret)
-		return ret;
-
-	/*
-	 * Attempt to finish the unmapping now, in case the port has no
-	 * outstanding inflights. If that's not the case, this will fail and
-	 * the unmapping will be completed at a later time.
-	 */
-	unmap_complete = dlb2_domain_finish_unmap_port(hw, domain, port);
-
-	/*
-	 * If the unmapping couldn't complete immediately, launch the worker
-	 * thread (if it isn't already launched) to finish it later.
-	 */
-	if (!unmap_complete && !os_worker_active(hw))
-		os_schedule_work(hw);
-
-unmap_qid_done:
-	resp->status = 0;
-
-	return 0;
-}
-
-static void
-dlb2_log_pending_port_unmaps_args(struct dlb2_hw *hw,
-				  struct dlb2_pending_port_unmaps_args *args,
-				  bool vdev_req,
-				  unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB unmaps in progress arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from VF %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tPort ID: %d\n", args->port_id);
-}
-
-int dlb2_hw_pending_port_unmaps(struct dlb2_hw *hw,
-				u32 domain_id,
-				struct dlb2_pending_port_unmaps_args *args,
-				struct dlb2_cmd_response *resp,
-				bool vdev_req,
-				unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_port *port;
-
-	dlb2_log_pending_port_unmaps_args(hw, args, vdev_req, vdev_id);
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	port = dlb2_get_domain_used_ldb_port(args->port_id, vdev_req, domain);
-	if (port == NULL || !port->configured) {
-		resp->status = DLB2_ST_INVALID_PORT_ID;
-		return -EINVAL;
-	}
-
-	resp->id = port->num_pending_removals;
-
-	return 0;
-}
-
 static int dlb2_verify_start_domain_args(struct dlb2_hw *hw,
 					 u32 domain_id,
 					 struct dlb2_cmd_response *resp,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +298 -0

301 lines not on this page · raw message

Signature · 1 line
2.23.0
#159 lore raw

PATCH 12/25 event/dlb2: add DLB v2.5 support to start domain

In reply to Timothy McDaniel

Update low level functions to account for new register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 123 -----------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 130 ++++++++++++++++++
 2 files changed, 130 insertions(+), 123 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -123
index 02c2836ad..6b5c8ba01 100644
@@ -1246,129 +1246,6 @@ dlb2_get_domain_ldb_queue(u32 id,
 	return NULL;
 }
 
-static int dlb2_verify_start_domain_args(struct dlb2_hw *hw,
-					 u32 domain_id,
-					 struct dlb2_cmd_response *resp,
-					 bool vdev_req,
-					 unsigned int vdev_id)
-{
-	struct dlb2_hw_domain *domain;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-
-	if (domain == NULL) {
-		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
-		return -EINVAL;
-	}
-
-	if (!domain->configured) {
-		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
-		return -EINVAL;
-	}
-
-	if (domain->started) {
-		resp->status = DLB2_ST_DOMAIN_STARTED;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static void dlb2_log_start_domain(struct dlb2_hw *hw,
-				  u32 domain_id,
-				  bool vdev_req,
-				  unsigned int vdev_id)
-{
-	DLB2_HW_DBG(hw, "DLB2 start domain arguments:\n");
-	if (vdev_req)
-		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
-	DLB2_HW_DBG(hw, "\tDomain ID: %d\n", domain_id);
-}
-
-/**
- * dlb2_hw_start_domain() - Lock the domain configuration
- * @hw:	Contains the current state of the DLB2 hardware.
- * @domain_id: Domain ID
- * @arg: User-provided arguments (unused, here for ioctl callback template).
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int
-dlb2_hw_start_domain(struct dlb2_hw *hw,
-		     u32 domain_id,
-		     struct dlb2_start_domain_args *arg,
-		     struct dlb2_cmd_response *resp,
-		     bool vdev_req,
-		     unsigned int vdev_id)
-{
-	struct dlb2_list_entry *iter;
-	struct dlb2_dir_pq_pair *dir_queue;
-	struct dlb2_ldb_queue *ldb_queue;
-	struct dlb2_hw_domain *domain;
-	int ret;
-	RTE_SET_USED(arg);
-	RTE_SET_USED(iter);
-
-	dlb2_log_start_domain(hw, domain_id, vdev_req, vdev_id);
-
-	ret = dlb2_verify_start_domain_args(hw,
-					    domain_id,
-					    resp,
-					    vdev_req,
-					    vdev_id);
-	if (ret)
-		return ret;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: domain not found\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	/*
-	 * Enable load-balanced and directed queue write permissions for the
-	 * queues this domain owns. Without this, the DLB2 will drop all
-	 * incoming traffic to those queues.
-	 */
-	DLB2_DOM_LIST_FOR(domain->used_ldb_queues, ldb_queue, iter) {
-		union dlb2_sys_ldb_vasqid_v r0 = { {0} };
-		unsigned int offs;
-
-		r0.field.vasqid_v = 1;
-
-		offs = domain->id.phys_id * DLB2_MAX_NUM_LDB_QUEUES +
-			ldb_queue->id.phys_id;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_LDB_VASQID_V(offs), r0.val);
-	}
-
-	DLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, dir_queue, iter) {
-		union dlb2_sys_dir_vasqid_v r0 = { {0} };
-		unsigned int offs;
-
-		r0.field.vasqid_v = 1;
-
-		offs = domain->id.phys_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) +
-			dir_queue->id.phys_id;
-
-		DLB2_CSR_WR(hw, DLB2_SYS_DIR_VASQID_V(offs), r0.val);
-	}
-
-	dlb2_flush_csr(hw);
-
-	domain->started = true;
-
-	resp->status = 0;
-
-	return 0;
-}
-
 static void dlb2_log_get_dir_queue_depth(struct dlb2_hw *hw,
 					 u32 domain_id,
 					 u32 queue_id,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +130 -0

133 lines not on this page · raw message

Signature · 1 line
2.23.0
#160 lore raw

PATCH 13/25 event/dlb2: add DLB v2.5 credit scheme

In reply to Timothy McDaniel

DLB v2.5 uses a different credit scheme than was used in DLB v2.0 . Specifically, there is a single credit pool for both load balanced and directed traffic, instead of a separate pool for each as is found with DLB v2.0.

---
 drivers/event/dlb2/dlb2.c | 311 ++++++++++++++++++++++++++------------
 1 file changed, 212 insertions(+), 99 deletions(-)
drivers/event/dlb2/dlb2.c +212 -99
index 769bcb8af..a4a7db42e 100644
@@ -436,8 +436,13 @@ dlb2_eventdev_info_get(struct rte_eventdev *dev,
 	 */
 	evdev_dlb2_default_info.max_event_ports += dlb2->num_ldb_ports;
 	evdev_dlb2_default_info.max_event_queues += dlb2->num_ldb_queues;
-	evdev_dlb2_default_info.max_num_events += dlb2->max_ldb_credits;
-
+	if (dlb2->version == DLB2_HW_V2_5) {
+		evdev_dlb2_default_info.max_num_events +=
+			dlb2->max_credits;
+	} else {
+		evdev_dlb2_default_info.max_num_events +=
+			dlb2->max_ldb_credits;
+	}
 	evdev_dlb2_default_info.max_event_queues =
 		RTE_MIN(evdev_dlb2_default_info.max_event_queues,
 			RTE_EVENT_MAX_QUEUES_PER_DEV);
@@ -451,7 +456,8 @@ dlb2_eventdev_info_get(struct rte_eventdev *dev,
 
 static int
 dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
-			    const struct dlb2_hw_rsrcs *resources_asked)
+			    const struct dlb2_hw_rsrcs *resources_asked,
+			    uint8_t device_version)
 {
 	int ret = 0;
 	struct dlb2_create_sched_domain_args *cfg;
@@ -468,8 +474,10 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
 	/* DIR ports and queues */
 
 	cfg->num_dir_ports = resources_asked->num_dir_ports;
-
-	cfg->num_dir_credits = resources_asked->num_dir_credits;
+	if (device_version == DLB2_HW_V2_5)
+		cfg->num_credits = resources_asked->num_credits;
+	else
+		cfg->num_dir_credits = resources_asked->num_dir_credits;
 
 	/* LDB queues */
 
@@ -509,8 +517,8 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
 		break;
 	}
 
-	cfg->num_ldb_credits =
-		resources_asked->num_ldb_credits;
+	if (device_version == DLB2_HW_V2)
+		cfg->num_ldb_credits = resources_asked->num_ldb_credits;
 
 	cfg->num_atomic_inflights =
 		DLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE *
@@ -519,14 +527,24 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
 	cfg->num_hist_list_entries = resources_asked->num_ldb_ports *
 		DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
 
-	DLB2_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d\n",
-		     cfg->num_ldb_queues,
-		     resources_asked->num_ldb_ports,
-		     cfg->num_dir_ports,
-		     cfg->num_atomic_inflights,
-		     cfg->num_hist_list_entries,
-		     cfg->num_ldb_credits,
-		     cfg->num_dir_credits);
+	if (device_version == DLB2_HW_V2_5) {
+		DLB2_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\n",
+			     cfg->num_ldb_queues,
+			     resources_asked->num_ldb_ports,
+			     cfg->num_dir_ports,
+			     cfg->num_atomic_inflights,
+			     cfg->num_hist_list_entries,
+			     cfg->num_credits);
+	} else {
+		DLB2_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d\n",
+			     cfg->num_ldb_queues,
+			     resources_asked->num_ldb_ports,
+			     cfg->num_dir_ports,
+			     cfg->num_atomic_inflights,
+			     cfg->num_hist_list_entries,
+			     cfg->num_ldb_credits,
+			     cfg->num_dir_credits);
+	}
 
 	/* Configure the QM */
 
@@ -606,7 +624,6 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)
 	 */
 	if (dlb2->configured) {
 		dlb2_hw_reset_sched_domain(dev, true);
-
 		ret = dlb2_hw_query_resources(dlb2);
 		if (ret) {
 			DLB2_LOG_ERR("get resources err=%d, devid=%d\n",
@@ -665,20 +682,26 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)
 	/* 1 dir queue per dir port */
 	rsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;
 
-	/* Scale down nb_events_limit by 4 for directed credits, since there
-	 * are 4x as many load-balanced credits.
-	 */
-	rsrcs->num_ldb_credits = 0;
-	rsrcs->num_dir_credits = 0;
+	if (dlb2->version == DLB2_HW_V2_5) {
+		rsrcs->num_credits = 0;
+		if (rsrcs->num_ldb_queues || rsrcs->num_dir_ports)
+			rsrcs->num_credits = config->nb_events_limit;
+	} else {
+		/* Scale down nb_events_limit by 4 for directed credits,
+		 * since there are 4x as many load-balanced credits.
+		 */
+		rsrcs->num_ldb_credits = 0;
+		rsrcs->num_dir_credits = 0;
 
-	if (rsrcs->num_ldb_queues)
-		rsrcs->num_ldb_credits = config->nb_events_limit;
-	if (rsrcs->num_dir_ports)
-		rsrcs->num_dir_credits = config->nb_events_limit / 4;
-	if (dlb2->num_dir_credits_override != -1)
-		rsrcs->num_dir_credits = dlb2->num_dir_credits_override;
+		if (rsrcs->num_ldb_queues)
+			rsrcs->num_ldb_credits = config->nb_events_limit;
+		if (rsrcs->num_dir_ports)
+			rsrcs->num_dir_credits = config->nb_events_limit / 4;
+		if (dlb2->num_dir_credits_override != -1)
+			rsrcs->num_dir_credits = dlb2->num_dir_credits_override;
+	}
 
-	if (dlb2_hw_create_sched_domain(handle, rsrcs) < 0) {
+	if (dlb2_hw_create_sched_domain(handle, rsrcs, dlb2->version) < 0) {
 		DLB2_LOG_ERR("dlb2_hw_create_sched_domain failed\n");
 		return -ENODEV;
 	}
@@ -693,10 +716,15 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)
 	dlb2->num_ldb_ports = dlb2->num_ports - dlb2->num_dir_ports;
 	dlb2->num_ldb_queues = dlb2->num_queues - dlb2->num_dir_ports;
 	dlb2->num_dir_queues = dlb2->num_dir_ports;
-	dlb2->ldb_credit_pool = rsrcs->num_ldb_credits;
-	dlb2->max_ldb_credits = rsrcs->num_ldb_credits;
-	dlb2->dir_credit_pool = rsrcs->num_dir_credits;
-	dlb2->max_dir_credits = rsrcs->num_dir_credits;
+	if (dlb2->version == DLB2_HW_V2_5) {
+		dlb2->credit_pool = rsrcs->num_credits;
+		dlb2->max_credits = rsrcs->num_credits;
+	} else {
+		dlb2->ldb_credit_pool = rsrcs->num_ldb_credits;
+		dlb2->max_ldb_credits = rsrcs->num_ldb_credits;
+		dlb2->dir_credit_pool = rsrcs->num_dir_credits;
+		dlb2->max_dir_credits = rsrcs->num_dir_credits;
+	}
 
 	dlb2->configured = true;
 
@@ -1170,8 +1198,9 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
 	struct dlb2_port *qm_port = NULL;
 	char mz_name[RTE_MEMZONE_NAMESIZE];
 	uint32_t qm_port_id;
-	uint16_t ldb_credit_high_watermark;
-	uint16_t dir_credit_high_watermark;
+	uint16_t ldb_credit_high_watermark = 0;
+	uint16_t dir_credit_high_watermark = 0;
+	uint16_t credit_high_watermark = 0;
 
 	if (handle == NULL)
 		return -EINVAL;
@@ -1206,15 +1235,18 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
 	/* User controls the LDB high watermark via enqueue depth. The DIR high
 	 * watermark is equal, unless the directed credit pool is too small.
 	 */
-	ldb_credit_high_watermark = enqueue_depth;
-
-	/* If there are no directed ports, the kernel driver will ignore this
-	 * port's directed credit settings. Don't use enqueue_depth if it would
-	 * require more directed credits than are available.
-	 */
-	dir_credit_high_watermark =
-		RTE_MIN(enqueue_depth,
-			handle->cfg.num_dir_credits / dlb2->num_ports);
+	if (dlb2->version == DLB2_HW_V2) {
+		ldb_credit_high_watermark = enqueue_depth;
+		/* If there are no directed ports, the kernel driver will
+		 * ignore this port's directed credit settings. Don't use
+		 * enqueue_depth if it would require more directed credits
+		 * than are available.
+		 */
+		dir_credit_high_watermark =
+			RTE_MIN(enqueue_depth,
+				handle->cfg.num_dir_credits / dlb2->num_ports);
+	} else
+		credit_high_watermark = enqueue_depth;
 
 	/* Per QM values */
 
@@ -1249,8 +1281,12 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
 
 	qm_port->id = qm_port_id;
 
-	qm_port->cached_ldb_credits = 0;
-	qm_port->cached_dir_credits = 0;
+	if (dlb2->version == DLB2_HW_V2) {
+		qm_port->cached_ldb_credits = 0;
+		qm_port->cached_dir_credits = 0;
+	} else
+		qm_port->cached_credits = 0;
+
 	/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
 	 * the effective depth is smaller.
 	 */
@@ -1298,17 +1334,26 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
 	qm_port->state = PORT_STARTED; /* enabled at create time */
 	qm_port->config_state = DLB2_CONFIGURED;
 
-	qm_port->dir_credits = dir_credit_high_watermark;
-	qm_port->ldb_credits = ldb_credit_high_watermark;
-	qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
-	qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
-
-	DLB2_LOG_DBG("dlb2: created ldb port %d, depth = %d, ldb credits=%d, dir credits=%d\n",
-		     qm_port_id,
-		     dequeue_depth,
-		     qm_port->ldb_credits,
-		     qm_port->dir_credits);
+	if (dlb2->version == DLB2_HW_V2) {
+		qm_port->dir_credits = dir_credit_high_watermark;
+		qm_port->ldb_credits = ldb_credit_high_watermark;
+		qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
+		qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
+
+		DLB2_LOG_DBG("dlb2: created ldb port %d, depth = %d, ldb credits=%d, dir credits=%d\n",
+			     qm_port_id,
+			     dequeue_depth,
+			     qm_port->ldb_credits,
+			     qm_port->dir_credits);
+	} else {
+		qm_port->credits = credit_high_watermark;
+		qm_port->credit_pool[DLB2_COMBINED_POOL] = &dlb2->credit_pool;
 
+		DLB2_LOG_DBG("dlb2: created ldb port %d, depth = %d, credits=%d\n",
+			     qm_port_id,
+			     dequeue_depth,
+			     qm_port->credits);
+	}
 	rte_spinlock_unlock(&handle->resource_lock);
 
 	return 0;
@@ -1356,8 +1401,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
 	struct dlb2_port *qm_port = NULL;
 	char mz_name[RTE_MEMZONE_NAMESIZE];
 	uint32_t qm_port_id;
-	uint16_t ldb_credit_high_watermark;
-	uint16_t dir_credit_high_watermark;
+	uint16_t ldb_credit_high_watermark = 0;
+	uint16_t dir_credit_high_watermark = 0;
+	uint16_t credit_high_watermark = 0;
 
 	if (dlb2 == NULL || handle == NULL)
 		return -EINVAL;
@@ -1386,14 +1432,16 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
 	/* User controls the LDB high watermark via enqueue depth. The DIR high
 	 * watermark is equal, unless the directed credit pool is too small.
 	 */
-	ldb_credit_high_watermark = enqueue_depth;
-
-	/* Don't use enqueue_depth if it would require more directed credits
-	 * than are available.
-	 */
-	dir_credit_high_watermark =
-		RTE_MIN(enqueue_depth,
-			handle->cfg.num_dir_credits / dlb2->num_ports);
+	if (dlb2->version == DLB2_HW_V2) {
+		ldb_credit_high_watermark = enqueue_depth;
+		/* Don't use enqueue_depth if it would require more directed
+		 * credits than are available.
+		 */
+		dir_credit_high_watermark =
+			RTE_MIN(enqueue_depth,
+				handle->cfg.num_dir_credits / dlb2->num_ports);
+	} else
+		credit_high_watermark = enqueue_depth;
 
 	/* Per QM values */
 
@@ -1430,8 +1478,12 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
 
 	qm_port->id = qm_port_id;
 
-	qm_port->cached_ldb_credits = 0;
-	qm_port->cached_dir_credits = 0;
+	if (dlb2->version == DLB2_HW_V2) {
+		qm_port->cached_ldb_credits = 0;
+		qm_port->cached_dir_credits = 0;
+	} else
+		qm_port->cached_credits = 0;
+
 	/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
 	 * the effective depth is smaller.
 	 */
@@ -1467,17 +1519,26 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
 	qm_port->state = PORT_STARTED; /* enabled at create time */
 	qm_port->config_state = DLB2_CONFIGURED;
 
-	qm_port->dir_credits = dir_credit_high_watermark;
-	qm_port->ldb_credits = ldb_credit_high_watermark;
-	qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
-	qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
-
-	DLB2_LOG_DBG("dlb2: created dir port %d, depth = %d cr=%d,%d\n",
-		     qm_port_id,
-		     dequeue_depth,
-		     dir_credit_high_watermark,
-		     ldb_credit_high_watermark);
+	if (dlb2->version == DLB2_HW_V2) {
+		qm_port->dir_credits = dir_credit_high_watermark;
+		qm_port->ldb_credits = ldb_credit_high_watermark;
+		qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
+		qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
+
+		DLB2_LOG_DBG("dlb2: created dir port %d, depth = %d cr=%d,%d\n",
+			     qm_port_id,
+			     dequeue_depth,
+			     dir_credit_high_watermark,
+			     ldb_credit_high_watermark);
+	} else {
+		qm_port->credits = credit_high_watermark;
+		qm_port->credit_pool[DLB2_COMBINED_POOL] = &dlb2->credit_pool;
 
+		DLB2_LOG_DBG("dlb2: created dir port %d, depth = %d cr=%d\n",
+			     qm_port_id,
+			     dequeue_depth,
+			     credit_high_watermark);
+	}
 	rte_spinlock_unlock(&handle->resource_lock);
 
 	return 0;
@@ -2297,6 +2358,24 @@ dlb2_check_enqueue_hw_dir_credits(struct dlb2_port *qm_port)
 	return 0;
 }
 
+static inline int
+dlb2_check_enqueue_hw_credits(struct dlb2_port *qm_port)
+{
+	if (unlikely(qm_port->cached_credits == 0)) {
+		qm_port->cached_credits =
+			dlb2_port_credits_get(qm_port,
+					      DLB2_COMBINED_POOL);
+		if (unlikely(qm_port->cached_credits == 0)) {
+			DLB2_INC_STAT(
+			qm_port->ev_port->stats.traffic.tx_nospc_hw_credits, 1);
+			DLB2_LOG_DBG("credits exhausted\n");
+			return 1; /* credits exhausted */
+		}
+	}
+
+	return 0;
+}
+
 static __rte_always_inline void
 dlb2_pp_write(struct dlb2_enqueue_qe *qe4,
 	      struct process_local_port_data *port_data)
@@ -2565,12 +2644,19 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,
 	if (!qm_queue->is_directed) {
 		/* Load balanced destination queue */
 
-		if (dlb2_check_enqueue_hw_ldb_credits(qm_port)) {
-			rte_errno = -ENOSPC;
-			return 1;
+		if (dlb2->version == DLB2_HW_V2) {
+			if (dlb2_check_enqueue_hw_ldb_credits(qm_port)) {
+				rte_errno = -ENOSPC;
+				return 1;
+			}
+			cached_credits = &qm_port->cached_ldb_credits;
+		} else {
+			if (dlb2_check_enqueue_hw_credits(qm_port)) {
+				rte_errno = -ENOSPC;
+				return 1;
+			}
+			cached_credits = &qm_port->cached_credits;
 		}
-		cached_credits = &qm_port->cached_ldb_credits;
-
 		switch (ev->sched_type) {
 		case RTE_SCHED_TYPE_ORDERED:
 			DLB2_LOG_DBG("dlb2: put_qe: RTE_SCHED_TYPE_ORDERED\n");
@@ -2602,12 +2688,19 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,
 	} else {
 		/* Directed destination queue */
 
-		if (dlb2_check_enqueue_hw_dir_credits(qm_port)) {
-			rte_errno = -ENOSPC;
-			return 1;
+		if (dlb2->version == DLB2_HW_V2) {
+			if (dlb2_check_enqueue_hw_dir_credits(qm_port)) {
+				rte_errno = -ENOSPC;
+				return 1;
+			}
+			cached_credits = &qm_port->cached_dir_credits;
+		} else {
+			if (dlb2_check_enqueue_hw_credits(qm_port)) {
+				rte_errno = -ENOSPC;
+				return 1;
+			}
+			cached_credits = &qm_port->cached_credits;
 		}
-		cached_credits = &qm_port->cached_dir_credits;
-
 		DLB2_LOG_DBG("dlb2: put_qe: RTE_SCHED_TYPE_DIRECTED\n");
 
 		*sched_type = DLB2_SCHED_DIRECTED;
@@ -2891,20 +2984,40 @@ dlb2_port_credits_inc(struct dlb2_port *qm_port, int num)
 
 	/* increment port credits, and return to pool if exceeds threshold */
 	if (!qm_port->is_directed) {
-		qm_port->cached_ldb_credits += num;
-		if (qm_port->cached_ldb_credits >= 2 * batch_size) {
-			__atomic_fetch_add(
-				qm_port->credit_pool[DLB2_LDB_QUEUE],
-				batch_size, __ATOMIC_SEQ_CST);
-			qm_port->cached_ldb_credits -= batch_size;
+		if (qm_port->dlb2->version == DLB2_HW_V2) {
+			qm_port->cached_ldb_credits += num;
+			if (qm_port->cached_ldb_credits >= 2 * batch_size) {
+				__atomic_fetch_add(
+					qm_port->credit_pool[DLB2_LDB_QUEUE],
+					batch_size, __ATOMIC_SEQ_CST);
+				qm_port->cached_ldb_credits -= batch_size;
+			}
+		} else {
+			qm_port->cached_credits += num;
+			if (qm_port->cached_credits >= 2 * batch_size) {
+				__atomic_fetch_add(
+				      qm_port->credit_pool[DLB2_COMBINED_POOL],
+				      batch_size, __ATOMIC_SEQ_CST);
+				qm_port->cached_credits -= batch_size;
+			}
 		}
 	} else {
-		qm_port->cached_dir_credits += num;
-		if (qm_port->cached_dir_credits >= 2 * batch_size) {
-			__atomic_fetch_add(
-				qm_port->credit_pool[DLB2_DIR_QUEUE],
-				batch_size, __ATOMIC_SEQ_CST);
-			qm_port->cached_dir_credits -= batch_size;
+		if (qm_port->dlb2->version == DLB2_HW_V2) {
+			qm_port->cached_dir_credits += num;
+			if (qm_port->cached_dir_credits >= 2 * batch_size) {
+				__atomic_fetch_add(
+					qm_port->credit_pool[DLB2_DIR_QUEUE],
+					batch_size, __ATOMIC_SEQ_CST);
+				qm_port->cached_dir_credits -= batch_size;
+			}
+		} else {
+			qm_port->cached_credits += num;
+			if (qm_port->cached_credits >= 2 * batch_size) {
+				__atomic_fetch_add(
+				      qm_port->credit_pool[DLB2_COMBINED_POOL],
+				      batch_size, __ATOMIC_SEQ_CST);
+				qm_port->cached_credits -= batch_size;
+			}
 		}
 	}
 }
Signature · 1 line
2.23.0
#161 lore raw

PATCH 14/25 event/dlb2: Add DLB v2.5 support to get queue depth functions

In reply to Timothy McDaniel

Update get queue depth functions for DLB v2.5, accounting for combined register map and new hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    |  29 ----
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 135 ++++++++++++++++++
 2 files changed, 135 insertions(+), 29 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -29
index 6b5c8ba01..1066b8834 100644
@@ -66,17 +66,6 @@ static inline void dlb2_flush_csr(struct dlb2_hw *hw)
 	DLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);
 }
 
-static u32 dlb2_dir_queue_depth(struct dlb2_hw *hw,
-				struct dlb2_dir_pq_pair *queue)
-{
-	union dlb2_lsp_qid_dir_enqueue_cnt r0;
-
-	r0.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_DIR_ENQUEUE_CNT(queue->id.phys_id));
-
-	return r0.field.count;
-}
-
 static void dlb2_ldb_port_cq_enable(struct dlb2_hw *hw,
 				    struct dlb2_ldb_port *port)
 {
@@ -109,24 +98,6 @@ static void dlb2_ldb_port_cq_disable(struct dlb2_hw *hw,
 	dlb2_flush_csr(hw);
 }
 
-static u32 dlb2_ldb_queue_depth(struct dlb2_hw *hw,
-				struct dlb2_ldb_queue *queue)
-{
-	union dlb2_lsp_qid_aqed_active_cnt r0;
-	union dlb2_lsp_qid_atm_active r1;
-	union dlb2_lsp_qid_ldb_enqueue_cnt r2;
-
-	r0.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_AQED_ACTIVE_CNT(queue->id.phys_id));
-	r1.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_ATM_ACTIVE(queue->id.phys_id));
-
-	r2.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_LDB_ENQUEUE_CNT(queue->id.phys_id));
-
-	return r0.field.count + r1.field.count + r2.field.count;
-}
-
 static struct dlb2_ldb_queue *
 dlb2_get_ldb_queue_from_id(struct dlb2_hw *hw,
 			   u32 id,
drivers/event/dlb2/pf/base/dlb2_resource_new.c +135 -0

138 lines not on this page · raw message

Signature · 1 line
2.23.0
#162 lore raw

PATCH 15/25 event/dlb2: add DLB v2.5 finish map/unmap interfaces

In reply to Timothy McDaniel

Update low level hardware funcs with map/unmap interfaces, accounting for new combined register file and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 1043 -----------------
 .../event/dlb2/pf/base/dlb2_resource_new.c    |   50 +
 2 files changed, 50 insertions(+), 1043 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -1043
index 1066b8834..d66442c19 100644
@@ -66,1049 +66,6 @@ static inline void dlb2_flush_csr(struct dlb2_hw *hw)
 	DLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);
 }
 
-static void dlb2_ldb_port_cq_enable(struct dlb2_hw *hw,
-				    struct dlb2_ldb_port *port)
-{
-	union dlb2_lsp_cq_ldb_dsbl reg;
-
-	/*
-	 * Don't re-enable the port if a removal is pending. The caller should
-	 * mark this port as enabled (if it isn't already), and when the
-	 * removal completes the port will be enabled.
-	 */
-	if (port->num_pending_removals)
-		return;
-
-	reg.field.disabled = 0;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id), reg.val);
-
-	dlb2_flush_csr(hw);
-}
-
-static void dlb2_ldb_port_cq_disable(struct dlb2_hw *hw,
-				     struct dlb2_ldb_port *port)
-{
-	union dlb2_lsp_cq_ldb_dsbl reg;
-
-	reg.field.disabled = 1;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id), reg.val);
-
-	dlb2_flush_csr(hw);
-}
-
-static struct dlb2_ldb_queue *
-dlb2_get_ldb_queue_from_id(struct dlb2_hw *hw,
-			   u32 id,
-			   bool vdev_req,
-			   unsigned int vdev_id)
-{
-	struct dlb2_list_entry *iter1;
-	struct dlb2_list_entry *iter2;
-	struct dlb2_function_resources *rsrcs;
-	struct dlb2_hw_domain *domain;
-	struct dlb2_ldb_queue *queue;
-	RTE_SET_USED(iter1);
-	RTE_SET_USED(iter2);
-
-	if (id >= DLB2_MAX_NUM_LDB_QUEUES)
-		return NULL;
-
-	rsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;
-
-	if (!vdev_req)
-		return &hw->rsrcs.ldb_queues[id];
-
-	DLB2_FUNC_LIST_FOR(rsrcs->used_domains, domain, iter1) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter2)
-			if (queue->id.virt_id == id)
-				return queue;
-	}
-
-	DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_queues, queue, iter1)
-		if (queue->id.virt_id == id)
-			return queue;
-
-	return NULL;
-}
-
-static struct dlb2_hw_domain *dlb2_get_domain_from_id(struct dlb2_hw *hw,
-						      u32 id,
-						      bool vdev_req,
-						      unsigned int vdev_id)
-{
-	struct dlb2_list_entry *iteration;
-	struct dlb2_function_resources *rsrcs;
-	struct dlb2_hw_domain *domain;
-	RTE_SET_USED(iteration);
-
-	if (id >= DLB2_MAX_NUM_DOMAINS)
-		return NULL;
-
-	if (!vdev_req)
-		return &hw->domains[id];
-
-	rsrcs = &hw->vdev[vdev_id];
-
-	DLB2_FUNC_LIST_FOR(rsrcs->used_domains, domain, iteration)
-		if (domain->id.virt_id == id)
-			return domain;
-
-	return NULL;
-}
-
-static int dlb2_port_slot_state_transition(struct dlb2_hw *hw,
-					   struct dlb2_ldb_port *port,
-					   struct dlb2_ldb_queue *queue,
-					   int slot,
-					   enum dlb2_qid_map_state new_state)
-{
-	enum dlb2_qid_map_state curr_state = port->qid_map[slot].state;
-	struct dlb2_hw_domain *domain;
-	int domain_id;
-
-	domain_id = port->domain_id.phys_id;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, false, 0);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s()] Internal error: unable to find domain %d\n",
-			    __func__, domain_id);
-		return -EINVAL;
-	}
-
-	switch (curr_state) {
-	case DLB2_QUEUE_UNMAPPED:
-		switch (new_state) {
-		case DLB2_QUEUE_MAPPED:
-			queue->num_mappings++;
-			port->num_mappings++;
-			break;
-		case DLB2_QUEUE_MAP_IN_PROG:
-			queue->num_pending_additions++;
-			domain->num_pending_additions++;
-			break;
-		default:
-			goto error;
-		}
-		break;
-	case DLB2_QUEUE_MAPPED:
-		switch (new_state) {
-		case DLB2_QUEUE_UNMAPPED:
-			queue->num_mappings--;
-			port->num_mappings--;
-			break;
-		case DLB2_QUEUE_UNMAP_IN_PROG:
-			port->num_pending_removals++;
-			domain->num_pending_removals++;
-			break;
-		case DLB2_QUEUE_MAPPED:
-			/* Priority change, nothing to update */
-			break;
-		default:
-			goto error;
-		}
-		break;
-	case DLB2_QUEUE_MAP_IN_PROG:
-		switch (new_state) {
-		case DLB2_QUEUE_UNMAPPED:
-			queue->num_pending_additions--;
-			domain->num_pending_additions--;
-			break;
-		case DLB2_QUEUE_MAPPED:
-			queue->num_mappings++;
-			port->num_mappings++;
-			queue->num_pending_additions--;
-			domain->num_pending_additions--;
-			break;
-		default:
-			goto error;
-		}
-		break;
-	case DLB2_QUEUE_UNMAP_IN_PROG:
-		switch (new_state) {
-		case DLB2_QUEUE_UNMAPPED:
-			port->num_pending_removals--;
-			domain->num_pending_removals--;
-			queue->num_mappings--;
-			port->num_mappings--;
-			break;
-		case DLB2_QUEUE_MAPPED:
-			port->num_pending_removals--;
-			domain->num_pending_removals--;
-			break;
-		case DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP:
-			/* Nothing to update */
-			break;
-		default:
-			goto error;
-		}
-		break;
-	case DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP:
-		switch (new_state) {
-		case DLB2_QUEUE_UNMAP_IN_PROG:
-			/* Nothing to update */
-			break;
-		case DLB2_QUEUE_UNMAPPED:
-			/*
-			 * An UNMAP_IN_PROG_PENDING_MAP slot briefly
-			 * becomes UNMAPPED before it transitions to
-			 * MAP_IN_PROG.
-			 */
-			queue->num_mappings--;
-			port->num_mappings--;
-			port->num_pending_removals--;
-			domain->num_pending_removals--;
-			break;
-		default:
-			goto error;
-		}
-		break;
-	default:
-		goto error;
-	}
-
-	port->qid_map[slot].state = new_state;
-
-	DLB2_HW_DBG(hw,
-		    "[%s()] queue %d -> port %d state transition (%d -> %d)\n",
-		    __func__, queue->id.phys_id, port->id.phys_id,
-		    curr_state, new_state);
-	return 0;
-
-error:
-	DLB2_HW_ERR(hw,
-		    "[%s()] Internal error: invalid queue %d -> port %d state transition (%d -> %d)\n",
-		    __func__, queue->id.phys_id, port->id.phys_id,
-		    curr_state, new_state);
-	return -EFAULT;
-}
-
-static bool dlb2_port_find_slot(struct dlb2_ldb_port *port,
-				enum dlb2_qid_map_state state,
-				int *slot)
-{
-	int i;
-
-	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
-		if (port->qid_map[i].state == state)
-			break;
-	}
-
-	*slot = i;
-
-	return (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);
-}
-
-static bool dlb2_port_find_slot_queue(struct dlb2_ldb_port *port,
-				      enum dlb2_qid_map_state state,
-				      struct dlb2_ldb_queue *queue,
-				      int *slot)
-{
-	int i;
-
-	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
-		if (port->qid_map[i].state == state &&
-		    port->qid_map[i].qid == queue->id.phys_id)
-			break;
-	}
-
-	*slot = i;
-
-	return (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);
-}
-
-/*
- * dlb2_ldb_queue_{enable, disable}_mapped_cqs() don't operate exactly as
- * their function names imply, and should only be called by the dynamic CQ
- * mapping code.
- */
-static void dlb2_ldb_queue_disable_mapped_cqs(struct dlb2_hw *hw,
-					      struct dlb2_hw_domain *domain,
-					      struct dlb2_ldb_queue *queue)
-{
-	struct dlb2_list_entry *iter;
-	struct dlb2_ldb_port *port;
-	int slot, i;
-	RTE_SET_USED(iter);
-
-	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {
-			enum dlb2_qid_map_state state = DLB2_QUEUE_MAPPED;
-
-			if (!dlb2_port_find_slot_queue(port, state,
-						       queue, &slot))
-				continue;
-
-			if (port->enabled)
-				dlb2_ldb_port_cq_disable(hw, port);
-		}
-	}
-}
-
-static void dlb2_ldb_queue_enable_mapped_cqs(struct dlb2_hw *hw,
-					     struct dlb2_hw_domain *domain,
-					     struct dlb2_ldb_queue *queue)
-{
-	struct dlb2_list_entry *iter;
-	struct dlb2_ldb_port *port;
-	int slot, i;
-	RTE_SET_USED(iter);
-
-	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {
-			enum dlb2_qid_map_state state = DLB2_QUEUE_MAPPED;
-
-			if (!dlb2_port_find_slot_queue(port, state,
-						       queue, &slot))
-				continue;
-
-			if (port->enabled)
-				dlb2_ldb_port_cq_enable(hw, port);
-		}
-	}
-}
-
-static void dlb2_ldb_port_clear_queue_if_status(struct dlb2_hw *hw,
-						struct dlb2_ldb_port *port,
-						int slot)
-{
-	union dlb2_lsp_ldb_sched_ctrl r0 = { {0} };
-
-	r0.field.cq = port->id.phys_id;
-	r0.field.qidix = slot;
-	r0.field.value = 0;
-	r0.field.inflight_ok_v = 1;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r0.val);
-
-	dlb2_flush_csr(hw);
-}
-
-static void dlb2_ldb_port_set_queue_if_status(struct dlb2_hw *hw,
-					      struct dlb2_ldb_port *port,
-					      int slot)
-{
-	union dlb2_lsp_ldb_sched_ctrl r0 = { {0} };
-
-	r0.field.cq = port->id.phys_id;
-	r0.field.qidix = slot;
-	r0.field.value = 1;
-	r0.field.inflight_ok_v = 1;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r0.val);
-
-	dlb2_flush_csr(hw);
-}
-
-static int dlb2_ldb_port_map_qid_static(struct dlb2_hw *hw,
-					struct dlb2_ldb_port *p,
-					struct dlb2_ldb_queue *q,
-					u8 priority)
-{
-	union dlb2_lsp_cq2priov r0;
-	union dlb2_lsp_cq2qid0 r1;
-	union dlb2_atm_qid2cqidix_00 r2;
-	union dlb2_lsp_qid2cqidix_00 r3;
-	union dlb2_lsp_qid2cqidix2_00 r4;
-	enum dlb2_qid_map_state state;
-	int i;
-
-	/* Look for a pending or already mapped slot, else an unused slot */
-	if (!dlb2_port_find_slot_queue(p, DLB2_QUEUE_MAP_IN_PROG, q, &i) &&
-	    !dlb2_port_find_slot_queue(p, DLB2_QUEUE_MAPPED, q, &i) &&
-	    !dlb2_port_find_slot(p, DLB2_QUEUE_UNMAPPED, &i)) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: CQ has no available QID mapping slots\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port slot tracking failed\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	/* Read-modify-write the priority and valid bit register */
-	r0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(p->id.phys_id));
-
-	r0.field.v |= 1 << i;
-	r0.field.prio |= (priority & 0x7) << i * 3;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(p->id.phys_id), r0.val);
-
-	/* Read-modify-write the QID map register */
-	if (i < 4)
-		r1.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2QID0(p->id.phys_id));
-	else
-		r1.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2QID1(p->id.phys_id));
-
-	if (i == 0 || i == 4)
-		r1.field.qid_p0 = q->id.phys_id;
-	if (i == 1 || i == 5)
-		r1.field.qid_p1 = q->id.phys_id;
-	if (i == 2 || i == 6)
-		r1.field.qid_p2 = q->id.phys_id;
-	if (i == 3 || i == 7)
-		r1.field.qid_p3 = q->id.phys_id;
-
-	if (i < 4)
-		DLB2_CSR_WR(hw, DLB2_LSP_CQ2QID0(p->id.phys_id), r1.val);
-	else
-		DLB2_CSR_WR(hw, DLB2_LSP_CQ2QID1(p->id.phys_id), r1.val);
-
-	r2.val = DLB2_CSR_RD(hw,
-			     DLB2_ATM_QID2CQIDIX(q->id.phys_id,
-						 p->id.phys_id / 4));
-
-	r3.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID2CQIDIX(q->id.phys_id,
-						 p->id.phys_id / 4));
-
-	r4.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID2CQIDIX2(q->id.phys_id,
-						  p->id.phys_id / 4));
-
-	switch (p->id.phys_id % 4) {
-	case 0:
-		r2.field.cq_p0 |= 1 << i;
-		r3.field.cq_p0 |= 1 << i;
-		r4.field.cq_p0 |= 1 << i;
-		break;
-
-	case 1:
-		r2.field.cq_p1 |= 1 << i;
-		r3.field.cq_p1 |= 1 << i;
-		r4.field.cq_p1 |= 1 << i;
-		break;
-
-	case 2:
-		r2.field.cq_p2 |= 1 << i;
-		r3.field.cq_p2 |= 1 << i;
-		r4.field.cq_p2 |= 1 << i;
-		break;
-
-	case 3:
-		r2.field.cq_p3 |= 1 << i;
-		r3.field.cq_p3 |= 1 << i;
-		r4.field.cq_p3 |= 1 << i;
-		break;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_ATM_QID2CQIDIX(q->id.phys_id, p->id.phys_id / 4),
-		    r2.val);
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID2CQIDIX(q->id.phys_id, p->id.phys_id / 4),
-		    r3.val);
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID2CQIDIX2(q->id.phys_id, p->id.phys_id / 4),
-		    r4.val);
-
-	dlb2_flush_csr(hw);
-
-	p->qid_map[i].qid = q->id.phys_id;
-	p->qid_map[i].priority = priority;
-
-	state = DLB2_QUEUE_MAPPED;
-
-	return dlb2_port_slot_state_transition(hw, p, q, i, state);
-}
-
-static int dlb2_ldb_port_set_has_work_bits(struct dlb2_hw *hw,
-					   struct dlb2_ldb_port *port,
-					   struct dlb2_ldb_queue *queue,
-					   int slot)
-{
-	union dlb2_lsp_qid_aqed_active_cnt r0;
-	union dlb2_lsp_qid_ldb_enqueue_cnt r1;
-	union dlb2_lsp_ldb_sched_ctrl r2 = { {0} };
-
-	/* Set the atomic scheduling haswork bit */
-	r0.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_AQED_ACTIVE_CNT(queue->id.phys_id));
-
-	r2.field.cq = port->id.phys_id;
-	r2.field.qidix = slot;
-	r2.field.value = 1;
-	r2.field.rlist_haswork_v = r0.field.count > 0;
-
-	/* Set the non-atomic scheduling haswork bit */
-	DLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);
-
-	r1.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_LDB_ENQUEUE_CNT(queue->id.phys_id));
-
-	memset(&r2, 0, sizeof(r2));
-
-	r2.field.cq = port->id.phys_id;
-	r2.field.qidix = slot;
-	r2.field.value = 1;
-	r2.field.nalb_haswork_v = (r1.field.count > 0);
-
-	DLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);
-
-	dlb2_flush_csr(hw);
-
-	return 0;
-}
-
-static void dlb2_ldb_port_clear_has_work_bits(struct dlb2_hw *hw,
-					      struct dlb2_ldb_port *port,
-					      u8 slot)
-{
-	union dlb2_lsp_ldb_sched_ctrl r2 = { {0} };
-
-	r2.field.cq = port->id.phys_id;
-	r2.field.qidix = slot;
-	r2.field.value = 0;
-	r2.field.rlist_haswork_v = 1;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);
-
-	memset(&r2, 0, sizeof(r2));
-
-	r2.field.cq = port->id.phys_id;
-	r2.field.qidix = slot;
-	r2.field.value = 0;
-	r2.field.nalb_haswork_v = 1;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);
-
-	dlb2_flush_csr(hw);
-}
-
-static void dlb2_ldb_queue_set_inflight_limit(struct dlb2_hw *hw,
-					      struct dlb2_ldb_queue *queue)
-{
-	union dlb2_lsp_qid_ldb_infl_lim r0 = { {0} };
-
-	r0.field.limit = queue->num_qid_inflights;
-
-	DLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), r0.val);
-}
-
-static void dlb2_ldb_queue_clear_inflight_limit(struct dlb2_hw *hw,
-						struct dlb2_ldb_queue *queue)
-{
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id),
-		    DLB2_LSP_QID_LDB_INFL_LIM_RST);
-}
-
-static int dlb2_ldb_port_finish_map_qid_dynamic(struct dlb2_hw *hw,
-						struct dlb2_hw_domain *domain,
-						struct dlb2_ldb_port *port,
-						struct dlb2_ldb_queue *queue)
-{
-	struct dlb2_list_entry *iter;
-	union dlb2_lsp_qid_ldb_infl_cnt r0;
-	enum dlb2_qid_map_state state;
-	int slot, ret, i;
-	u8 prio;
-	RTE_SET_USED(iter);
-
-	r0.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));
-
-	if (r0.field.count) {
-		DLB2_HW_ERR(hw,
-			    "[%s()] Internal error: non-zero QID inflight count\n",
-			    __func__);
-		return -EINVAL;
-	}
-
-	/*
-	 * Static map the port and set its corresponding has_work bits.
-	 */
-	state = DLB2_QUEUE_MAP_IN_PROG;
-	if (!dlb2_port_find_slot_queue(port, state, queue, &slot))
-		return -EINVAL;
-
-	if (slot >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port slot tracking failed\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	prio = port->qid_map[slot].priority;
-
-	/*
-	 * Update the CQ2QID, CQ2PRIOV, and QID2CQIDX registers, and
-	 * the port's qid_map state.
-	 */
-	ret = dlb2_ldb_port_map_qid_static(hw, port, queue, prio);
-	if (ret)
-		return ret;
-
-	ret = dlb2_ldb_port_set_has_work_bits(hw, port, queue, slot);
-	if (ret)
-		return ret;
-
-	/*
-	 * Ensure IF_status(cq,qid) is 0 before enabling the port to
-	 * prevent spurious schedules to cause the queue's inflight
-	 * count to increase.
-	 */
-	dlb2_ldb_port_clear_queue_if_status(hw, port, slot);
-
-	/* Reset the queue's inflight status */
-	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {
-			state = DLB2_QUEUE_MAPPED;
-			if (!dlb2_port_find_slot_queue(port, state,
-						       queue, &slot))
-				continue;
-
-			dlb2_ldb_port_set_queue_if_status(hw, port, slot);
-		}
-	}
-
-	dlb2_ldb_queue_set_inflight_limit(hw, queue);
-
-	/* Re-enable CQs mapped to this queue */
-	dlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);
-
-	/* If this queue has other mappings pending, clear its inflight limit */
-	if (queue->num_pending_additions > 0)
-		dlb2_ldb_queue_clear_inflight_limit(hw, queue);
-
-	return 0;
-}
-
-/**
- * dlb2_ldb_port_map_qid_dynamic() - perform a "dynamic" QID->CQ mapping
- * @hw: dlb2_hw handle for a particular device.
- * @port: load-balanced port
- * @queue: load-balanced queue
- * @priority: queue servicing priority
- *
- * Returns 0 if the queue was mapped, 1 if the mapping is scheduled to occur
- * at a later point, and <0 if an error occurred.
- */
-static int dlb2_ldb_port_map_qid_dynamic(struct dlb2_hw *hw,
-					 struct dlb2_ldb_port *port,
-					 struct dlb2_ldb_queue *queue,
-					 u8 priority)
-{
-	union dlb2_lsp_qid_ldb_infl_cnt r0 = { {0} };
-	enum dlb2_qid_map_state state;
-	struct dlb2_hw_domain *domain;
-	int domain_id, slot, ret;
-
-	domain_id = port->domain_id.phys_id;
-
-	domain = dlb2_get_domain_from_id(hw, domain_id, false, 0);
-	if (domain == NULL) {
-		DLB2_HW_ERR(hw,
-			    "[%s()] Internal error: unable to find domain %d\n",
-			    __func__, port->domain_id.phys_id);
-		return -EINVAL;
-	}
-
-	/*
-	 * Set the QID inflight limit to 0 to prevent further scheduling of the
-	 * queue.
-	 */
-	DLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), 0);
-
-	if (!dlb2_port_find_slot(port, DLB2_QUEUE_UNMAPPED, &slot)) {
-		DLB2_HW_ERR(hw,
-			    "Internal error: No available unmapped slots\n");
-		return -EFAULT;
-	}
-
-	if (slot >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port slot tracking failed\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	port->qid_map[slot].qid = queue->id.phys_id;
-	port->qid_map[slot].priority = priority;
-
-	state = DLB2_QUEUE_MAP_IN_PROG;
-	ret = dlb2_port_slot_state_transition(hw, port, queue, slot, state);
-	if (ret)
-		return ret;
-
-	r0.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));
-
-	if (r0.field.count) {
-		/*
-		 * The queue is owed completions so it's not safe to map it
-		 * yet. Schedule a kernel thread to complete the mapping later,
-		 * once software has completed all the queue's inflight events.
-		 */
-		if (!os_worker_active(hw))
-			os_schedule_work(hw);
-
-		return 1;
-	}
-
-	/*
-	 * Disable the affected CQ, and the CQs already mapped to the QID,
-	 * before reading the QID's inflight count a second time. There is an
-	 * unlikely race in which the QID may schedule one more QE after we
-	 * read an inflight count of 0, and disabling the CQs guarantees that
-	 * the race will not occur after a re-read of the inflight count
-	 * register.
-	 */
-	if (port->enabled)
-		dlb2_ldb_port_cq_disable(hw, port);
-
-	dlb2_ldb_queue_disable_mapped_cqs(hw, domain, queue);
-
-	r0.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));
-
-	if (r0.field.count) {
-		if (port->enabled)
-			dlb2_ldb_port_cq_enable(hw, port);
-
-		dlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);
-
-		/*
-		 * The queue is owed completions so it's not safe to map it
-		 * yet. Schedule a kernel thread to complete the mapping later,
-		 * once software has completed all the queue's inflight events.
-		 */
-		if (!os_worker_active(hw))
-			os_schedule_work(hw);
-
-		return 1;
-	}
-
-	return dlb2_ldb_port_finish_map_qid_dynamic(hw, domain, port, queue);
-}
-
-static void dlb2_domain_finish_map_port(struct dlb2_hw *hw,
-					struct dlb2_hw_domain *domain,
-					struct dlb2_ldb_port *port)
-{
-	int i;
-
-	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
-		union dlb2_lsp_qid_ldb_infl_cnt r0;
-		struct dlb2_ldb_queue *queue;
-		int qid;
-
-		if (port->qid_map[i].state != DLB2_QUEUE_MAP_IN_PROG)
-			continue;
-
-		qid = port->qid_map[i].qid;
-
-		queue = dlb2_get_ldb_queue_from_id(hw, qid, false, 0);
-
-		if (queue == NULL) {
-			DLB2_HW_ERR(hw,
-				    "[%s()] Internal error: unable to find queue %d\n",
-				    __func__, qid);
-			continue;
-		}
-
-		r0.val = DLB2_CSR_RD(hw, DLB2_LSP_QID_LDB_INFL_CNT(qid));
-
-		if (r0.field.count)
-			continue;
-
-		/*
-		 * Disable the affected CQ, and the CQs already mapped to the
-		 * QID, before reading the QID's inflight count a second time.
-		 * There is an unlikely race in which the QID may schedule one
-		 * more QE after we read an inflight count of 0, and disabling
-		 * the CQs guarantees that the race will not occur after a
-		 * re-read of the inflight count register.
-		 */
-		if (port->enabled)
-			dlb2_ldb_port_cq_disable(hw, port);
-
-		dlb2_ldb_queue_disable_mapped_cqs(hw, domain, queue);
-
-		r0.val = DLB2_CSR_RD(hw, DLB2_LSP_QID_LDB_INFL_CNT(qid));
-
-		if (r0.field.count) {
-			if (port->enabled)
-				dlb2_ldb_port_cq_enable(hw, port);
-
-			dlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);
-
-			continue;
-		}
-
-		dlb2_ldb_port_finish_map_qid_dynamic(hw, domain, port, queue);
-	}
-}
-
-static unsigned int
-dlb2_domain_finish_map_qid_procedures(struct dlb2_hw *hw,
-				      struct dlb2_hw_domain *domain)
-{
-	struct dlb2_list_entry *iter;
-	struct dlb2_ldb_port *port;
-	int i;
-	RTE_SET_USED(iter);
-
-	if (!domain->configured || domain->num_pending_additions == 0)
-		return 0;
-
-	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)
-			dlb2_domain_finish_map_port(hw, domain, port);
-	}
-
-	return domain->num_pending_additions;
-}
-
-static int dlb2_ldb_port_unmap_qid(struct dlb2_hw *hw,
-				   struct dlb2_ldb_port *port,
-				   struct dlb2_ldb_queue *queue)
-{
-	enum dlb2_qid_map_state mapped, in_progress, pending_map, unmapped;
-	union dlb2_lsp_cq2priov r0;
-	union dlb2_atm_qid2cqidix_00 r1;
-	union dlb2_lsp_qid2cqidix_00 r2;
-	union dlb2_lsp_qid2cqidix2_00 r3;
-	u32 queue_id;
-	u32 port_id;
-	int i;
-
-	/* Find the queue's slot */
-	mapped = DLB2_QUEUE_MAPPED;
-	in_progress = DLB2_QUEUE_UNMAP_IN_PROG;
-	pending_map = DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP;
-
-	if (!dlb2_port_find_slot_queue(port, mapped, queue, &i) &&
-	    !dlb2_port_find_slot_queue(port, in_progress, queue, &i) &&
-	    !dlb2_port_find_slot_queue(port, pending_map, queue, &i)) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: QID %d isn't mapped\n",
-			    __func__, __LINE__, queue->id.phys_id);
-		return -EFAULT;
-	}
-
-	if (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {
-		DLB2_HW_ERR(hw,
-			    "[%s():%d] Internal error: port slot tracking failed\n",
-			    __func__, __LINE__);
-		return -EFAULT;
-	}
-
-	port_id = port->id.phys_id;
-	queue_id = queue->id.phys_id;
-
-	/* Read-modify-write the priority and valid bit register */
-	r0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(port_id));
-
-	r0.field.v &= ~(1 << i);
-
-	DLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port_id), r0.val);
-
-	r1.val = DLB2_CSR_RD(hw,
-			     DLB2_ATM_QID2CQIDIX(queue_id, port_id / 4));
-
-	r2.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID2CQIDIX(queue_id, port_id / 4));
-
-	r3.val = DLB2_CSR_RD(hw,
-			     DLB2_LSP_QID2CQIDIX2(queue_id, port_id / 4));
-
-	switch (port_id % 4) {
-	case 0:
-		r1.field.cq_p0 &= ~(1 << i);
-		r2.field.cq_p0 &= ~(1 << i);
-		r3.field.cq_p0 &= ~(1 << i);
-		break;
-
-	case 1:
-		r1.field.cq_p1 &= ~(1 << i);
-		r2.field.cq_p1 &= ~(1 << i);
-		r3.field.cq_p1 &= ~(1 << i);
-		break;
-
-	case 2:
-		r1.field.cq_p2 &= ~(1 << i);
-		r2.field.cq_p2 &= ~(1 << i);
-		r3.field.cq_p2 &= ~(1 << i);
-		break;
-
-	case 3:
-		r1.field.cq_p3 &= ~(1 << i);
-		r2.field.cq_p3 &= ~(1 << i);
-		r3.field.cq_p3 &= ~(1 << i);
-		break;
-	}
-
-	DLB2_CSR_WR(hw,
-		    DLB2_ATM_QID2CQIDIX(queue_id, port_id / 4),
-		    r1.val);
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID2CQIDIX(queue_id, port_id / 4),
-		    r2.val);
-
-	DLB2_CSR_WR(hw,
-		    DLB2_LSP_QID2CQIDIX2(queue_id, port_id / 4),
-		    r3.val);
-
-	dlb2_flush_csr(hw);
-
-	unmapped = DLB2_QUEUE_UNMAPPED;
-
-	return dlb2_port_slot_state_transition(hw, port, queue, i, unmapped);
-}
-
-static int dlb2_ldb_port_map_qid(struct dlb2_hw *hw,
-				 struct dlb2_hw_domain *domain,
-				 struct dlb2_ldb_port *port,
-				 struct dlb2_ldb_queue *queue,
-				 u8 prio)
-{
-	if (domain->started)
-		return dlb2_ldb_port_map_qid_dynamic(hw, port, queue, prio);
-	else
-		return dlb2_ldb_port_map_qid_static(hw, port, queue, prio);
-}
-
-static void
-dlb2_domain_finish_unmap_port_slot(struct dlb2_hw *hw,
-				   struct dlb2_hw_domain *domain,
-				   struct dlb2_ldb_port *port,
-				   int slot)
-{
-	enum dlb2_qid_map_state state;
-	struct dlb2_ldb_queue *queue;
-
-	queue = &hw->rsrcs.ldb_queues[port->qid_map[slot].qid];
-
-	state = port->qid_map[slot].state;
-
-	/* Update the QID2CQIDX and CQ2QID vectors */
-	dlb2_ldb_port_unmap_qid(hw, port, queue);
-
-	/*
-	 * Ensure the QID will not be serviced by this {CQ, slot} by clearing
-	 * the has_work bits
-	 */
-	dlb2_ldb_port_clear_has_work_bits(hw, port, slot);
-
-	/* Reset the {CQ, slot} to its default state */
-	dlb2_ldb_port_set_queue_if_status(hw, port, slot);
-
-	/* Re-enable the CQ if it wasn't manually disabled by the user */
-	if (port->enabled)
-		dlb2_ldb_port_cq_enable(hw, port);
-
-	/*
-	 * If there is a mapping that is pending this slot's removal, perform
-	 * the mapping now.
-	 */
-	if (state == DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP) {
-		struct dlb2_ldb_port_qid_map *map;
-		struct dlb2_ldb_queue *map_queue;
-		u8 prio;
-
-		map = &port->qid_map[slot];
-
-		map->qid = map->pending_qid;
-		map->priority = map->pending_priority;
-
-		map_queue = &hw->rsrcs.ldb_queues[map->qid];
-		prio = map->priority;
-
-		dlb2_ldb_port_map_qid(hw, domain, port, map_queue, prio);
-	}
-}
-
-static bool dlb2_domain_finish_unmap_port(struct dlb2_hw *hw,
-					  struct dlb2_hw_domain *domain,
-					  struct dlb2_ldb_port *port)
-{
-	union dlb2_lsp_cq_ldb_infl_cnt r0;
-	int i;
-
-	if (port->num_pending_removals == 0)
-		return false;
-
-	/*
-	 * The unmap requires all the CQ's outstanding inflights to be
-	 * completed.
-	 */
-	r0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ_LDB_INFL_CNT(port->id.phys_id));
-	if (r0.field.count > 0)
-		return false;
-
-	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
-		struct dlb2_ldb_port_qid_map *map;
-
-		map = &port->qid_map[i];
-
-		if (map->state != DLB2_QUEUE_UNMAP_IN_PROG &&
-		    map->state != DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP)
-			continue;
-
-		dlb2_domain_finish_unmap_port_slot(hw, domain, port, i);
-	}
-
-	return true;
-}
-
-static unsigned int
-dlb2_domain_finish_unmap_qid_procedures(struct dlb2_hw *hw,
-					struct dlb2_hw_domain *domain)
-{
-	struct dlb2_list_entry *iter;
-	struct dlb2_ldb_port *port;
-	int i;
-	RTE_SET_USED(iter);
-
-	if (!domain->configured || domain->num_pending_removals == 0)
-		return 0;
-
-	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
-		DLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)
-			dlb2_domain_finish_unmap_port(hw, domain, port);
-	}
-
-	return domain->num_pending_removals;
-}
-
-unsigned int dlb2_finish_unmap_qid_procedures(struct dlb2_hw *hw)
-{
-	int i, num = 0;
-
-	/* Finish queue unmap jobs for any domain that needs it */
-	for (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {
-		struct dlb2_hw_domain *domain = &hw->domains[i];
-
-		num += dlb2_domain_finish_unmap_qid_procedures(hw, domain);
-	}
-
-	return num;
-}
-
-unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)
-{
-	int i, num = 0;
-
-	/* Finish queue map jobs for any domain that needs it */
-	for (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {
-		struct dlb2_hw_domain *domain = &hw->domains[i];
-
-		num += dlb2_domain_finish_map_qid_procedures(hw, domain);
-	}
-
-	return num;
-}
-
 int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)
 {
 	if (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)
drivers/event/dlb2/pf/base/dlb2_resource_new.c +50 -0

53 lines not on this page · raw message

Signature · 1 line
2.23.0
#163 lore raw

PATCH 16/25 event/dlb2: add DLB v2.5 sparse cq mode

In reply to Timothy McDaniel

Update sparse cq mode mode functions for DLB v2.5, accounting for new combined register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    | 22 -----------
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 39 +++++++++++++++++++
 2 files changed, 39 insertions(+), 22 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -22
index d66442c19..1759cee6b 100644
@@ -33,28 +33,6 @@
 #define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \
 	DLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)
 
-void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)
-{
-	union dlb2_chp_cfg_chp_csr_ctrl r0;
-
-	r0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);
-
-	r0.field.cfg_64bytes_qe_dir_cq_mode = 1;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);
-}
-
-void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)
-{
-	union dlb2_chp_cfg_chp_csr_ctrl r0;
-
-	r0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);
-
-	r0.field.cfg_64bytes_qe_ldb_cq_mode = 1;
-
-	DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);
-}
-
 /*
  * The PF driver cannot assume that a register write will affect subsequent HCW
  * writes. To ensure a write completes, the driver must read back a CSR. This
drivers/event/dlb2/pf/base/dlb2_resource_new.c +39 -0
index 7c71fa791..f147937c0 100644
@@ -6090,3 +6090,42 @@ unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)
 
 	return num;
 }
+
+/**
+ * dlb2_hw_enable_sparse_dir_cq_mode() - enable sparse mode for directed ports.
+ * @hw: dlb2_hw handle for a particular device.
+ *
+ * This function must be called prior to configuring scheduling domains.
+ */
+
+void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)
+{
+	u32 ctrl;
+
+	ctrl = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);
+
+	DLB2_BIT_SET(ctrl,
+		     DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE);
+
+	DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);
+}
+
+/**
+ * dlb2_hw_enable_sparse_ldb_cq_mode() - enable sparse mode for load-balanced
+ *	ports.
+ * @hw: dlb2_hw handle for a particular device.
+ *
+ * This function must be called prior to configuring scheduling domains.
+ */
+void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)
+{
+	u32 ctrl;
+
+	ctrl = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);
+
+	DLB2_BIT_SET(ctrl,
+		     DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE);
+
+	DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);
+}
+
Signature · 1 line
2.23.0
#164 lore raw

PATCH 17/25 event/dlb2: add DLB v2.5 support to sequence number management

In reply to Timothy McDaniel

Update sequence number management functions for DLB v2.5, accounting for new combined register map and hardware access macros.

---
 drivers/event/dlb2/pf/base/dlb2_resource.c    |   1 +
 drivers/event/dlb2/pf/base/dlb2_resource.h    |   4 +-
 .../event/dlb2/pf/base/dlb2_resource_new.c    | 105 ++++++++++++++++++
 3 files changed, 108 insertions(+), 2 deletions(-)
drivers/event/dlb2/pf/base/dlb2_resource.c +1 -0
index 1759cee6b..bd1404f33 100644
@@ -242,3 +242,4 @@ int dlb2_hw_get_ldb_queue_depth(struct dlb2_hw *hw,
 
 	return 0;
 }
+
drivers/event/dlb2/pf/base/dlb2_resource.h +2 -2
index 2e13193bb..00a0b6b57 100644
@@ -792,8 +792,8 @@ int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw,
  * ordered queue is configured.
  */
 int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,
-				    unsigned int group_id,
-				    unsigned long val);
+				    u32 group_id,
+				    u32 val);
 
 /**
  * dlb2_reset_domain() - reset a scheduling domain
drivers/event/dlb2/pf/base/dlb2_resource_new.c +105 -0

108 lines not on this page · raw message

Signature · 1 line
2.23.0
#165 lore raw

PATCH 18/25 event/dlb2: consolidate dlb resource header files into one file

In reply to Timothy McDaniel

A temporary version of dlb_resource.h (dlb_resource_new.h) was used by the previous commits in this patch series. Merge the two files now that DLB v2.5 support has been fully added to dlb_resource.c.

---
 drivers/event/dlb2/pf/base/dlb2_osdep.h       |  1 -
 drivers/event/dlb2/pf/base/dlb2_resource.h    | 36 +++++++++
 .../event/dlb2/pf/base/dlb2_resource_new.c    |  2 +-
 .../event/dlb2/pf/base/dlb2_resource_new.h    | 73 -------------------
 drivers/event/dlb2/pf/dlb2_main.c             |  2 +-
 drivers/event/dlb2/pf/dlb2_pf.c               |  2 +-
 6 files changed, 39 insertions(+), 77 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.h
drivers/event/dlb2/pf/base/dlb2_osdep.h +0 -1
index 747f680b9..1bdb201f2 100644
@@ -18,7 +18,6 @@
 #include "../dlb2_main.h"
 
 /* TEMPORARY inclusion of both headers for merge */
-#include "dlb2_resource_new.h"
 #include "dlb2_resource.h"
 
 #include "../../dlb2_log.h"
drivers/event/dlb2/pf/base/dlb2_resource.h +36 -0
index 00a0b6b57..684049cd6 100644
@@ -8,6 +8,42 @@
 #include "dlb2_user.h"
 #include "dlb2_osdep_types.h"
 
+/**
+ * dlb2_resource_init() - initialize the device
+ * @hw: pointer to struct dlb2_hw.
+ * @ver: device version.
+ *
+ * This function initializes the device's software state (pointed to by the hw
+ * argument) and programs global scheduling QoS registers. This function should
+ * be called during driver initialization.
+ *
+ * The dlb2_hw struct must be unique per DLB 2.0 device and persist until the
+ * device is reset.
+ *
+ * Return:
+ * Returns 0 upon success, <0 otherwise.
+ */
+int dlb2_resource_init(struct dlb2_hw *hw, enum dlb2_hw_ver ver);
+
+/**
+ * dlb2_clr_pmcsr_disable() - power on bulk of DLB 2.0 logic
+ * @hw: dlb2_hw handle for a particular device.
+ * @ver: device version.
+ *
+ * Clearing the PMCSR must be done at initialization to make the device fully
+ * operational.
+ */
+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw, enum dlb2_hw_ver ver);
+
+/**
+ * dlb2_resource_free() - free device state memory
+ * @hw: dlb2_hw handle for a particular device.
+ *
+ * This function frees software state pointed to by dlb2_hw. This function
+ * should be called when resetting the device or unloading the driver.
+ */
+void dlb2_resource_free(struct dlb2_hw *hw);
+
 /**
  * dlb2_resource_reset() - reset in-use resources to their initial state
  * @hw: dlb2_hw handle for a particular device.
drivers/event/dlb2/pf/base/dlb2_resource_new.c +1 -1
index 9e4e49583..8d6c00f31 100644
@@ -12,7 +12,7 @@
 #include "dlb2_osdep_bitmap.h"
 #include "dlb2_osdep_types.h"
 #include "dlb2_regs_new.h"
-#include "dlb2_resource_new.h" /* TEMP FOR UPSTREAMPATCHES */
+#include "dlb2_resource.h"
 
 #include "../../dlb2_priv.h"
 #include "../../dlb2_inline_fns.h"
drivers/event/dlb2/pf/base/dlb2_resource_new.h deleted +0 -73

73 lines not on this page · raw message

drivers/event/dlb2/pf/dlb2_main.c +1 -1
index 5c0640b3c..bac07f097 100644
@@ -17,7 +17,7 @@
 
 #include "base/dlb2_regs_new.h"
 #include "base/dlb2_hw_types_new.h"
-#include "base/dlb2_resource_new.h"
+#include "base/dlb2_resource.h"
 #include "base/dlb2_osdep.h"
 #include "dlb2_main.h"
 #include "../dlb2_user.h"
drivers/event/dlb2/pf/dlb2_pf.c +1 -1
index 9b40e5eb3..4214ed85a 100644
@@ -39,7 +39,7 @@
 #include "dlb2_main.h"
 #include "base/dlb2_hw_types_new.h"
 #include "base/dlb2_osdep.h"
-#include "base/dlb2_resource_new.h"
+#include "base/dlb2_resource.h"
 
 static const char *event_dlb2_pf_name = RTE_STR(EVDEV_DLB2_NAME_PMD);
 
Signature · 1 line
2.23.0
#166 lore raw

PATCH 19/25 event/dlb2: delete old dlb2_resource.c file

In reply to Timothy McDaniel

The file dlb_resource_new.c now contains all of the low level functions required to support both DLB v2.0 and DLB v2.5, so delete the temporary "old" file, and stop building it. The new file (dlb_resource_new.c) will be renamed to dlb_resource.c in the next commit.

---
 drivers/event/dlb2/meson.build             |   1 -
 drivers/event/dlb2/pf/base/dlb2_resource.c | 245 ---------------------
 2 files changed, 246 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.c
drivers/event/dlb2/meson.build +0 -1
index bded07e06..d8cfd377f 100644
@@ -13,7 +13,6 @@ sources = files('dlb2.c',
 		'dlb2_xstats.c',
 		'pf/dlb2_main.c',
 		'pf/dlb2_pf.c',
-		'pf/base/dlb2_resource.c',
 		'pf/base/dlb2_resource_new.c',
 		'rte_pmd_dlb2.c',
 		'dlb2_selftest.c'
drivers/event/dlb2/pf/base/dlb2_resource.c deleted +0 -245

245 lines not on this page · raw message

Signature · 1 line
2.23.0
#167 lore raw

PATCH 20/25 event/dlb2: move dlb_resource_new.c to dlb_resource.c

In reply to Timothy McDaniel

The file dlb_resource_new.c now contains all of the low level functions required to support both DLB v2.0 and DLB v2.5, and the original file (dlb_resource.c) was removed in the previous commit, so rename dlb_resource_new.c to dlb_resource.c, and update the meson build file so that the new file is built.

---
 drivers/event/dlb2/meson.build                                  | 2 +-
 .../event/dlb2/pf/base/{dlb2_resource_new.c => dlb2_resource.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename drivers/event/dlb2/pf/base/{dlb2_resource_new.c => dlb2_resource.c} (100%)
drivers/event/dlb2/meson.build +1 -1
index d8cfd377f..f22638b8e 100644
@@ -13,7 +13,7 @@ sources = files('dlb2.c',
 		'dlb2_xstats.c',
 		'pf/dlb2_main.c',
 		'pf/dlb2_pf.c',
-		'pf/base/dlb2_resource_new.c',
+		'pf/base/dlb2_resource.c',
 		'rte_pmd_dlb2.c',
 		'dlb2_selftest.c'
 )
drivers/event/dlb2/pf/base/dlb2_resource.c renamed from drivers/event/dlb2/pf/base/dlb2_resource_new.c +0 -0
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_resource_new.c
rename to drivers/event/dlb2/pf/base/dlb2_resource.c
Signature · 1 line
2.23.0
#168 lore raw

PATCH 21/25 event/dlb2: remove temporary file, dlb_hw_types.h

In reply to Timothy McDaniel

As support for DLB v2.5 was added, modifications were made to dlb_hw_types_new.h, but the old file needed to be preserved during the port in order to meet the requirement that individual patches in a series each compile successfully. Since the DLB v2.5 support is completely integrated, it is now safe to remove the old (original) file, as well as the DLB2_USE_NEW_HEADERS define that was used to control which version of the file was to be included in certain source files. The next commit will rename dlb2_hw_type_new.h to dlb_hw_types.h.

---
 drivers/event/dlb2/pf/base/dlb2_hw_types.h | 341 ---------------------
 drivers/event/dlb2/pf/base/dlb2_resource.c |   2 -
 drivers/event/dlb2/pf/dlb2_main.c          |   2 -
 drivers/event/dlb2/pf/dlb2_main.h          |   4 -
 drivers/event/dlb2/pf/dlb2_pf.c            |   2 -
 5 files changed, 351 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types.h
drivers/event/dlb2/pf/base/dlb2_hw_types.h deleted +0 -341
deleted file mode 100644
index 11e518982..000000000
@@ -1,341 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2016-2020 Intel Corporation
- */
-
-#ifndef __DLB2_HW_TYPES_H
-#define __DLB2_HW_TYPES_H
-
-#include "../../dlb2_priv.h"
-#include "dlb2_user.h"
-
-#include "dlb2_osdep_list.h"
-#include "dlb2_osdep_types.h"
-
-#define DLB2_MAX_NUM_VDEVS			16
-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS	2
-#define DLB2_NUM_ARB_WEIGHTS			8
-#define DLB2_MAX_NUM_AQED_ENTRIES		2048
-#define DLB2_MAX_WEIGHT				255
-#define DLB2_NUM_COS_DOMAINS			4
-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS	2
-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES	5
-#define DLB2_MAX_CQ_COMP_CHECK_LOOPS		409600
-#define DLB2_MAX_QID_EMPTY_CHECK_LOOPS		(32 * 64 * 1024 * (800 / 30))
-
-#define DLB2_FUNC_BAR				0
-#define DLB2_CSR_BAR				2
-
-#ifdef FPGA
-#define DLB2_HZ					2000000
-#else
-#define DLB2_HZ					800000000
-#endif
-
-#define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710
-#define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711
-
-#define PCI_DEVICE_ID_INTEL_DLB2_5_PF 0x2714
-#define PCI_DEVICE_ID_INTEL_DLB2_5_VF 0x2715
-
-#define DLB2_ALARM_HW_SOURCE_SYS 0
-#define DLB2_ALARM_HW_SOURCE_DLB 1
-
-#define DLB2_ALARM_HW_UNIT_CHP 4
-
-#define DLB2_ALARM_SYS_AID_ILLEGAL_QID		3
-#define DLB2_ALARM_SYS_AID_DISABLED_QID		4
-#define DLB2_ALARM_SYS_AID_ILLEGAL_HCW		5
-#define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ	1
-#define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2
-
-/*
- * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by
- * the PF driver.
- */
-#define DLB2_DRV_LDB_PP_BASE   0x2300000
-#define DLB2_DRV_LDB_PP_STRIDE 0x1000
-#define DLB2_DRV_LDB_PP_BOUND  (DLB2_DRV_LDB_PP_BASE + \
-				DLB2_DRV_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)
-#define DLB2_DRV_DIR_PP_BASE   0x2200000
-#define DLB2_DRV_DIR_PP_STRIDE 0x1000
-#define DLB2_DRV_DIR_PP_BOUND  (DLB2_DRV_DIR_PP_BASE + \
-				DLB2_DRV_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)
-#define DLB2_LDB_PP_BASE       0x2100000
-#define DLB2_LDB_PP_STRIDE     0x1000
-#define DLB2_LDB_PP_BOUND      (DLB2_LDB_PP_BASE + \
-				DLB2_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)
-#define DLB2_LDB_PP_OFFS(id)   (DLB2_LDB_PP_BASE + (id) * DLB2_PP_SIZE)
-#define DLB2_DIR_PP_BASE       0x2000000
-#define DLB2_DIR_PP_STRIDE     0x1000
-#define DLB2_DIR_PP_BOUND      (DLB2_DIR_PP_BASE + \
-				DLB2_DIR_PP_STRIDE * \
-				DLB2_MAX_NUM_DIR_PORTS_V2_5)
-#define DLB2_DIR_PP_OFFS(id)   (DLB2_DIR_PP_BASE + (id) * DLB2_PP_SIZE)
-
-struct dlb2_resource_id {
-	u32 phys_id;
-	u32 virt_id;
-	u8 vdev_owned;
-	u8 vdev_id;
-};
-
-struct dlb2_freelist {
-	u32 base;
-	u32 bound;
-	u32 offset;
-};
-
-static inline u32 dlb2_freelist_count(struct dlb2_freelist *list)
-{
-	return list->bound - list->base - list->offset;
-}
-
-struct dlb2_hcw {
-	u64 data;
-	/* Word 3 */
-	u16 opaque;
-	u8 qid;
-	u8 sched_type:2;
-	u8 priority:3;
-	u8 msg_type:3;
-	/* Word 4 */
-	u16 lock_id;
-	u8 ts_flag:1;
-	u8 rsvd1:2;
-	u8 no_dec:1;
-	u8 cmp_id:4;
-	u8 cq_token:1;
-	u8 qe_comp:1;
-	u8 qe_frag:1;
-	u8 qe_valid:1;
-	u8 int_arm:1;
-	u8 error:1;
-	u8 rsvd:2;
-};
-
-struct dlb2_ldb_queue {
-	struct dlb2_list_entry domain_list;
-	struct dlb2_list_entry func_list;
-	struct dlb2_resource_id id;
-	struct dlb2_resource_id domain_id;
-	u32 num_qid_inflights;
-	u32 aqed_limit;
-	u32 sn_group; /* sn == sequence number */
-	u32 sn_slot;
-	u32 num_mappings;
-	u8 sn_cfg_valid;
-	u8 num_pending_additions;
-	u8 owned;
-	u8 configured;
-};
-
-/*
- * Directed ports and queues are paired by nature, so the driver tracks them
- * with a single data structure.
- */
-struct dlb2_dir_pq_pair {
-	struct dlb2_list_entry domain_list;
-	struct dlb2_list_entry func_list;
-	struct dlb2_resource_id id;
-	struct dlb2_resource_id domain_id;
-	u32 ref_cnt;
-	u8 init_tkn_cnt;
-	u8 queue_configured;
-	u8 port_configured;
-	u8 owned;
-	u8 enabled;
-};
-
-enum dlb2_qid_map_state {
-	/* The slot doesn't contain a valid queue mapping */
-	DLB2_QUEUE_UNMAPPED,
-	/* The slot contains a valid queue mapping */
-	DLB2_QUEUE_MAPPED,
-	/* The driver is mapping a queue into this slot */
-	DLB2_QUEUE_MAP_IN_PROG,
-	/* The driver is unmapping a queue from this slot */
-	DLB2_QUEUE_UNMAP_IN_PROG,
-	/*
-	 * The driver is unmapping a queue from this slot, and once complete
-	 * will replace it with another mapping.
-	 */
-	DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP,
-};
-
-struct dlb2_ldb_port_qid_map {
-	enum dlb2_qid_map_state state;
-	u16 qid;
-	u16 pending_qid;
-	u8 priority;
-	u8 pending_priority;
-};
-
-struct dlb2_ldb_port {
-	struct dlb2_list_entry domain_list;
-	struct dlb2_list_entry func_list;
-	struct dlb2_resource_id id;
-	struct dlb2_resource_id domain_id;
-	/* The qid_map represents the hardware QID mapping state. */
-	struct dlb2_ldb_port_qid_map qid_map[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];
-	u32 hist_list_entry_base;
-	u32 hist_list_entry_limit;
-	u32 ref_cnt;
-	u8 init_tkn_cnt;
-	u8 num_pending_removals;
-	u8 num_mappings;
-	u8 owned;
-	u8 enabled;
-	u8 configured;
-};
-
-struct dlb2_sn_group {
-	u32 mode;
-	u32 sequence_numbers_per_queue;
-	u32 slot_use_bitmap;
-	u32 id;
-};
-
-static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)
-{
-	const u32 mask[] = {
-		0x0000ffff,  /* 64 SNs per queue */
-		0x000000ff,  /* 128 SNs per queue */
-		0x0000000f,  /* 256 SNs per queue */
-		0x00000003,  /* 512 SNs per queue */
-		0x00000001}; /* 1024 SNs per queue */
-
-	return group->slot_use_bitmap == mask[group->mode];
-}
-
-static inline int dlb2_sn_group_alloc_slot(struct dlb2_sn_group *group)
-{
-	const u32 bound[] = {16, 8, 4, 2, 1};
-	u32 i;
-
-	for (i = 0; i < bound[group->mode]; i++) {
-		if (!(group->slot_use_bitmap & (1 << i))) {
-			group->slot_use_bitmap |= 1 << i;
-			return i;
-		}
-	}
-
-	return -1;
-}
-
-static inline void
-dlb2_sn_group_free_slot(struct dlb2_sn_group *group, int slot)
-{
-	group->slot_use_bitmap &= ~(1 << slot);
-}
-
-static inline int dlb2_sn_group_used_slots(struct dlb2_sn_group *group)
-{
-	int i, cnt = 0;
-
-	for (i = 0; i < 32; i++)
-		cnt += !!(group->slot_use_bitmap & (1 << i));
-
-	return cnt;
-}
-
-struct dlb2_hw_domain {
-	struct dlb2_function_resources *parent_func;
-	struct dlb2_list_entry func_list;
-	struct dlb2_list_head used_ldb_queues;
-	struct dlb2_list_head used_ldb_ports[DLB2_NUM_COS_DOMAINS];
-	struct dlb2_list_head used_dir_pq_pairs;
-	struct dlb2_list_head avail_ldb_queues;
-	struct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
-	struct dlb2_list_head avail_dir_pq_pairs;
-	u32 total_hist_list_entries;
-	u32 avail_hist_list_entries;
-	u32 hist_list_entry_base;
-	u32 hist_list_entry_offset;
-	u32 num_ldb_credits;
-	u32 num_dir_credits;
-	u32 num_avail_aqed_entries;
-	u32 num_used_aqed_entries;
-	struct dlb2_resource_id id;
-	int num_pending_removals;
-	int num_pending_additions;
-	u8 configured;
-	u8 started;
-};
-
-struct dlb2_bitmap;
-
-struct dlb2_function_resources {
-	struct dlb2_list_head avail_domains;
-	struct dlb2_list_head used_domains;
-	struct dlb2_list_head avail_ldb_queues;
-	struct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
-	struct dlb2_list_head avail_dir_pq_pairs;
-	struct dlb2_bitmap *avail_hist_list_entries;
-	u32 num_avail_domains;
-	u32 num_avail_ldb_queues;
-	u32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
-	u32 num_avail_dir_pq_pairs;
-	u32 num_avail_qed_entries;
-	u32 num_avail_dqed_entries;
-	u32 num_avail_aqed_entries;
-	u8 locked; /* (VDEV only) */
-};
-
-/*
- * After initialization, each resource in dlb2_hw_resources is located in one
- * of the following lists:
- * -- The PF's available resources list. These are unconfigured resources owned
- *	by the PF and not allocated to a dlb2 scheduling domain.
- * -- A VDEV's available resources list. These are VDEV-owned unconfigured
- *	resources not allocated to a dlb2 scheduling domain.
- * -- A domain's available resources list. These are domain-owned unconfigured
- *	resources.
- * -- A domain's used resources list. These are domain-owned configured
- *	resources.
- *
- * A resource moves to a new list when a VDEV or domain is created or destroyed,
- * or when the resource is configured.
- */
-struct dlb2_hw_resources {
-	struct dlb2_ldb_queue ldb_queues[DLB2_MAX_NUM_LDB_QUEUES];
-	struct dlb2_ldb_port ldb_ports[DLB2_MAX_NUM_LDB_PORTS];
-	struct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS_V2_5];
-	struct dlb2_sn_group sn_groups[DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS];
-};
-
-struct dlb2_mbox {
-	u32 *mbox;
-	u32 *isr_in_progress;
-};
-
-struct dlb2_sw_mbox {
-	struct dlb2_mbox vdev_to_pf;
-	struct dlb2_mbox pf_to_vdev;
-	void (*pf_to_vdev_inject)(void *arg);
-	void *pf_to_vdev_inject_arg;
-};
-
-struct dlb2_hw {
-	uint8_t ver;
-
-	/* BAR 0 address */
-	void *csr_kva;
-	unsigned long csr_phys_addr;
-	/* BAR 2 address */
-	void *func_kva;
-	unsigned long func_phys_addr;
-
-	/* Resource tracking */
-	struct dlb2_hw_resources rsrcs;
-	struct dlb2_function_resources pf;
-	struct dlb2_function_resources vdev[DLB2_MAX_NUM_VDEVS];
-	struct dlb2_hw_domain domains[DLB2_MAX_NUM_DOMAINS];
-	u8 cos_reservation[DLB2_NUM_COS_DOMAINS];
-
-	/* Virtualization */
-	int virt_mode;
-	struct dlb2_sw_mbox mbox[DLB2_MAX_NUM_VDEVS];
-	unsigned int pasid[DLB2_MAX_NUM_VDEVS];
-};
-
-#endif /* __DLB2_HW_TYPES_H */
drivers/event/dlb2/pf/base/dlb2_resource.c +0 -2
index 8d6c00f31..4b3d1202c 100644
@@ -2,8 +2,6 @@
  * Copyright(c) 2016-2020 Intel Corporation
  */
 
-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
-
 #include "dlb2_user.h"
 
 #include "dlb2_hw_types_new.h"
drivers/event/dlb2/pf/dlb2_main.c +0 -2
index bac07f097..3ab0c3ef5 100644
@@ -13,8 +13,6 @@
 #include <rte_malloc.h>
 #include <rte_errno.h>
 
-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
-
 #include "base/dlb2_regs_new.h"
 #include "base/dlb2_hw_types_new.h"
 #include "base/dlb2_resource.h"
drivers/event/dlb2/pf/dlb2_main.h +0 -4
index 01a24e8a4..2dfca58e3 100644
@@ -15,11 +15,7 @@
 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
 #endif
 
-#ifdef DLB2_USE_NEW_HEADERS
 #include "base/dlb2_hw_types_new.h"
-#else
-#include "base/dlb2_hw_types.h"
-#endif
 #include "../dlb2_user.h"
 
 #define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5
drivers/event/dlb2/pf/dlb2_pf.c +0 -2
index 4214ed85a..c4c776e83 100644
@@ -31,8 +31,6 @@
 #include <rte_memory.h>
 #include <rte_string_fns.h>
 
-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
-
 #include "../dlb2_priv.h"
 #include "../dlb2_iface.h"
 #include "../dlb2_inline_fns.h"
Signature · 1 line
2.23.0
#169 lore raw

PATCH 22/25 event/dlb2: move dlb2_hw_type_new.h to dlb2_hw_types.h

In reply to Timothy McDaniel

The original and a "new" file were maintained during the early portions of the patch series in order to ensure that all individual patches compiled cleanly. It is now safe to rename the new file, and use it unconditionally in all DLB source files.

---
 .../event/dlb2/pf/base/{dlb2_hw_types_new.h => dlb2_hw_types.h} | 0
 drivers/event/dlb2/pf/base/dlb2_resource.c                      | 2 +-
 drivers/event/dlb2/pf/dlb2_main.c                               | 2 +-
 drivers/event/dlb2/pf/dlb2_main.h                               | 2 +-
 drivers/event/dlb2/pf/dlb2_pf.c                                 | 2 +-
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename drivers/event/dlb2/pf/base/{dlb2_hw_types_new.h => dlb2_hw_types.h} (100%)
drivers/event/dlb2/pf/base/dlb2_hw_types.h renamed from drivers/event/dlb2/pf/base/dlb2_hw_types_new.h +0 -0
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_hw_types_new.h
rename to drivers/event/dlb2/pf/base/dlb2_hw_types.h
drivers/event/dlb2/pf/base/dlb2_resource.c +1 -1
index 4b3d1202c..e5fa0f047 100644
@@ -4,7 +4,7 @@
 
 #include "dlb2_user.h"
 
-#include "dlb2_hw_types_new.h"
+#include "dlb2_hw_types.h"
 #include "dlb2_mbox.h"
 #include "dlb2_osdep.h"
 #include "dlb2_osdep_bitmap.h"
drivers/event/dlb2/pf/dlb2_main.c +1 -1
index 3ab0c3ef5..1f6ccf8e4 100644
@@ -14,7 +14,7 @@
 #include <rte_errno.h>
 
 #include "base/dlb2_regs_new.h"
-#include "base/dlb2_hw_types_new.h"
+#include "base/dlb2_hw_types.h"
 #include "base/dlb2_resource.h"
 #include "base/dlb2_osdep.h"
 #include "dlb2_main.h"
drivers/event/dlb2/pf/dlb2_main.h +1 -1
index 2dfca58e3..f3bee71fb 100644
@@ -15,7 +15,7 @@
 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
 #endif
 
-#include "base/dlb2_hw_types_new.h"
+#include "base/dlb2_hw_types.h"
 #include "../dlb2_user.h"
 
 #define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5
drivers/event/dlb2/pf/dlb2_pf.c +1 -1
index c4c776e83..a937d0f9c 100644
@@ -35,7 +35,7 @@
 #include "../dlb2_iface.h"
 #include "../dlb2_inline_fns.h"
 #include "dlb2_main.h"
-#include "base/dlb2_hw_types_new.h"
+#include "base/dlb2_hw_types.h"
 #include "base/dlb2_osdep.h"
 #include "base/dlb2_resource.h"
 
Signature · 1 line
2.23.0
#170 lore raw

PATCH 23/25 event/dlb2: delete old register map file, dlb2_regs.h

In reply to Timothy McDaniel

All dependencies on the old register map have been removed, so it can now be deleted. The next commit will rename dlb2_regs_new.h to dlb2_regs.h.

---
 drivers/event/dlb2/pf/base/dlb2_regs.h | 2527 ------------------------
 1 file changed, 2527 deletions(-)
 delete mode 100644 drivers/event/dlb2/pf/base/dlb2_regs.h
drivers/event/dlb2/pf/base/dlb2_regs.h deleted +0 -2527
deleted file mode 100644
index 43ecad4f8..000000000
@@ -1,2527 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2016-2020 Intel Corporation
- */
-
-#ifndef __DLB2_REGS_H
-#define __DLB2_REGS_H
-
-#include "dlb2_osdep_types.h"
-
-#define DLB2_FUNC_PF_VF2PF_MAILBOX_BYTES 256
-#define DLB2_FUNC_PF_VF2PF_MAILBOX(vf_id, x) \
-	(0x1000 + 0x4 * (x) + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_VF2PF_MAILBOX_RST 0x0
-union dlb2_func_pf_vf2pf_mailbox {
-	struct {
-		u32 msg : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR(vf_id) \
-	(0x1f00 + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR_RST 0x0
-union dlb2_func_pf_vf2pf_mailbox_isr {
-	struct {
-		u32 vf0_isr : 1;
-		u32 vf1_isr : 1;
-		u32 vf2_isr : 1;
-		u32 vf3_isr : 1;
-		u32 vf4_isr : 1;
-		u32 vf5_isr : 1;
-		u32 vf6_isr : 1;
-		u32 vf7_isr : 1;
-		u32 vf8_isr : 1;
-		u32 vf9_isr : 1;
-		u32 vf10_isr : 1;
-		u32 vf11_isr : 1;
-		u32 vf12_isr : 1;
-		u32 vf13_isr : 1;
-		u32 vf14_isr : 1;
-		u32 vf15_isr : 1;
-		u32 rsvd0 : 16;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_PF_VF2PF_FLR_ISR(vf_id) \
-	(0x1f04 + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_VF2PF_FLR_ISR_RST 0x0
-union dlb2_func_pf_vf2pf_flr_isr {
-	struct {
-		u32 vf0_isr : 1;
-		u32 vf1_isr : 1;
-		u32 vf2_isr : 1;
-		u32 vf3_isr : 1;
-		u32 vf4_isr : 1;
-		u32 vf5_isr : 1;
-		u32 vf6_isr : 1;
-		u32 vf7_isr : 1;
-		u32 vf8_isr : 1;
-		u32 vf9_isr : 1;
-		u32 vf10_isr : 1;
-		u32 vf11_isr : 1;
-		u32 vf12_isr : 1;
-		u32 vf13_isr : 1;
-		u32 vf14_isr : 1;
-		u32 vf15_isr : 1;
-		u32 rsvd0 : 16;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_PF_VF2PF_ISR_PEND(vf_id) \
-	(0x1f10 + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_VF2PF_ISR_PEND_RST 0x0
-union dlb2_func_pf_vf2pf_isr_pend {
-	struct {
-		u32 isr_pend : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_PF_PF2VF_MAILBOX_BYTES 64
-#define DLB2_FUNC_PF_PF2VF_MAILBOX(vf_id, x) \
-	(0x2000 + 0x4 * (x) + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_PF2VF_MAILBOX_RST 0x0
-union dlb2_func_pf_pf2vf_mailbox {
-	struct {
-		u32 msg : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR(vf_id) \
-	(0x2f00 + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR_RST 0x0
-union dlb2_func_pf_pf2vf_mailbox_isr {
-	struct {
-		u32 vf0_isr : 1;
-		u32 vf1_isr : 1;
-		u32 vf2_isr : 1;
-		u32 vf3_isr : 1;
-		u32 vf4_isr : 1;
-		u32 vf5_isr : 1;
-		u32 vf6_isr : 1;
-		u32 vf7_isr : 1;
-		u32 vf8_isr : 1;
-		u32 vf9_isr : 1;
-		u32 vf10_isr : 1;
-		u32 vf11_isr : 1;
-		u32 vf12_isr : 1;
-		u32 vf13_isr : 1;
-		u32 vf14_isr : 1;
-		u32 vf15_isr : 1;
-		u32 rsvd0 : 16;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS(vf_id) \
-	(0x3000 + (vf_id) * 0x10000)
-#define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS_RST 0xffff
-union dlb2_func_pf_vf_reset_in_progress {
-	struct {
-		u32 vf0_reset_in_progress : 1;
-		u32 vf1_reset_in_progress : 1;
-		u32 vf2_reset_in_progress : 1;
-		u32 vf3_reset_in_progress : 1;
-		u32 vf4_reset_in_progress : 1;
-		u32 vf5_reset_in_progress : 1;
-		u32 vf6_reset_in_progress : 1;
-		u32 vf7_reset_in_progress : 1;
-		u32 vf8_reset_in_progress : 1;
-		u32 vf9_reset_in_progress : 1;
-		u32 vf10_reset_in_progress : 1;
-		u32 vf11_reset_in_progress : 1;
-		u32 vf12_reset_in_progress : 1;
-		u32 vf13_reset_in_progress : 1;
-		u32 vf14_reset_in_progress : 1;
-		u32 vf15_reset_in_progress : 1;
-		u32 rsvd0 : 16;
-	} field;
-	u32 val;
-};
-
-#define DLB2_MSIX_MEM_VECTOR_CTRL(x) \
-	(0x100000c + (x) * 0x10)
-#define DLB2_MSIX_MEM_VECTOR_CTRL_RST 0x1
-union dlb2_msix_mem_vector_ctrl {
-	struct {
-		u32 vec_mask : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_IOSF_FUNC_VF_BAR_DSBL(x) \
-	(0x20 + (x) * 0x4)
-#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RST 0x0
-union dlb2_iosf_func_vf_bar_dsbl {
-	struct {
-		u32 func_vf_bar_dis : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_VAS 0x1000011c
-#define DLB2_SYS_TOTAL_VAS_RST 0x20
-union dlb2_sys_total_vas {
-	struct {
-		u32 total_vas : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_DIR_PORTS 0x10000118
-#define DLB2_SYS_TOTAL_DIR_PORTS_RST 0x40
-union dlb2_sys_total_dir_ports {
-	struct {
-		u32 total_dir_ports : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_LDB_PORTS 0x10000114
-#define DLB2_SYS_TOTAL_LDB_PORTS_RST 0x40
-union dlb2_sys_total_ldb_ports {
-	struct {
-		u32 total_ldb_ports : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_DIR_QID 0x10000110
-#define DLB2_SYS_TOTAL_DIR_QID_RST 0x40
-union dlb2_sys_total_dir_qid {
-	struct {
-		u32 total_dir_qid : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_LDB_QID 0x1000010c
-#define DLB2_SYS_TOTAL_LDB_QID_RST 0x20
-union dlb2_sys_total_ldb_qid {
-	struct {
-		u32 total_ldb_qid : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_DIR_CRDS 0x10000108
-#define DLB2_SYS_TOTAL_DIR_CRDS_RST 0x1000
-union dlb2_sys_total_dir_crds {
-	struct {
-		u32 total_dir_credits : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_TOTAL_LDB_CRDS 0x10000104
-#define DLB2_SYS_TOTAL_LDB_CRDS_RST 0x2000
-union dlb2_sys_total_ldb_crds {
-	struct {
-		u32 total_ldb_credits : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_PF_SYND2 0x10000508
-#define DLB2_SYS_ALARM_PF_SYND2_RST 0x0
-union dlb2_sys_alarm_pf_synd2 {
-	struct {
-		u32 lock_id : 16;
-		u32 meas : 1;
-		u32 debug : 7;
-		u32 cq_pop : 1;
-		u32 qe_uhl : 1;
-		u32 qe_orsp : 1;
-		u32 qe_valid : 1;
-		u32 cq_int_rearm : 1;
-		u32 dsi_error : 1;
-		u32 rsvd0 : 2;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_PF_SYND1 0x10000504
-#define DLB2_SYS_ALARM_PF_SYND1_RST 0x0
-union dlb2_sys_alarm_pf_synd1 {
-	struct {
-		u32 dsi : 16;
-		u32 qid : 8;
-		u32 qtype : 2;
-		u32 qpri : 3;
-		u32 msg_type : 3;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_PF_SYND0 0x10000500
-#define DLB2_SYS_ALARM_PF_SYND0_RST 0x0
-union dlb2_sys_alarm_pf_synd0 {
-	struct {
-		u32 syndrome : 8;
-		u32 rtype : 2;
-		u32 rsvd0 : 3;
-		u32 is_ldb : 1;
-		u32 cls : 2;
-		u32 aid : 6;
-		u32 unit : 4;
-		u32 source : 4;
-		u32 more : 1;
-		u32 valid : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_LDB_VPP_V(x) \
-	(0x10000f00 + (x) * 0x1000)
-#define DLB2_SYS_VF_LDB_VPP_V_RST 0x0
-union dlb2_sys_vf_ldb_vpp_v {
-	struct {
-		u32 vpp_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_LDB_VPP2PP(x) \
-	(0x10000f04 + (x) * 0x1000)
-#define DLB2_SYS_VF_LDB_VPP2PP_RST 0x0
-union dlb2_sys_vf_ldb_vpp2pp {
-	struct {
-		u32 pp : 6;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_DIR_VPP_V(x) \
-	(0x10000f08 + (x) * 0x1000)
-#define DLB2_SYS_VF_DIR_VPP_V_RST 0x0
-union dlb2_sys_vf_dir_vpp_v {
-	struct {
-		u32 vpp_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_DIR_VPP2PP(x) \
-	(0x10000f0c + (x) * 0x1000)
-#define DLB2_SYS_VF_DIR_VPP2PP_RST 0x0
-union dlb2_sys_vf_dir_vpp2pp {
-	struct {
-		u32 pp : 6;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_LDB_VQID_V(x) \
-	(0x10000f10 + (x) * 0x1000)
-#define DLB2_SYS_VF_LDB_VQID_V_RST 0x0
-union dlb2_sys_vf_ldb_vqid_v {
-	struct {
-		u32 vqid_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_LDB_VQID2QID(x) \
-	(0x10000f14 + (x) * 0x1000)
-#define DLB2_SYS_VF_LDB_VQID2QID_RST 0x0
-union dlb2_sys_vf_ldb_vqid2qid {
-	struct {
-		u32 qid : 5;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_QID2VQID(x) \
-	(0x10000f18 + (x) * 0x1000)
-#define DLB2_SYS_LDB_QID2VQID_RST 0x0
-union dlb2_sys_ldb_qid2vqid {
-	struct {
-		u32 vqid : 5;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_DIR_VQID_V(x) \
-	(0x10000f1c + (x) * 0x1000)
-#define DLB2_SYS_VF_DIR_VQID_V_RST 0x0
-union dlb2_sys_vf_dir_vqid_v {
-	struct {
-		u32 vqid_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_VF_DIR_VQID2QID(x) \
-	(0x10000f20 + (x) * 0x1000)
-#define DLB2_SYS_VF_DIR_VQID2QID_RST 0x0
-union dlb2_sys_vf_dir_vqid2qid {
-	struct {
-		u32 qid : 6;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_VASQID_V(x) \
-	(0x10000f24 + (x) * 0x1000)
-#define DLB2_SYS_LDB_VASQID_V_RST 0x0
-union dlb2_sys_ldb_vasqid_v {
-	struct {
-		u32 vasqid_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_VASQID_V(x) \
-	(0x10000f28 + (x) * 0x1000)
-#define DLB2_SYS_DIR_VASQID_V_RST 0x0
-union dlb2_sys_dir_vasqid_v {
-	struct {
-		u32 vasqid_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_VF_SYND2(x) \
-	(0x10000f48 + (x) * 0x1000)
-#define DLB2_SYS_ALARM_VF_SYND2_RST 0x0
-union dlb2_sys_alarm_vf_synd2 {
-	struct {
-		u32 lock_id : 16;
-		u32 debug : 8;
-		u32 cq_pop : 1;
-		u32 qe_uhl : 1;
-		u32 qe_orsp : 1;
-		u32 qe_valid : 1;
-		u32 isz : 1;
-		u32 dsi_error : 1;
-		u32 dlbrsvd : 2;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_VF_SYND1(x) \
-	(0x10000f44 + (x) * 0x1000)
-#define DLB2_SYS_ALARM_VF_SYND1_RST 0x0
-union dlb2_sys_alarm_vf_synd1 {
-	struct {
-		u32 dsi : 16;
-		u32 qid : 8;
-		u32 qtype : 2;
-		u32 qpri : 3;
-		u32 msg_type : 3;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_VF_SYND0(x) \
-	(0x10000f40 + (x) * 0x1000)
-#define DLB2_SYS_ALARM_VF_SYND0_RST 0x0
-union dlb2_sys_alarm_vf_synd0 {
-	struct {
-		u32 syndrome : 8;
-		u32 rtype : 2;
-		u32 vf_synd0_parity : 1;
-		u32 vf_synd1_parity : 1;
-		u32 vf_synd2_parity : 1;
-		u32 is_ldb : 1;
-		u32 cls : 2;
-		u32 aid : 6;
-		u32 unit : 4;
-		u32 source : 4;
-		u32 more : 1;
-		u32 valid : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_QID_CFG_V(x) \
-	(0x10000f58 + (x) * 0x1000)
-#define DLB2_SYS_LDB_QID_CFG_V_RST 0x0
-union dlb2_sys_ldb_qid_cfg_v {
-	struct {
-		u32 sn_cfg_v : 1;
-		u32 fid_cfg_v : 1;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_QID_ITS(x) \
-	(0x10000f54 + (x) * 0x1000)
-#define DLB2_SYS_LDB_QID_ITS_RST 0x0
-union dlb2_sys_ldb_qid_its {
-	struct {
-		u32 qid_its : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_QID_V(x) \
-	(0x10000f50 + (x) * 0x1000)
-#define DLB2_SYS_LDB_QID_V_RST 0x0
-union dlb2_sys_ldb_qid_v {
-	struct {
-		u32 qid_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_QID_ITS(x) \
-	(0x10000f64 + (x) * 0x1000)
-#define DLB2_SYS_DIR_QID_ITS_RST 0x0
-union dlb2_sys_dir_qid_its {
-	struct {
-		u32 qid_its : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_QID_V(x) \
-	(0x10000f60 + (x) * 0x1000)
-#define DLB2_SYS_DIR_QID_V_RST 0x0
-union dlb2_sys_dir_qid_v {
-	struct {
-		u32 qid_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_AI_DATA(x) \
-	(0x10000fa8 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_AI_DATA_RST 0x0
-union dlb2_sys_ldb_cq_ai_data {
-	struct {
-		u32 cq_ai_data : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_AI_ADDR(x) \
-	(0x10000fa4 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_AI_ADDR_RST 0x0
-union dlb2_sys_ldb_cq_ai_addr {
-	struct {
-		u32 rsvd1 : 2;
-		u32 cq_ai_addr : 18;
-		u32 rsvd0 : 12;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_PASID(x) \
-	(0x10000fa0 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_PASID_RST 0x0
-union dlb2_sys_ldb_cq_pasid {
-	struct {
-		u32 pasid : 20;
-		u32 exe_req : 1;
-		u32 priv_req : 1;
-		u32 fmt2 : 1;
-		u32 rsvd0 : 9;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_AT(x) \
-	(0x10000f9c + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_AT_RST 0x0
-union dlb2_sys_ldb_cq_at {
-	struct {
-		u32 cq_at : 2;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_ISR(x) \
-	(0x10000f98 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_ISR_RST 0x0
-/* CQ Interrupt Modes */
-#define DLB2_CQ_ISR_MODE_DIS  0
-#define DLB2_CQ_ISR_MODE_MSI  1
-#define DLB2_CQ_ISR_MODE_MSIX 2
-#define DLB2_CQ_ISR_MODE_ADI  3
-union dlb2_sys_ldb_cq_isr {
-	struct {
-		u32 vector : 6;
-		u32 vf : 4;
-		u32 en_code : 2;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ2VF_PF_RO(x) \
-	(0x10000f94 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ2VF_PF_RO_RST 0x0
-union dlb2_sys_ldb_cq2vf_pf_ro {
-	struct {
-		u32 vf : 4;
-		u32 is_pf : 1;
-		u32 ro : 1;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_PP_V(x) \
-	(0x10000f90 + (x) * 0x1000)
-#define DLB2_SYS_LDB_PP_V_RST 0x0
-union dlb2_sys_ldb_pp_v {
-	struct {
-		u32 pp_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_PP2VDEV(x) \
-	(0x10000f8c + (x) * 0x1000)
-#define DLB2_SYS_LDB_PP2VDEV_RST 0x0
-union dlb2_sys_ldb_pp2vdev {
-	struct {
-		u32 vdev : 4;
-		u32 rsvd0 : 28;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_PP2VAS(x) \
-	(0x10000f88 + (x) * 0x1000)
-#define DLB2_SYS_LDB_PP2VAS_RST 0x0
-union dlb2_sys_ldb_pp2vas {
-	struct {
-		u32 vas : 5;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_ADDR_U(x) \
-	(0x10000f84 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_ADDR_U_RST 0x0
-union dlb2_sys_ldb_cq_addr_u {
-	struct {
-		u32 addr_u : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_ADDR_L(x) \
-	(0x10000f80 + (x) * 0x1000)
-#define DLB2_SYS_LDB_CQ_ADDR_L_RST 0x0
-union dlb2_sys_ldb_cq_addr_l {
-	struct {
-		u32 rsvd0 : 6;
-		u32 addr_l : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_FMT(x) \
-	(0x10000fec + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_FMT_RST 0x0
-union dlb2_sys_dir_cq_fmt {
-	struct {
-		u32 keep_pf_ppid : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_AI_DATA(x) \
-	(0x10000fe8 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_AI_DATA_RST 0x0
-union dlb2_sys_dir_cq_ai_data {
-	struct {
-		u32 cq_ai_data : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_AI_ADDR(x) \
-	(0x10000fe4 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_AI_ADDR_RST 0x0
-union dlb2_sys_dir_cq_ai_addr {
-	struct {
-		u32 rsvd1 : 2;
-		u32 cq_ai_addr : 18;
-		u32 rsvd0 : 12;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_PASID(x) \
-	(0x10000fe0 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_PASID_RST 0x0
-union dlb2_sys_dir_cq_pasid {
-	struct {
-		u32 pasid : 20;
-		u32 exe_req : 1;
-		u32 priv_req : 1;
-		u32 fmt2 : 1;
-		u32 rsvd0 : 9;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_AT(x) \
-	(0x10000fdc + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_AT_RST 0x0
-union dlb2_sys_dir_cq_at {
-	struct {
-		u32 cq_at : 2;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_ISR(x) \
-	(0x10000fd8 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_ISR_RST 0x0
-union dlb2_sys_dir_cq_isr {
-	struct {
-		u32 vector : 6;
-		u32 vf : 4;
-		u32 en_code : 2;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ2VF_PF_RO(x) \
-	(0x10000fd4 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ2VF_PF_RO_RST 0x0
-union dlb2_sys_dir_cq2vf_pf_ro {
-	struct {
-		u32 vf : 4;
-		u32 is_pf : 1;
-		u32 ro : 1;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_PP_V(x) \
-	(0x10000fd0 + (x) * 0x1000)
-#define DLB2_SYS_DIR_PP_V_RST 0x0
-union dlb2_sys_dir_pp_v {
-	struct {
-		u32 pp_v : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_PP2VDEV(x) \
-	(0x10000fcc + (x) * 0x1000)
-#define DLB2_SYS_DIR_PP2VDEV_RST 0x0
-union dlb2_sys_dir_pp2vdev {
-	struct {
-		u32 vdev : 4;
-		u32 rsvd0 : 28;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_PP2VAS(x) \
-	(0x10000fc8 + (x) * 0x1000)
-#define DLB2_SYS_DIR_PP2VAS_RST 0x0
-union dlb2_sys_dir_pp2vas {
-	struct {
-		u32 vas : 5;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_ADDR_U(x) \
-	(0x10000fc4 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_ADDR_U_RST 0x0
-union dlb2_sys_dir_cq_addr_u {
-	struct {
-		u32 addr_u : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_ADDR_L(x) \
-	(0x10000fc0 + (x) * 0x1000)
-#define DLB2_SYS_DIR_CQ_ADDR_L_RST 0x0
-union dlb2_sys_dir_cq_addr_l {
-	struct {
-		u32 rsvd0 : 6;
-		u32 addr_l : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_INGRESS_ALARM_ENBL 0x10000300
-#define DLB2_SYS_INGRESS_ALARM_ENBL_RST 0x0
-union dlb2_sys_ingress_alarm_enbl {
-	struct {
-		u32 illegal_hcw : 1;
-		u32 illegal_pp : 1;
-		u32 illegal_pasid : 1;
-		u32 illegal_qid : 1;
-		u32 disabled_qid : 1;
-		u32 illegal_ldb_qid_cfg : 1;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_MSIX_ACK 0x10000400
-#define DLB2_SYS_MSIX_ACK_RST 0x0
-union dlb2_sys_msix_ack {
-	struct {
-		u32 msix_0_ack : 1;
-		u32 msix_1_ack : 1;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_MSIX_PASSTHRU 0x10000404
-#define DLB2_SYS_MSIX_PASSTHRU_RST 0x0
-union dlb2_sys_msix_passthru {
-	struct {
-		u32 msix_0_passthru : 1;
-		u32 msix_1_passthru : 1;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_MSIX_MODE 0x10000408
-#define DLB2_SYS_MSIX_MODE_RST 0x0
-/* MSI-X Modes */
-#define DLB2_MSIX_MODE_PACKED     0
-#define DLB2_MSIX_MODE_COMPRESSED 1
-union dlb2_sys_msix_mode {
-	struct {
-		u32 mode : 1;
-		u32 poll_mode : 1;
-		u32 poll_mask : 1;
-		u32 poll_lock : 1;
-		u32 rsvd0 : 28;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS 0x10000440
-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_RST 0x0
-union dlb2_sys_dir_cq_31_0_occ_int_sts {
-	struct {
-		u32 cq_0_occ_int : 1;
-		u32 cq_1_occ_int : 1;
-		u32 cq_2_occ_int : 1;
-		u32 cq_3_occ_int : 1;
-		u32 cq_4_occ_int : 1;
-		u32 cq_5_occ_int : 1;
-		u32 cq_6_occ_int : 1;
-		u32 cq_7_occ_int : 1;
-		u32 cq_8_occ_int : 1;
-		u32 cq_9_occ_int : 1;
-		u32 cq_10_occ_int : 1;
-		u32 cq_11_occ_int : 1;
-		u32 cq_12_occ_int : 1;
-		u32 cq_13_occ_int : 1;
-		u32 cq_14_occ_int : 1;
-		u32 cq_15_occ_int : 1;
-		u32 cq_16_occ_int : 1;
-		u32 cq_17_occ_int : 1;
-		u32 cq_18_occ_int : 1;
-		u32 cq_19_occ_int : 1;
-		u32 cq_20_occ_int : 1;
-		u32 cq_21_occ_int : 1;
-		u32 cq_22_occ_int : 1;
-		u32 cq_23_occ_int : 1;
-		u32 cq_24_occ_int : 1;
-		u32 cq_25_occ_int : 1;
-		u32 cq_26_occ_int : 1;
-		u32 cq_27_occ_int : 1;
-		u32 cq_28_occ_int : 1;
-		u32 cq_29_occ_int : 1;
-		u32 cq_30_occ_int : 1;
-		u32 cq_31_occ_int : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS 0x10000444
-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_RST 0x0
-union dlb2_sys_dir_cq_63_32_occ_int_sts {
-	struct {
-		u32 cq_32_occ_int : 1;
-		u32 cq_33_occ_int : 1;
-		u32 cq_34_occ_int : 1;
-		u32 cq_35_occ_int : 1;
-		u32 cq_36_occ_int : 1;
-		u32 cq_37_occ_int : 1;
-		u32 cq_38_occ_int : 1;
-		u32 cq_39_occ_int : 1;
-		u32 cq_40_occ_int : 1;
-		u32 cq_41_occ_int : 1;
-		u32 cq_42_occ_int : 1;
-		u32 cq_43_occ_int : 1;
-		u32 cq_44_occ_int : 1;
-		u32 cq_45_occ_int : 1;
-		u32 cq_46_occ_int : 1;
-		u32 cq_47_occ_int : 1;
-		u32 cq_48_occ_int : 1;
-		u32 cq_49_occ_int : 1;
-		u32 cq_50_occ_int : 1;
-		u32 cq_51_occ_int : 1;
-		u32 cq_52_occ_int : 1;
-		u32 cq_53_occ_int : 1;
-		u32 cq_54_occ_int : 1;
-		u32 cq_55_occ_int : 1;
-		u32 cq_56_occ_int : 1;
-		u32 cq_57_occ_int : 1;
-		u32 cq_58_occ_int : 1;
-		u32 cq_59_occ_int : 1;
-		u32 cq_60_occ_int : 1;
-		u32 cq_61_occ_int : 1;
-		u32 cq_62_occ_int : 1;
-		u32 cq_63_occ_int : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS 0x10000460
-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_RST 0x0
-union dlb2_sys_ldb_cq_31_0_occ_int_sts {
-	struct {
-		u32 cq_0_occ_int : 1;
-		u32 cq_1_occ_int : 1;
-		u32 cq_2_occ_int : 1;
-		u32 cq_3_occ_int : 1;
-		u32 cq_4_occ_int : 1;
-		u32 cq_5_occ_int : 1;
-		u32 cq_6_occ_int : 1;
-		u32 cq_7_occ_int : 1;
-		u32 cq_8_occ_int : 1;
-		u32 cq_9_occ_int : 1;
-		u32 cq_10_occ_int : 1;
-		u32 cq_11_occ_int : 1;
-		u32 cq_12_occ_int : 1;
-		u32 cq_13_occ_int : 1;
-		u32 cq_14_occ_int : 1;
-		u32 cq_15_occ_int : 1;
-		u32 cq_16_occ_int : 1;
-		u32 cq_17_occ_int : 1;
-		u32 cq_18_occ_int : 1;
-		u32 cq_19_occ_int : 1;
-		u32 cq_20_occ_int : 1;
-		u32 cq_21_occ_int : 1;
-		u32 cq_22_occ_int : 1;
-		u32 cq_23_occ_int : 1;
-		u32 cq_24_occ_int : 1;
-		u32 cq_25_occ_int : 1;
-		u32 cq_26_occ_int : 1;
-		u32 cq_27_occ_int : 1;
-		u32 cq_28_occ_int : 1;
-		u32 cq_29_occ_int : 1;
-		u32 cq_30_occ_int : 1;
-		u32 cq_31_occ_int : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS 0x10000464
-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_RST 0x0
-union dlb2_sys_ldb_cq_63_32_occ_int_sts {
-	struct {
-		u32 cq_32_occ_int : 1;
-		u32 cq_33_occ_int : 1;
-		u32 cq_34_occ_int : 1;
-		u32 cq_35_occ_int : 1;
-		u32 cq_36_occ_int : 1;
-		u32 cq_37_occ_int : 1;
-		u32 cq_38_occ_int : 1;
-		u32 cq_39_occ_int : 1;
-		u32 cq_40_occ_int : 1;
-		u32 cq_41_occ_int : 1;
-		u32 cq_42_occ_int : 1;
-		u32 cq_43_occ_int : 1;
-		u32 cq_44_occ_int : 1;
-		u32 cq_45_occ_int : 1;
-		u32 cq_46_occ_int : 1;
-		u32 cq_47_occ_int : 1;
-		u32 cq_48_occ_int : 1;
-		u32 cq_49_occ_int : 1;
-		u32 cq_50_occ_int : 1;
-		u32 cq_51_occ_int : 1;
-		u32 cq_52_occ_int : 1;
-		u32 cq_53_occ_int : 1;
-		u32 cq_54_occ_int : 1;
-		u32 cq_55_occ_int : 1;
-		u32 cq_56_occ_int : 1;
-		u32 cq_57_occ_int : 1;
-		u32 cq_58_occ_int : 1;
-		u32 cq_59_occ_int : 1;
-		u32 cq_60_occ_int : 1;
-		u32 cq_61_occ_int : 1;
-		u32 cq_62_occ_int : 1;
-		u32 cq_63_occ_int : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_DIR_CQ_OPT_CLR 0x100004c0
-#define DLB2_SYS_DIR_CQ_OPT_CLR_RST 0x0
-union dlb2_sys_dir_cq_opt_clr {
-	struct {
-		u32 cq : 6;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_SYS_ALARM_HW_SYND 0x1000050c
-#define DLB2_SYS_ALARM_HW_SYND_RST 0x0
-union dlb2_sys_alarm_hw_synd {
-	struct {
-		u32 syndrome : 8;
-		u32 rtype : 2;
-		u32 alarm : 1;
-		u32 cwd : 1;
-		u32 vf_pf_mb : 1;
-		u32 rsvd0 : 1;
-		u32 cls : 2;
-		u32 aid : 6;
-		u32 unit : 4;
-		u32 source : 4;
-		u32 more : 1;
-		u32 valid : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_AQED_PIPE_QID_FID_LIM(x) \
-	(0x20000000 + (x) * 0x1000)
-#define DLB2_AQED_PIPE_QID_FID_LIM_RST 0x7ff
-union dlb2_aqed_pipe_qid_fid_lim {
-	struct {
-		u32 qid_fid_limit : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_AQED_PIPE_QID_HID_WIDTH(x) \
-	(0x20080000 + (x) * 0x1000)
-#define DLB2_AQED_PIPE_QID_HID_WIDTH_RST 0x0
-union dlb2_aqed_pipe_qid_hid_width {
-	struct {
-		u32 compress_code : 3;
-		u32 rsvd0 : 29;
-	} field;
-	u32 val;
-};
-
-#define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0 0x24000004
-#define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfefcfaf8
-union dlb2_aqed_pipe_cfg_arb_weights_tqpri_atm_0 {
-	struct {
-		u32 pri0 : 8;
-		u32 pri1 : 8;
-		u32 pri2 : 8;
-		u32 pri3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_ATM_QID2CQIDIX_00(x) \
-	(0x30080000 + (x) * 0x1000)
-#define DLB2_ATM_QID2CQIDIX_00_RST 0x0
-#define DLB2_ATM_QID2CQIDIX(x, y) \
-	(DLB2_ATM_QID2CQIDIX_00(x) + 0x80000 * (y))
-#define DLB2_ATM_QID2CQIDIX_NUM 16
-union dlb2_atm_qid2cqidix_00 {
-	struct {
-		u32 cq_p0 : 8;
-		u32 cq_p1 : 8;
-		u32 cq_p2 : 8;
-		u32 cq_p3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN 0x34000004
-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_RST 0xfffefdfc
-union dlb2_atm_cfg_arb_weights_rdy_bin {
-	struct {
-		u32 bin0 : 8;
-		u32 bin1 : 8;
-		u32 bin2 : 8;
-		u32 bin3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN 0x34000008
-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_RST 0xfffefdfc
-union dlb2_atm_cfg_arb_weights_sched_bin {
-	struct {
-		u32 bin0 : 8;
-		u32 bin1 : 8;
-		u32 bin2 : 8;
-		u32 bin3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_VAS_CRD(x) \
-	(0x40000000 + (x) * 0x1000)
-#define DLB2_CHP_CFG_DIR_VAS_CRD_RST 0x0
-union dlb2_chp_cfg_dir_vas_crd {
-	struct {
-		u32 count : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_VAS_CRD(x) \
-	(0x40080000 + (x) * 0x1000)
-#define DLB2_CHP_CFG_LDB_VAS_CRD_RST 0x0
-union dlb2_chp_cfg_ldb_vas_crd {
-	struct {
-		u32 count : 15;
-		u32 rsvd0 : 17;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_ORD_QID_SN(x) \
-	(0x40100000 + (x) * 0x1000)
-#define DLB2_CHP_ORD_QID_SN_RST 0x0
-union dlb2_chp_ord_qid_sn {
-	struct {
-		u32 sn : 10;
-		u32 rsvd0 : 22;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_ORD_QID_SN_MAP(x) \
-	(0x40180000 + (x) * 0x1000)
-#define DLB2_CHP_ORD_QID_SN_MAP_RST 0x0
-union dlb2_chp_ord_qid_sn_map {
-	struct {
-		u32 mode : 3;
-		u32 slot : 4;
-		u32 rsvz0 : 1;
-		u32 grp : 1;
-		u32 rsvz1 : 1;
-		u32 rsvd0 : 22;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_SN_CHK_ENBL(x) \
-	(0x40200000 + (x) * 0x1000)
-#define DLB2_CHP_SN_CHK_ENBL_RST 0x0
-union dlb2_chp_sn_chk_enbl {
-	struct {
-		u32 en : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_DEPTH(x) \
-	(0x40280000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_DEPTH_RST 0x0
-union dlb2_chp_dir_cq_depth {
-	struct {
-		u32 depth : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(x) \
-	(0x40300000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RST 0x0
-union dlb2_chp_dir_cq_int_depth_thrsh {
-	struct {
-		u32 depth_threshold : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_INT_ENB(x) \
-	(0x40380000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_INT_ENB_RST 0x0
-union dlb2_chp_dir_cq_int_enb {
-	struct {
-		u32 en_tim : 1;
-		u32 en_depth : 1;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_TMR_THRSH(x) \
-	(0x40480000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_TMR_THRSH_RST 0x1
-union dlb2_chp_dir_cq_tmr_thrsh {
-	struct {
-		u32 thrsh_0 : 1;
-		u32 thrsh_13_1 : 13;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(x) \
-	(0x40500000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RST 0x0
-union dlb2_chp_dir_cq_tkn_depth_sel {
-	struct {
-		u32 token_depth_select : 4;
-		u32 rsvd0 : 28;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_WD_ENB(x) \
-	(0x40580000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_WD_ENB_RST 0x0
-union dlb2_chp_dir_cq_wd_enb {
-	struct {
-		u32 wd_enable : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_WPTR(x) \
-	(0x40600000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ_WPTR_RST 0x0
-union dlb2_chp_dir_cq_wptr {
-	struct {
-		u32 write_pointer : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ2VAS(x) \
-	(0x40680000 + (x) * 0x1000)
-#define DLB2_CHP_DIR_CQ2VAS_RST 0x0
-union dlb2_chp_dir_cq2vas {
-	struct {
-		u32 cq2vas : 5;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_HIST_LIST_BASE(x) \
-	(0x40700000 + (x) * 0x1000)
-#define DLB2_CHP_HIST_LIST_BASE_RST 0x0
-union dlb2_chp_hist_list_base {
-	struct {
-		u32 base : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_HIST_LIST_LIM(x) \
-	(0x40780000 + (x) * 0x1000)
-#define DLB2_CHP_HIST_LIST_LIM_RST 0x0
-union dlb2_chp_hist_list_lim {
-	struct {
-		u32 limit : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_HIST_LIST_POP_PTR(x) \
-	(0x40800000 + (x) * 0x1000)
-#define DLB2_CHP_HIST_LIST_POP_PTR_RST 0x0
-union dlb2_chp_hist_list_pop_ptr {
-	struct {
-		u32 pop_ptr : 13;
-		u32 generation : 1;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_HIST_LIST_PUSH_PTR(x) \
-	(0x40880000 + (x) * 0x1000)
-#define DLB2_CHP_HIST_LIST_PUSH_PTR_RST 0x0
-union dlb2_chp_hist_list_push_ptr {
-	struct {
-		u32 push_ptr : 13;
-		u32 generation : 1;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_DEPTH(x) \
-	(0x40900000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_DEPTH_RST 0x0
-union dlb2_chp_ldb_cq_depth {
-	struct {
-		u32 depth : 11;
-		u32 rsvd0 : 21;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(x) \
-	(0x40980000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RST 0x0
-union dlb2_chp_ldb_cq_int_depth_thrsh {
-	struct {
-		u32 depth_threshold : 11;
-		u32 rsvd0 : 21;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_INT_ENB(x) \
-	(0x40a00000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_INT_ENB_RST 0x0
-union dlb2_chp_ldb_cq_int_enb {
-	struct {
-		u32 en_tim : 1;
-		u32 en_depth : 1;
-		u32 rsvd0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_TMR_THRSH(x) \
-	(0x40b00000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_TMR_THRSH_RST 0x1
-union dlb2_chp_ldb_cq_tmr_thrsh {
-	struct {
-		u32 thrsh_0 : 1;
-		u32 thrsh_13_1 : 13;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(x) \
-	(0x40b80000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RST 0x0
-union dlb2_chp_ldb_cq_tkn_depth_sel {
-	struct {
-		u32 token_depth_select : 4;
-		u32 rsvd0 : 28;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_WD_ENB(x) \
-	(0x40c00000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_WD_ENB_RST 0x0
-union dlb2_chp_ldb_cq_wd_enb {
-	struct {
-		u32 wd_enable : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_WPTR(x) \
-	(0x40c80000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ_WPTR_RST 0x0
-union dlb2_chp_ldb_cq_wptr {
-	struct {
-		u32 write_pointer : 11;
-		u32 rsvd0 : 21;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ2VAS(x) \
-	(0x40d00000 + (x) * 0x1000)
-#define DLB2_CHP_LDB_CQ2VAS_RST 0x0
-union dlb2_chp_ldb_cq2vas {
-	struct {
-		u32 cq2vas : 5;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_CHP_CSR_CTRL 0x44000008
-#define DLB2_CHP_CFG_CHP_CSR_CTRL_RST 0x180002
-union dlb2_chp_cfg_chp_csr_ctrl {
-	struct {
-		u32 int_cor_alarm_dis : 1;
-		u32 int_cor_synd_dis : 1;
-		u32 int_uncr_alarm_dis : 1;
-		u32 int_unc_synd_dis : 1;
-		u32 int_inf0_alarm_dis : 1;
-		u32 int_inf0_synd_dis : 1;
-		u32 int_inf1_alarm_dis : 1;
-		u32 int_inf1_synd_dis : 1;
-		u32 int_inf2_alarm_dis : 1;
-		u32 int_inf2_synd_dis : 1;
-		u32 int_inf3_alarm_dis : 1;
-		u32 int_inf3_synd_dis : 1;
-		u32 int_inf4_alarm_dis : 1;
-		u32 int_inf4_synd_dis : 1;
-		u32 int_inf5_alarm_dis : 1;
-		u32 int_inf5_synd_dis : 1;
-		u32 dlb_cor_alarm_enable : 1;
-		u32 cfg_64bytes_qe_ldb_cq_mode : 1;
-		u32 cfg_64bytes_qe_dir_cq_mode : 1;
-		u32 pad_write_ldb : 1;
-		u32 pad_write_dir : 1;
-		u32 pad_first_write_ldb : 1;
-		u32 pad_first_write_dir : 1;
-		u32 rsvz0 : 9;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_INTR_ARMED0 0x4400005c
-#define DLB2_CHP_DIR_CQ_INTR_ARMED0_RST 0x0
-union dlb2_chp_dir_cq_intr_armed0 {
-	struct {
-		u32 armed : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_DIR_CQ_INTR_ARMED1 0x44000060
-#define DLB2_CHP_DIR_CQ_INTR_ARMED1_RST 0x0
-union dlb2_chp_dir_cq_intr_armed1 {
-	struct {
-		u32 armed : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL 0x44000084
-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RST 0x0
-union dlb2_chp_cfg_dir_cq_timer_ctl {
-	struct {
-		u32 sample_interval : 8;
-		u32 enb : 1;
-		u32 rsvz0 : 23;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_WDTO_0 0x44000088
-#define DLB2_CHP_CFG_DIR_WDTO_0_RST 0x0
-union dlb2_chp_cfg_dir_wdto_0 {
-	struct {
-		u32 wdto : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_WDTO_1 0x4400008c
-#define DLB2_CHP_CFG_DIR_WDTO_1_RST 0x0
-union dlb2_chp_cfg_dir_wdto_1 {
-	struct {
-		u32 wdto : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_WD_DISABLE0 0x44000098
-#define DLB2_CHP_CFG_DIR_WD_DISABLE0_RST 0xffffffff
-union dlb2_chp_cfg_dir_wd_disable0 {
-	struct {
-		u32 wd_disable : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_WD_DISABLE1 0x4400009c
-#define DLB2_CHP_CFG_DIR_WD_DISABLE1_RST 0xffffffff
-union dlb2_chp_cfg_dir_wd_disable1 {
-	struct {
-		u32 wd_disable : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000a0
-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RST 0x0
-union dlb2_chp_cfg_dir_wd_enb_interval {
-	struct {
-		u32 sample_interval : 28;
-		u32 enb : 1;
-		u32 rsvz0 : 3;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD 0x440000ac
-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RST 0x0
-union dlb2_chp_cfg_dir_wd_threshold {
-	struct {
-		u32 wd_threshold : 8;
-		u32 rsvz0 : 24;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_INTR_ARMED0 0x440000b0
-#define DLB2_CHP_LDB_CQ_INTR_ARMED0_RST 0x0
-union dlb2_chp_ldb_cq_intr_armed0 {
-	struct {
-		u32 armed : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_LDB_CQ_INTR_ARMED1 0x440000b4
-#define DLB2_CHP_LDB_CQ_INTR_ARMED1_RST 0x0
-union dlb2_chp_ldb_cq_intr_armed1 {
-	struct {
-		u32 armed : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL 0x440000d8
-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RST 0x0
-union dlb2_chp_cfg_ldb_cq_timer_ctl {
-	struct {
-		u32 sample_interval : 8;
-		u32 enb : 1;
-		u32 rsvz0 : 23;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_WDTO_0 0x440000dc
-#define DLB2_CHP_CFG_LDB_WDTO_0_RST 0x0
-union dlb2_chp_cfg_ldb_wdto_0 {
-	struct {
-		u32 wdto : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_WDTO_1 0x440000e0
-#define DLB2_CHP_CFG_LDB_WDTO_1_RST 0x0
-union dlb2_chp_cfg_ldb_wdto_1 {
-	struct {
-		u32 wdto : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_WD_DISABLE0 0x440000ec
-#define DLB2_CHP_CFG_LDB_WD_DISABLE0_RST 0xffffffff
-union dlb2_chp_cfg_ldb_wd_disable0 {
-	struct {
-		u32 wd_disable : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_WD_DISABLE1 0x440000f0
-#define DLB2_CHP_CFG_LDB_WD_DISABLE1_RST 0xffffffff
-union dlb2_chp_cfg_ldb_wd_disable1 {
-	struct {
-		u32 wd_disable : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL 0x440000f4
-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RST 0x0
-union dlb2_chp_cfg_ldb_wd_enb_interval {
-	struct {
-		u32 sample_interval : 28;
-		u32 enb : 1;
-		u32 rsvz0 : 3;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD 0x44000100
-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RST 0x0
-union dlb2_chp_cfg_ldb_wd_threshold {
-	struct {
-		u32 wd_threshold : 8;
-		u32 rsvz0 : 24;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CHP_CTRL_DIAG_02 0x4c000028
-#define DLB2_CHP_CTRL_DIAG_02_RST 0x1555
-union dlb2_chp_ctrl_diag_02 {
-	struct {
-		u32 egress_credit_status_empty : 1;
-		u32 egress_credit_status_afull : 1;
-		u32 chp_outbound_hcw_pipe_credit_status_empty : 1;
-		u32 chp_outbound_hcw_pipe_credit_status_afull : 1;
-		u32 chp_lsp_ap_cmp_pipe_credit_status_empty : 1;
-		u32 chp_lsp_ap_cmp_pipe_credit_status_afull : 1;
-		u32 chp_lsp_tok_pipe_credit_status_empty : 1;
-		u32 chp_lsp_tok_pipe_credit_status_afull : 1;
-		u32 chp_rop_pipe_credit_status_empty : 1;
-		u32 chp_rop_pipe_credit_status_afull : 1;
-		u32 qed_to_cq_pipe_credit_status_empty : 1;
-		u32 qed_to_cq_pipe_credit_status_afull : 1;
-		u32 egress_lsp_token_credit_status_empty : 1;
-		u32 egress_lsp_token_credit_status_afull : 1;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0 0x54000000
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_RST 0xfefcfaf8
-union dlb2_dp_cfg_arb_weights_tqpri_dir_0 {
-	struct {
-		u32 pri0 : 8;
-		u32 pri1 : 8;
-		u32 pri2 : 8;
-		u32 pri3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1 0x54000004
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RST 0x0
-union dlb2_dp_cfg_arb_weights_tqpri_dir_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x54000008
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8
-union dlb2_dp_cfg_arb_weights_tqpri_replay_0 {
-	struct {
-		u32 pri0 : 8;
-		u32 pri1 : 8;
-		u32 pri2 : 8;
-		u32 pri3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x5400000c
-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0
-union dlb2_dp_cfg_arb_weights_tqpri_replay_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_DP_DIR_CSR_CTRL 0x54000010
-#define DLB2_DP_DIR_CSR_CTRL_RST 0x0
-union dlb2_dp_dir_csr_ctrl {
-	struct {
-		u32 int_cor_alarm_dis : 1;
-		u32 int_cor_synd_dis : 1;
-		u32 int_uncr_alarm_dis : 1;
-		u32 int_unc_synd_dis : 1;
-		u32 int_inf0_alarm_dis : 1;
-		u32 int_inf0_synd_dis : 1;
-		u32 int_inf1_alarm_dis : 1;
-		u32 int_inf1_synd_dis : 1;
-		u32 int_inf2_alarm_dis : 1;
-		u32 int_inf2_synd_dis : 1;
-		u32 int_inf3_alarm_dis : 1;
-		u32 int_inf3_synd_dis : 1;
-		u32 int_inf4_alarm_dis : 1;
-		u32 int_inf4_synd_dis : 1;
-		u32 int_inf5_alarm_dis : 1;
-		u32 int_inf5_synd_dis : 1;
-		u32 rsvz0 : 16;
-	} field;
-	u32 val;
-};
-
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x84000000
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfefcfaf8
-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_0 {
-	struct {
-		u32 pri0 : 8;
-		u32 pri1 : 8;
-		u32 pri2 : 8;
-		u32 pri3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x84000004
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0x0
-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x84000008
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfefcfaf8
-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_0 {
-	struct {
-		u32 pri0 : 8;
-		u32 pri1 : 8;
-		u32 pri2 : 8;
-		u32 pri3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x8400000c
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RST 0x0
-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x84000010
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8
-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_0 {
-	struct {
-		u32 pri0 : 8;
-		u32 pri1 : 8;
-		u32 pri2 : 8;
-		u32 pri3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x84000014
-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0
-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_RO_PIPE_GRP_0_SLT_SHFT(x) \
-	(0x96000000 + (x) * 0x4)
-#define DLB2_RO_PIPE_GRP_0_SLT_SHFT_RST 0x0
-union dlb2_ro_pipe_grp_0_slt_shft {
-	struct {
-		u32 change : 10;
-		u32 rsvd0 : 22;
-	} field;
-	u32 val;
-};
-
-#define DLB2_RO_PIPE_GRP_1_SLT_SHFT(x) \
-	(0x96010000 + (x) * 0x4)
-#define DLB2_RO_PIPE_GRP_1_SLT_SHFT_RST 0x0
-union dlb2_ro_pipe_grp_1_slt_shft {
-	struct {
-		u32 change : 10;
-		u32 rsvd0 : 22;
-	} field;
-	u32 val;
-};
-
-#define DLB2_RO_PIPE_GRP_SN_MODE 0x94000000
-#define DLB2_RO_PIPE_GRP_SN_MODE_RST 0x0
-union dlb2_ro_pipe_grp_sn_mode {
-	struct {
-		u32 sn_mode_0 : 3;
-		u32 rszv0 : 5;
-		u32 sn_mode_1 : 3;
-		u32 rszv1 : 21;
-	} field;
-	u32 val;
-};
-
-#define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0 0x9c000000
-#define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0_RST 0x0
-union dlb2_ro_pipe_cfg_ctrl_general_0 {
-	struct {
-		u32 unit_single_step_mode : 1;
-		u32 rr_en : 1;
-		u32 rszv0 : 30;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ2PRIOV(x) \
-	(0xa0000000 + (x) * 0x1000)
-#define DLB2_LSP_CQ2PRIOV_RST 0x0
-union dlb2_lsp_cq2priov {
-	struct {
-		u32 prio : 24;
-		u32 v : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ2QID0(x) \
-	(0xa0080000 + (x) * 0x1000)
-#define DLB2_LSP_CQ2QID0_RST 0x0
-union dlb2_lsp_cq2qid0 {
-	struct {
-		u32 qid_p0 : 7;
-		u32 rsvd3 : 1;
-		u32 qid_p1 : 7;
-		u32 rsvd2 : 1;
-		u32 qid_p2 : 7;
-		u32 rsvd1 : 1;
-		u32 qid_p3 : 7;
-		u32 rsvd0 : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ2QID1(x) \
-	(0xa0100000 + (x) * 0x1000)
-#define DLB2_LSP_CQ2QID1_RST 0x0
-union dlb2_lsp_cq2qid1 {
-	struct {
-		u32 qid_p4 : 7;
-		u32 rsvd3 : 1;
-		u32 qid_p5 : 7;
-		u32 rsvd2 : 1;
-		u32 qid_p6 : 7;
-		u32 rsvd1 : 1;
-		u32 qid_p7 : 7;
-		u32 rsvd0 : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_DIR_DSBL(x) \
-	(0xa0180000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_DIR_DSBL_RST 0x1
-union dlb2_lsp_cq_dir_dsbl {
-	struct {
-		u32 disabled : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_DIR_TKN_CNT(x) \
-	(0xa0200000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_DIR_TKN_CNT_RST 0x0
-union dlb2_lsp_cq_dir_tkn_cnt {
-	struct {
-		u32 count : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \
-	(0xa0280000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST 0x0
-union dlb2_lsp_cq_dir_tkn_depth_sel_dsi {
-	struct {
-		u32 token_depth_select : 4;
-		u32 disable_wb_opt : 1;
-		u32 ignore_depth : 1;
-		u32 rsvd0 : 26;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(x) \
-	(0xa0300000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_RST 0x0
-union dlb2_lsp_cq_dir_tot_sch_cntl {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(x) \
-	(0xa0380000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_RST 0x0
-union dlb2_lsp_cq_dir_tot_sch_cnth {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_DSBL(x) \
-	(0xa0400000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_DSBL_RST 0x1
-union dlb2_lsp_cq_ldb_dsbl {
-	struct {
-		u32 disabled : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_INFL_CNT(x) \
-	(0xa0480000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_INFL_CNT_RST 0x0
-union dlb2_lsp_cq_ldb_infl_cnt {
-	struct {
-		u32 count : 12;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_INFL_LIM(x) \
-	(0xa0500000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_INFL_LIM_RST 0x0
-union dlb2_lsp_cq_ldb_infl_lim {
-	struct {
-		u32 limit : 12;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_TKN_CNT(x) \
-	(0xa0580000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_TKN_CNT_RST 0x0
-union dlb2_lsp_cq_ldb_tkn_cnt {
-	struct {
-		u32 token_count : 11;
-		u32 rsvd0 : 21;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(x) \
-	(0xa0600000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RST 0x0
-union dlb2_lsp_cq_ldb_tkn_depth_sel {
-	struct {
-		u32 token_depth_select : 4;
-		u32 ignore_depth : 1;
-		u32 rsvd0 : 27;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(x) \
-	(0xa0680000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_RST 0x0
-union dlb2_lsp_cq_ldb_tot_sch_cntl {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(x) \
-	(0xa0700000 + (x) * 0x1000)
-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_RST 0x0
-union dlb2_lsp_cq_ldb_tot_sch_cnth {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_DIR_MAX_DEPTH(x) \
-	(0xa0780000 + (x) * 0x1000)
-#define DLB2_LSP_QID_DIR_MAX_DEPTH_RST 0x0
-union dlb2_lsp_qid_dir_max_depth {
-	struct {
-		u32 depth : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(x) \
-	(0xa0800000 + (x) * 0x1000)
-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_RST 0x0
-union dlb2_lsp_qid_dir_tot_enq_cntl {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(x) \
-	(0xa0880000 + (x) * 0x1000)
-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_RST 0x0
-union dlb2_lsp_qid_dir_tot_enq_cnth {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT(x) \
-	(0xa0900000 + (x) * 0x1000)
-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RST 0x0
-union dlb2_lsp_qid_dir_enqueue_cnt {
-	struct {
-		u32 count : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_DIR_DEPTH_THRSH(x) \
-	(0xa0980000 + (x) * 0x1000)
-#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RST 0x0
-union dlb2_lsp_qid_dir_depth_thrsh {
-	struct {
-		u32 thresh : 13;
-		u32 rsvd0 : 19;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_AQED_ACTIVE_CNT(x) \
-	(0xa0a00000 + (x) * 0x1000)
-#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RST 0x0
-union dlb2_lsp_qid_aqed_active_cnt {
-	struct {
-		u32 count : 12;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_AQED_ACTIVE_LIM(x) \
-	(0xa0a80000 + (x) * 0x1000)
-#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RST 0x0
-union dlb2_lsp_qid_aqed_active_lim {
-	struct {
-		u32 limit : 12;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(x) \
-	(0xa0b00000 + (x) * 0x1000)
-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_RST 0x0
-union dlb2_lsp_qid_atm_tot_enq_cntl {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(x) \
-	(0xa0b80000 + (x) * 0x1000)
-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_RST 0x0
-union dlb2_lsp_qid_atm_tot_enq_cnth {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_ATQ_ENQUEUE_CNT(x) \
-	(0xa0c00000 + (x) * 0x1000)
-#define DLB2_LSP_QID_ATQ_ENQUEUE_CNT_RST 0x0
-union dlb2_lsp_qid_atq_enqueue_cnt {
-	struct {
-		u32 count : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT(x) \
-	(0xa0c80000 + (x) * 0x1000)
-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RST 0x0
-union dlb2_lsp_qid_ldb_enqueue_cnt {
-	struct {
-		u32 count : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_LDB_INFL_CNT(x) \
-	(0xa0d00000 + (x) * 0x1000)
-#define DLB2_LSP_QID_LDB_INFL_CNT_RST 0x0
-union dlb2_lsp_qid_ldb_infl_cnt {
-	struct {
-		u32 count : 12;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_LDB_INFL_LIM(x) \
-	(0xa0d80000 + (x) * 0x1000)
-#define DLB2_LSP_QID_LDB_INFL_LIM_RST 0x0
-union dlb2_lsp_qid_ldb_infl_lim {
-	struct {
-		u32 limit : 12;
-		u32 rsvd0 : 20;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID2CQIDIX_00(x) \
-	(0xa0e00000 + (x) * 0x1000)
-#define DLB2_LSP_QID2CQIDIX_00_RST 0x0
-#define DLB2_LSP_QID2CQIDIX(x, y) \
-	(DLB2_LSP_QID2CQIDIX_00(x) + 0x80000 * (y))
-#define DLB2_LSP_QID2CQIDIX_NUM 16
-union dlb2_lsp_qid2cqidix_00 {
-	struct {
-		u32 cq_p0 : 8;
-		u32 cq_p1 : 8;
-		u32 cq_p2 : 8;
-		u32 cq_p3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID2CQIDIX2_00(x) \
-	(0xa1600000 + (x) * 0x1000)
-#define DLB2_LSP_QID2CQIDIX2_00_RST 0x0
-#define DLB2_LSP_QID2CQIDIX2(x, y) \
-	(DLB2_LSP_QID2CQIDIX2_00(x) + 0x80000 * (y))
-#define DLB2_LSP_QID2CQIDIX2_NUM 16
-union dlb2_lsp_qid2cqidix2_00 {
-	struct {
-		u32 cq_p0 : 8;
-		u32 cq_p1 : 8;
-		u32 cq_p2 : 8;
-		u32 cq_p3 : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_LDB_REPLAY_CNT(x) \
-	(0xa1e00000 + (x) * 0x1000)
-#define DLB2_LSP_QID_LDB_REPLAY_CNT_RST 0x0
-union dlb2_lsp_qid_ldb_replay_cnt {
-	struct {
-		u32 count : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_NALDB_MAX_DEPTH(x) \
-	(0xa1f00000 + (x) * 0x1000)
-#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RST 0x0
-union dlb2_lsp_qid_naldb_max_depth {
-	struct {
-		u32 depth : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(x) \
-	(0xa1f80000 + (x) * 0x1000)
-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_RST 0x0
-union dlb2_lsp_qid_naldb_tot_enq_cntl {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(x) \
-	(0xa2000000 + (x) * 0x1000)
-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_RST 0x0
-union dlb2_lsp_qid_naldb_tot_enq_cnth {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_ATM_DEPTH_THRSH(x) \
-	(0xa2080000 + (x) * 0x1000)
-#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RST 0x0
-union dlb2_lsp_qid_atm_depth_thrsh {
-	struct {
-		u32 thresh : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH(x) \
-	(0xa2100000 + (x) * 0x1000)
-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RST 0x0
-union dlb2_lsp_qid_naldb_depth_thrsh {
-	struct {
-		u32 thresh : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_QID_ATM_ACTIVE(x) \
-	(0xa2180000 + (x) * 0x1000)
-#define DLB2_LSP_QID_ATM_ACTIVE_RST 0x0
-union dlb2_lsp_qid_atm_active {
-	struct {
-		u32 count : 14;
-		u32 rsvd0 : 18;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0xa4000008
-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_RST 0x0
-union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_0 {
-	struct {
-		u32 pri0_weight : 8;
-		u32 pri1_weight : 8;
-		u32 pri2_weight : 8;
-		u32 pri3_weight : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0xa400000c
-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RST 0x0
-union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0 0xa4000014
-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_RST 0x0
-union dlb2_lsp_cfg_arb_weight_ldb_qid_0 {
-	struct {
-		u32 pri0_weight : 8;
-		u32 pri1_weight : 8;
-		u32 pri2_weight : 8;
-		u32 pri3_weight : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1 0xa4000018
-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RST 0x0
-union dlb2_lsp_cfg_arb_weight_ldb_qid_1 {
-	struct {
-		u32 rsvz0 : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_LDB_SCHED_CTRL 0xa400002c
-#define DLB2_LSP_LDB_SCHED_CTRL_RST 0x0
-union dlb2_lsp_ldb_sched_ctrl {
-	struct {
-		u32 cq : 8;
-		u32 qidix : 3;
-		u32 value : 1;
-		u32 nalb_haswork_v : 1;
-		u32 rlist_haswork_v : 1;
-		u32 slist_haswork_v : 1;
-		u32 inflight_ok_v : 1;
-		u32 aqed_nfull_v : 1;
-		u32 rsvz0 : 15;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_DIR_SCH_CNT_L 0xa4000034
-#define DLB2_LSP_DIR_SCH_CNT_L_RST 0x0
-union dlb2_lsp_dir_sch_cnt_l {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_DIR_SCH_CNT_H 0xa4000038
-#define DLB2_LSP_DIR_SCH_CNT_H_RST 0x0
-union dlb2_lsp_dir_sch_cnt_h {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_LDB_SCH_CNT_L 0xa400003c
-#define DLB2_LSP_LDB_SCH_CNT_L_RST 0x0
-union dlb2_lsp_ldb_sch_cnt_l {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_LDB_SCH_CNT_H 0xa4000040
-#define DLB2_LSP_LDB_SCH_CNT_H_RST 0x0
-union dlb2_lsp_ldb_sch_cnt_h {
-	struct {
-		u32 count : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_SHDW_CTRL 0xa4000070
-#define DLB2_LSP_CFG_SHDW_CTRL_RST 0x0
-union dlb2_lsp_cfg_shdw_ctrl {
-	struct {
-		u32 transfer : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_SHDW_RANGE_COS(x) \
-	(0xa4000074 + (x) * 4)
-#define DLB2_LSP_CFG_SHDW_RANGE_COS_RST 0x40
-union dlb2_lsp_cfg_shdw_range_cos {
-	struct {
-		u32 bw_range : 9;
-		u32 rsvz0 : 22;
-		u32 no_extra_credit : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_LSP_CFG_CTRL_GENERAL_0 0xac000000
-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RST 0x0
-union dlb2_lsp_cfg_ctrl_general_0 {
-	struct {
-		u32 disab_atq_empty_arb : 1;
-		u32 inc_tok_unit_idle : 1;
-		u32 disab_rlist_pri : 1;
-		u32 inc_cmp_unit_idle : 1;
-		u32 rsvz0 : 2;
-		u32 dir_single_op : 1;
-		u32 dir_half_bw : 1;
-		u32 dir_single_out : 1;
-		u32 dir_disab_multi : 1;
-		u32 atq_single_op : 1;
-		u32 atq_half_bw : 1;
-		u32 atq_single_out : 1;
-		u32 atq_disab_multi : 1;
-		u32 dirrpl_single_op : 1;
-		u32 dirrpl_half_bw : 1;
-		u32 dirrpl_single_out : 1;
-		u32 lbrpl_single_op : 1;
-		u32 lbrpl_half_bw : 1;
-		u32 lbrpl_single_out : 1;
-		u32 ldb_single_op : 1;
-		u32 ldb_half_bw : 1;
-		u32 ldb_disab_multi : 1;
-		u32 atm_single_sch : 1;
-		u32 atm_single_cmp : 1;
-		u32 ldb_ce_tog_arb : 1;
-		u32 rsvz1 : 1;
-		u32 smon0_valid_sel : 2;
-		u32 smon0_value_sel : 1;
-		u32 smon0_compare_sel : 2;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CFG_MSTR_DIAG_RESET_STS 0xb4000000
-#define DLB2_CFG_MSTR_DIAG_RESET_STS_RST 0x80000bff
-union dlb2_cfg_mstr_diag_reset_sts {
-	struct {
-		u32 chp_pf_reset_done : 1;
-		u32 rop_pf_reset_done : 1;
-		u32 lsp_pf_reset_done : 1;
-		u32 nalb_pf_reset_done : 1;
-		u32 ap_pf_reset_done : 1;
-		u32 dp_pf_reset_done : 1;
-		u32 qed_pf_reset_done : 1;
-		u32 dqed_pf_reset_done : 1;
-		u32 aqed_pf_reset_done : 1;
-		u32 sys_pf_reset_done : 1;
-		u32 pf_reset_active : 1;
-		u32 flrsm_state : 7;
-		u32 rsvd0 : 13;
-		u32 dlb_proc_reset_done : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS 0xb4000004
-#define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS_RST 0x9d0fffff
-union dlb2_cfg_mstr_cfg_diagnostic_idle_status {
-	struct {
-		u32 chp_pipeidle : 1;
-		u32 rop_pipeidle : 1;
-		u32 lsp_pipeidle : 1;
-		u32 nalb_pipeidle : 1;
-		u32 ap_pipeidle : 1;
-		u32 dp_pipeidle : 1;
-		u32 qed_pipeidle : 1;
-		u32 dqed_pipeidle : 1;
-		u32 aqed_pipeidle : 1;
-		u32 sys_pipeidle : 1;
-		u32 chp_unit_idle : 1;
-		u32 rop_unit_idle : 1;
-		u32 lsp_unit_idle : 1;
-		u32 nalb_unit_idle : 1;
-		u32 ap_unit_idle : 1;
-		u32 dp_unit_idle : 1;
-		u32 qed_unit_idle : 1;
-		u32 dqed_unit_idle : 1;
-		u32 aqed_unit_idle : 1;
-		u32 sys_unit_idle : 1;
-		u32 rsvd1 : 4;
-		u32 mstr_cfg_ring_idle : 1;
-		u32 mstr_cfg_mstr_idle : 1;
-		u32 mstr_flr_clkreq_b : 1;
-		u32 mstr_proc_idle : 1;
-		u32 mstr_proc_idle_masked : 1;
-		u32 rsvd0 : 2;
-		u32 dlb_func_idle : 1;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CFG_MSTR_CFG_PM_STATUS 0xb4000014
-#define DLB2_CFG_MSTR_CFG_PM_STATUS_RST 0x100403e
-union dlb2_cfg_mstr_cfg_pm_status {
-	struct {
-		u32 prochot : 1;
-		u32 pgcb_dlb_idle : 1;
-		u32 pgcb_dlb_pg_rdy_ack_b : 1;
-		u32 pmsm_pgcb_req_b : 1;
-		u32 pgbc_pmc_pg_req_b : 1;
-		u32 pmc_pgcb_pg_ack_b : 1;
-		u32 pmc_pgcb_fet_en_b : 1;
-		u32 pgcb_fet_en_b : 1;
-		u32 rsvz0 : 1;
-		u32 rsvz1 : 1;
-		u32 fuse_force_on : 1;
-		u32 fuse_proc_disable : 1;
-		u32 rsvz2 : 1;
-		u32 rsvz3 : 1;
-		u32 pm_fsm_d0tod3_ok : 1;
-		u32 pm_fsm_d3tod0_ok : 1;
-		u32 dlb_in_d3 : 1;
-		u32 rsvz4 : 7;
-		u32 pmsm : 8;
-	} field;
-	u32 val;
-};
-
-#define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE 0xb4000018
-#define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE_RST 0x1
-union dlb2_cfg_mstr_cfg_pm_pmcsr_disable {
-	struct {
-		u32 disable : 1;
-		u32 rsvz0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_VF2PF_MAILBOX_BYTES 256
-#define DLB2_FUNC_VF_VF2PF_MAILBOX(x) \
-	(0x1000 + (x) * 0x4)
-#define DLB2_FUNC_VF_VF2PF_MAILBOX_RST 0x0
-union dlb2_func_vf_vf2pf_mailbox {
-	struct {
-		u32 msg : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR 0x1f00
-#define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR_RST 0x0
-#define DLB2_FUNC_VF_SIOV_VF2PF_MAILBOX_ISR_TRIGGER 0x8000
-union dlb2_func_vf_vf2pf_mailbox_isr {
-	struct {
-		u32 isr : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_PF2VF_MAILBOX_BYTES 64
-#define DLB2_FUNC_VF_PF2VF_MAILBOX(x) \
-	(0x2000 + (x) * 0x4)
-#define DLB2_FUNC_VF_PF2VF_MAILBOX_RST 0x0
-union dlb2_func_vf_pf2vf_mailbox {
-	struct {
-		u32 msg : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR 0x2f00
-#define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR_RST 0x0
-union dlb2_func_vf_pf2vf_mailbox_isr {
-	struct {
-		u32 pf_isr : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_VF_MSI_ISR_PEND 0x2f10
-#define DLB2_FUNC_VF_VF_MSI_ISR_PEND_RST 0x0
-union dlb2_func_vf_vf_msi_isr_pend {
-	struct {
-		u32 isr_pend : 32;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS 0x3000
-#define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS_RST 0x1
-union dlb2_func_vf_vf_reset_in_progress {
-	struct {
-		u32 reset_in_progress : 1;
-		u32 rsvd0 : 31;
-	} field;
-	u32 val;
-};
-
-#define DLB2_FUNC_VF_VF_MSI_ISR 0x4000
-#define DLB2_FUNC_VF_VF_MSI_ISR_RST 0x0
-union dlb2_func_vf_vf_msi_isr {
-	struct {
-		u32 vf_msi_isr : 32;
-	} field;
-	u32 val;
-};
-
-#endif /* __DLB2_REGS_H */
Signature · 1 line
2.23.0
#171 lore raw

PATCH 24/25 event/dlb2: rename dlb2_regs_new.h to dlb2_regs.h

In reply to Timothy McDaniel

All references to the old register map have been removed, so it is safe to rename the new combined file that supports both DLB v2.0 and DLB v2.5. Also fixed all places where this file is included.

---
 drivers/event/dlb2/pf/base/dlb2_hw_types.h                  | 2 +-
 drivers/event/dlb2/pf/base/{dlb2_regs_new.h => dlb2_regs.h} | 6 +++---
 drivers/event/dlb2/pf/base/dlb2_resource.c                  | 2 +-
 drivers/event/dlb2/pf/dlb2_main.c                           | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)
 rename drivers/event/dlb2/pf/base/{dlb2_regs_new.h => dlb2_regs.h} (99%)
drivers/event/dlb2/pf/base/dlb2_hw_types.h +1 -1
index 0f418ef5d..db9dfd240 100644
@@ -10,7 +10,7 @@
 
 #include "dlb2_osdep_list.h"
 #include "dlb2_osdep_types.h"
-#include "dlb2_regs_new.h"
+#include "dlb2_regs.h"
 
 #define DLB2_BITS_SET(x, val, mask)	(x = ((x) & ~(mask))     \
 				 | (((val) << (mask##_LOC)) & (mask)))
drivers/event/dlb2/pf/base/dlb2_regs.h renamed from drivers/event/dlb2/pf/base/dlb2_regs_new.h +3 -3
similarity index 99%
rename from drivers/event/dlb2/pf/base/dlb2_regs_new.h
rename to drivers/event/dlb2/pf/base/dlb2_regs.h
index 593243d63..cdff5cb1f 100644
@@ -2,8 +2,8 @@
  * Copyright(c) 2016-2020 Intel Corporation
  */
 
-#ifndef __DLB2_REGS_NEW_H
-#define __DLB2_REGS_NEW_H
+#ifndef __DLB2_REGS_H
+#define __DLB2_REGS_H
 
 #include "dlb2_osdep_types.h"
 
@@ -4409,4 +4409,4 @@
 #define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_V_LOC		15
 #define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RSVD0_LOC	16
 
-#endif /* __DLB2_REGS_NEW_H */
+#endif /* __DLB2_REGS_H */
drivers/event/dlb2/pf/base/dlb2_resource.c +1 -1
index e5fa0f047..d71adce16 100644
@@ -9,7 +9,7 @@
 #include "dlb2_osdep.h"
 #include "dlb2_osdep_bitmap.h"
 #include "dlb2_osdep_types.h"
-#include "dlb2_regs_new.h"
+#include "dlb2_regs.h"
 #include "dlb2_resource.h"
 
 #include "../../dlb2_priv.h"
drivers/event/dlb2/pf/dlb2_main.c +1 -1
index 1f6ccf8e4..b6ec85b47 100644
@@ -13,7 +13,7 @@
 #include <rte_malloc.h>
 #include <rte_errno.h>
 
-#include "base/dlb2_regs_new.h"
+#include "base/dlb2_regs.h"
 #include "base/dlb2_hw_types.h"
 #include "base/dlb2_resource.h"
 #include "base/dlb2_osdep.h"
Signature · 1 line
2.23.0
#172 lore raw

PATCH 25/25 event/dlb2: update xstats for DLB v2.5

In reply to Timothy McDaniel

Add DLB v2.5 specific information such as credit metrics to xstats.

---
 drivers/event/dlb2/dlb2_xstats.c | 41 ++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)
drivers/event/dlb2/dlb2_xstats.c +37 -4
index b62e62060..d4c8d9903 100644
@@ -9,6 +9,7 @@
 
 #include "dlb2_priv.h"
 #include "dlb2_inline_fns.h"
+#include "pf/base/dlb2_regs.h"
 
 enum dlb2_xstats_type {
 	/* common to device and port */
@@ -21,6 +22,7 @@ enum dlb2_xstats_type {
 	zero_polls,			/**< Call dequeue burst and return 0 */
 	tx_nospc_ldb_hw_credits,	/**< Insufficient LDB h/w credits */
 	tx_nospc_dir_hw_credits,	/**< Insufficient DIR h/w credits */
+	tx_nospc_hw_credits,		/**< Insufficient h/w credits */
 	tx_nospc_inflight_max,		/**< Reach the new_event_threshold */
 	tx_nospc_new_event_limit,	/**< Insufficient s/w credits */
 	tx_nospc_inflight_credits,	/**< Port has too few s/w credits */
@@ -29,6 +31,7 @@ enum dlb2_xstats_type {
 	inflight_events,
 	ldb_pool_size,
 	dir_pool_size,
+	pool_size,
 	/* port specific */
 	tx_new,				/**< Send an OP_NEW event */
 	tx_fwd,				/**< Send an OP_FORWARD event */
@@ -129,6 +132,9 @@ dlb2_device_traffic_stat_get(struct dlb2_eventdev *dlb2,
 		case tx_nospc_dir_hw_credits:
 			val += port->stats.traffic.tx_nospc_dir_hw_credits;
 			break;
+		case tx_nospc_hw_credits:
+			val += port->stats.traffic.tx_nospc_hw_credits;
+			break;
 		case tx_nospc_inflight_max:
 			val += port->stats.traffic.tx_nospc_inflight_max;
 			break;
@@ -159,6 +165,7 @@ get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,
 	case zero_polls:
 	case tx_nospc_ldb_hw_credits:
 	case tx_nospc_dir_hw_credits:
+	case tx_nospc_hw_credits:
 	case tx_nospc_inflight_max:
 	case tx_nospc_new_event_limit:
 	case tx_nospc_inflight_credits:
@@ -171,6 +178,8 @@ get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,
 		return dlb2->num_ldb_credits;
 	case dir_pool_size:
 		return dlb2->num_dir_credits;
+	case pool_size:
+		return dlb2->num_credits;
 	default: return -1;
 	}
 }
@@ -203,6 +212,9 @@ get_port_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx,
 	case tx_nospc_dir_hw_credits:
 		return ev_port->stats.traffic.tx_nospc_dir_hw_credits;
 
+	case tx_nospc_hw_credits:
+		return ev_port->stats.traffic.tx_nospc_hw_credits;
+
 	case tx_nospc_inflight_max:
 		return ev_port->stats.traffic.tx_nospc_inflight_max;
 
@@ -357,6 +369,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		"zero_polls",
 		"tx_nospc_ldb_hw_credits",
 		"tx_nospc_dir_hw_credits",
+		"tx_nospc_hw_credits",
 		"tx_nospc_inflight_max",
 		"tx_nospc_new_event_limit",
 		"tx_nospc_inflight_credits",
@@ -364,6 +377,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		"inflight_events",
 		"ldb_pool_size",
 		"dir_pool_size",
+		"pool_size",
 	};
 	static const enum dlb2_xstats_type dev_types[] = {
 		rx_ok,
@@ -375,6 +389,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		zero_polls,
 		tx_nospc_ldb_hw_credits,
 		tx_nospc_dir_hw_credits,
+		tx_nospc_hw_credits,
 		tx_nospc_inflight_max,
 		tx_nospc_new_event_limit,
 		tx_nospc_inflight_credits,
@@ -382,6 +397,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		inflight_events,
 		ldb_pool_size,
 		dir_pool_size,
+		pool_size,
 	};
 	/* Note: generated device stats are not allowed to be reset. */
 	static const uint8_t dev_reset_allowed[] = {
@@ -394,6 +410,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		0, /* zero_polls */
 		0, /* tx_nospc_ldb_hw_credits */
 		0, /* tx_nospc_dir_hw_credits */
+		0, /* tx_nospc_hw_credits */
 		0, /* tx_nospc_inflight_max */
 		0, /* tx_nospc_new_event_limit */
 		0, /* tx_nospc_inflight_credits */
@@ -401,6 +418,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		0, /* inflight_events */
 		0, /* ldb_pool_size */
 		0, /* dir_pool_size */
+		0, /* pool_size */
 	};
 	static const char * const port_stats[] = {
 		"is_configured",
@@ -415,6 +433,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		"zero_polls",
 		"tx_nospc_ldb_hw_credits",
 		"tx_nospc_dir_hw_credits",
+		"tx_nospc_hw_credits",
 		"tx_nospc_inflight_max",
 		"tx_nospc_new_event_limit",
 		"tx_nospc_inflight_credits",
@@ -448,6 +467,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		zero_polls,
 		tx_nospc_ldb_hw_credits,
 		tx_nospc_dir_hw_credits,
+		tx_nospc_hw_credits,
 		tx_nospc_inflight_max,
 		tx_nospc_new_event_limit,
 		tx_nospc_inflight_credits,
@@ -481,6 +501,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)
 		1, /* zero_polls */
 		1, /* tx_nospc_ldb_hw_credits */
 		1, /* tx_nospc_dir_hw_credits */
+		1, /* tx_nospc_hw_credits */
 		1, /* tx_nospc_inflight_max */
 		1, /* tx_nospc_new_event_limit */
 		1, /* tx_nospc_inflight_credits */
@@ -935,8 +956,8 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
 		break;
 	case RTE_EVENT_DEV_XSTATS_PORT:
 		if (queue_port_id == -1) {
-			for (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version);
-					i++) {
+			for (i = 0;
+			     i < DLB2_MAX_NUM_PORTS(dlb2->version); i++) {
 				if (dlb2_xstats_reset_port(dlb2, i,
 							   ids, nb_ids))
 					return -EINVAL;
@@ -949,8 +970,8 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
 		break;
 	case RTE_EVENT_DEV_XSTATS_QUEUE:
 		if (queue_port_id == -1) {
-			for (i = 0; i < DLB2_MAX_NUM_QUEUES(dlb2->version);
-					i++) {
+			for (i = 0;
+			     i < DLB2_MAX_NUM_QUEUES(dlb2->version); i++) {
 				if (dlb2_xstats_reset_queue(dlb2, i,
 							    ids, nb_ids))
 					return -EINVAL;
@@ -1048,6 +1069,9 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
 	fprintf(f, "\tnum_dir_credits = %u\n",
 		dlb2->hw_rsrc_query_results.num_dir_credits);
 
+	fprintf(f, "\tnum_credits = %u\n",
+		dlb2->hw_rsrc_query_results.num_credits);
+
 	/* Port level information */
 
 	for (i = 0; i < dlb2->num_ports; i++) {
@@ -1102,6 +1126,12 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
 		fprintf(f, "\tdir_credits = %u\n",
 			p->qm_port.dir_credits);
 
+		fprintf(f, "\tcached_credits = %u\n",
+			p->qm_port.cached_credits);
+
+		fprintf(f, "\tdir_credits = %u\n",
+			p->qm_port.credits);
+
 		fprintf(f, "\tgenbit=%d, cq_idx=%d, cq_depth=%d\n",
 			p->qm_port.gen_bit,
 			p->qm_port.cq_idx,
@@ -1139,6 +1169,9 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
 		fprintf(f, "\t\ttx_nospc_dir_hw_credits %" PRIu64 "\n",
 			p->stats.traffic.tx_nospc_dir_hw_credits);
 
+		fprintf(f, "\t\ttx_nospc_hw_credits %" PRIu64 "\n",
+			p->stats.traffic.tx_nospc_hw_credits);
+
 		fprintf(f, "\t\ttx_nospc_inflight_max %" PRIu64 "\n",
 			p->stats.traffic.tx_nospc_inflight_max);
 
Signature · 1 line
2.23.0
#173 lore raw
In reply to Timothy McDaniel
Quoted 26 lines · Timothy McDaniel

This patch series adds support for DLB v2.5 to the current DLB V2.0 PMD. The resulting PMD supports both hardware versions.

The main differences between the DLB v2.5 and v2.0 hardware are:
- Number of queues/ports
- DLB v2.5 uses a combined credit pool, whereas DLB v2.0 splits credits into 2 pools, a directed credit pool and a load balanced credit pool.
- Different register maps, with different bit names and offsets

In order to support both hardware versions with the same PMD, and avoid code duplication, the file dlb2_resource.c required a complete rewrite. This required some creative staging of the changes in order to keep the individual patches relatively small, while also meeting the requirement that all individual patches in the set compile cleanly.

To accomplish this, a few temporary files are used:

dlb2_hw_types_new.h
dlb2_resources_new.h
dlb2_resources_new.c

Quoted 7 lines

As dlb2_resources_new.c is populated with the new combined v2.0/v2.5 low level logic, the corresponding old code is removed from dlb2_resource.c, thus allowing both the original and new code to continue to compile and link cleanly. Once all of the code has been migrated to the new model, the old versions of the files are removed, and the new versions are renamed, effectively replacing the old original files.

# Please make sure each patch compiles. It fails on the second patch[1] now with clang.
# Please check each patch with ./devtools/test-meson-builds.sh. # Also, update the release notes for 2.5 HW support.

[1]
FAILED: drivers/libtmp_rte_event_dlb2.a.p/event_dlb2_pf_base_dlb2_resource_new.c.o ccache clang -Idrivers/libtmp_rte_event_dlb2.a.p -Idrivers
-I../drivers -Idrivers/event/dlb2 -I../drivers/event/dlb2 -Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I.. -Iconfig -I../config -Ilib/librte_eal/include -I../lib/librte_eal/i
nclude -Ilib/librte_eal/linux/include
-I../lib/librte_eal/linux/include -Ilib/librte_eal/x86/include -I../lib/librte_eal/x86/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs
-I../lib/librte_kvargs -Ilib/librte_metrics -I../lib/librte_metrics
-Ilib/librte_telemetry -I../lib/librte_telemetry -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -Il
ib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_hash -Ilib/librte_rcu
-I../lib/librte_rcu -Ilib/librte_timer -I../lib/librte_timer - Ilib/librte_cryptodev -I../lib/librte_cryptodev -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Xclang -fcolor-diagnostics -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O2
-g -include rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat -Wformat-nonliteral -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wsign-compare -Wstrict-prototypes
-Wundef -Wwrite-strings -Wno-address-of-packed-member -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC -march=native -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API -MD -MQ drivers/libtmp_rte_event_dlb2.a.p/event_dlb2_pf_base_dlb2_resource
_new.c.o -MF drivers/libtmp_rte_event_dlb2.a.p/event_dlb2_pf_base_dlb2_resource_new.c.o.d -o drivers/libtmp_rte_event_dlb2.a.p/event_dlb2_pf_base_dlb2_resource_new.c.o -c ../drivers/event/dlb2/pf/base/dlb2_resource_new.c ../drivers/event/dlb2/pf/base/dlb2_resource_new.c:44:20: error: unused function 'dlb2_flush_csr' [-Werror,-Wunused-function]
static inline void dlb2_flush_csr(struct dlb2_hw *hw)

                   ^

1 error generated.
[1976/2578] Compiling C ob

Quoted 49 lines

As you review the code, you can ignore the code deletions from dlb2_resource.c, as that file continues to shrink as the new corresponding logic is added to dlb2_resource_new.c.

Timothy McDaniel (25):
event/dlb2: add dlb v2.5 probe
event/dlb2: add DLB v2.5 probe-time hardware init event/dlb2: add DLB v2.5 support to get_resources event/dlb2: add DLB v2.5 support to create sched domain event/dlb2: add DLB v2.5 support to domain reset event/dlb2: add DLB V2.5 support to create ldb queue event/dlb2: add DLB v2.5 support to create ldb port event/dlb2: add DLB v2.5 support to create dir port event/dlb2: add DLB v2.5 support to create dir queue event/dlb2: add DLB v2.5 support to map qid event/dlb2: add DLB v2.5 support to unmap queue event/dlb2: add DLB v2.5 support to start domain event/dlb2: add DLB v2.5 credit scheme
event/dlb2: Add DLB v2.5 support to get queue depth functions event/dlb2: add DLB v2.5 finish map/unmap interfaces event/dlb2: add DLB v2.5 sparse cq mode
event/dlb2: add DLB v2.5 support to sequence number management event/dlb2: consolidate dlb resource header files into one file event/dlb2: delete old dlb2_resource.c file event/dlb2: move dlb_resource_new.c to dlb_resource.c event/dlb2: remove temporary file, dlb_hw_types.h event/dlb2: move dlb2_hw_type_new.h to dlb2_hw_types.h event/dlb2: delete old register map file, dlb2_regs.h event/dlb2: rename dlb2_regs_new.h to dlb2_regs.h event/dlb2: update xstats for DLB v2.5

 drivers/event/dlb2/dlb2.c                  |  430 +-
 drivers/event/dlb2/dlb2_priv.h             |  158 +-
 drivers/event/dlb2/dlb2_user.h             |   27 +-
 drivers/event/dlb2/dlb2_xstats.c           |   70 +-
 drivers/event/dlb2/pf/base/dlb2_hw_types.h |  102 +-
 drivers/event/dlb2/pf/base/dlb2_mbox.h     |    1 -
 drivers/event/dlb2/pf/base/dlb2_osdep.h    |    3 +
 drivers/event/dlb2/pf/base/dlb2_regs.h     | 6063 +++++++++++++-------
 drivers/event/dlb2/pf/base/dlb2_resource.c | 3277 ++++++-----
 drivers/event/dlb2/pf/base/dlb2_resource.h |   28 +-
 drivers/event/dlb2/pf/dlb2_main.c          |   37 +-
 drivers/event/dlb2/pf/dlb2_pf.c            |   62 +-
 12 files changed, 6366 insertions(+), 3892 deletions(-)

--
2.23.0