DDR/L3 Scaling support on SC7280 SoCs
Subsystems (5)
v3 cover DDR/L3 Scaling support on SC7280 SoCs
The patch series adds support for DDR/L3 Scaling on SC7280 SoCs.
V3:
* Rename opp table nodes [Matthias]
* Rename opp phandles [Doug]
V2:
* Add a new opp table for cpu 7 to account for the additional frequencies supported by it.
Depends on the following patch series:
L3 Provider Support: https://lore.kernel.org/lkml/[email protected]/
CPUfreq Support: https://lore.kernel.org/lkml/[email protected]/
RPMH Provider Support: https://lore.kernel.org/lkml/[email protected]/
It also depends on L3 and cpufreq dt nodes from the ^^ series to not have overlapping memory regions.
Sibi Sankar (2):
cpufreq: blacklist SC7280 in cpufreq-dt-platdev
arm64: dts: qcom: sc7280: Add cpu OPP tables
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++ drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 2 files changed, 216 insertions(+)
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PATCH v3 1/2 cpufreq: blacklist SC7280 in cpufreq-dt-platdev
Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver.
--- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+)
drivers/cpufreq/cpufreq-dt-platdev.c +1 -0
@@ -137,6 +137,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, { .compatible = "qcom,sc7180", }, + { .compatible = "qcom,sc7280", }, { .compatible = "qcom,sdm845", }, { .compatible = "st,stih407", },
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Viresh Kumar
maintainerRe: [PATCH v3 1/2] cpufreq: blacklist SC7280 in cpufreq-dt-platdev
Quoted 14 lines · Sibi Sankar
Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>--- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+)drivers/cpufreq/cpufreq-dt-platdev.c +0
-0
drivers/cpufreq/cpufreq-dt-platdev.c static const struct of_device_id blacklist[] __initconst = { · line 143
Quoted 7 lines
drivers/cpufreq/cpufreq-dt-platdev.c +1
-0@@ -137,6 +137,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, { .compatible = "qcom,sc7180", }, + { .compatible = "qcom,sc7280", }, { .compatible = "qcom,sdm845", }, { .compatible = "st,stih407", },
Applied 1/2. Thanks.
What do you want to do for 2/2 ? Go through my tree? need an update ?
Signature · 1 line
viresh
Re: [PATCH v3 1/2] cpufreq: blacklist SC7280 in cpufreq-dt-platdev
Quoted 22 lines · Viresh Kumar
Quoted 21 lines · Sibi Sankar
Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>--- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+)drivers/cpufreq/cpufreq-dt-platdev.c +1
-0@@ -137,6 +137,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, { .compatible = "qcom,sc7180", }, + { .compatible = "qcom,sc7280", }, { .compatible = "qcom,sdm845", },
Quoted 5 lines
Quoted 1 line
{ .compatible = "st,stih407", },
Applied 1/2. Thanks.
What do you want to do for 2/2 ? Go through my tree? need an update ?
Lets skip pulling in 2/2 for now. It depends
on a few other changes to land first and the
cpufreq node for sc7280 needs a re-spin.
Signature · 2 lines
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Re: [PATCH v3 1/2] cpufreq: blacklist SC7280 in cpufreq-dt-platdev
Quoted 24 lines · Sibi Sankar
Quoted 23 lines · Viresh Kumar
Quoted 22 lines · Sibi Sankar
Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>--- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+)drivers/cpufreq/cpufreq-dt-platdev.c +1
-0@@ -137,6 +137,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, { .compatible = "qcom,sc7180", }, + { .compatible = "qcom,sc7280", }, { .compatible = "qcom,sdm845", },
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
{ .compatible = "st,stih407", },
Applied 1/2. Thanks.
What do you want to do for 2/2 ? Go through my tree? need an update ?
Lets skip pulling in 2/2 for now.
In particular it's ripe for merge conflicts, so I'd prefer to take it through my tree.
Quoted 2 lines
It depends on a few other changes to land first and the cpufreq node for sc7280 needs a re-spin.
What other dependencies do we have?
I dropped the reg-names from the cpufreq node and merged that change.
Regards,
Bjorn
Re: [PATCH v3 1/2] cpufreq: blacklist SC7280 in cpufreq-dt-platdev
Quoted 37 lines · Bjorn Andersson
Quoted 24 lines · Sibi Sankar
Quoted 23 lines · Viresh Kumar
Quoted 22 lines · Sibi Sankar
Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>--- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+)drivers/cpufreq/cpufreq-dt-platdev.c +1
-0@@ -137,6 +137,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, { .compatible = "qcom,sc7180", }, + { .compatible = "qcom,sc7280", }, { .compatible = "qcom,sdm845", },Quoted 7 lines
Quoted 5 lines
Quoted 1 line
{ .compatible = "st,stih407", },
Applied 1/2. Thanks.
What do you want to do for 2/2 ? Go through my tree? need an update ?
Lets skip pulling in 2/2 for now.
In particular it's ripe for merge conflicts, so I'd prefer to take it through my tree.
Quoted 6 lines
Quoted 2 lines
It depends on a few other changes to land first and the cpufreq node for sc7280 needs a re-spin.
What other dependencies do we have?
I dropped the reg-names from the cpufreq node and merged that change.
It depends on the epss cpufreq and l3 node.
The reg regions used by the cpufreq and
l3 regions currently overlap and that needs
to be sorted out in cpufreq.
Quoted 3 lines
Regards,
Bjorn
Signature · 2 lines
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PATCH v3 2/2 arm64: dts: qcom: sc7280: Add cpu OPP tables
In reply to Sibi SankarAdd OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
---
V3:
* Rename cpu opp table nodes [Matthias]
* Rename opp phandles [Doug]
Depends on the following patch series:
L3 Provider Support: https://lore.kernel.org/lkml/[email protected]/
CPUfreq Support: https://lore.kernel.org/lkml/[email protected]/
RPMH Provider Support: https://lore.kernel.org/lkml/[email protected]/
It also depends on L3 and cpufreq dt nodes from the ^^ series to not have overlapping memory regions.
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +215 -0
@@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc7280.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -71,6 +72,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache";
@@ -90,6 +94,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache";
@@ -106,6 +113,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache";
@@ -122,6 +132,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache";
@@ -138,6 +151,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache";
@@ -154,6 +170,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache";
@@ -170,6 +189,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache";
@@ -186,6 +208,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache";
@@ -248,6 +273,196 @@ }; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_300mhz: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp_691mhz: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <800000 17817600>; + }; + + cpu0_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <800000 20889600>; + }; + + cpu0_opp_940mhz: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <1804000 24576000>; + }; + + cpu0_opp_1152mhz: opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <2188000 27033600>; + }; + + cpu0_opp_1324mhz: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 33792000>; + }; + + cpu0_opp_1516mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 38092800>; + }; + + cpu0_opp_1651mhz: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <3072000 41779200>; + }; + + cpu0_opp_1804mhz: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <4068000 48537600>; + }; + + cpu0_opp_1958mhz: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <4068000 48537600>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp_691mhz: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <1804000 9600000>; + }; + + cpu4_opp_940mhz: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 17817600>; + }; + + cpu4_opp_1228mhz: opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1344mhz: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1516mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1651mhz: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu4_opp_1900mhz: opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2054mhz: opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2131mhz: opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2208mhz: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2400mhz: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 48537600>; + }; + }; + + cpu7_opp_table: cpu7-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu7_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <1804000 9600000>; + }; + + cpu7_opp_1056mhz: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <2188000 17817600>; + }; + + cpu7_opp_1324mhz: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu7_opp_1516mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu7_opp_1766mhz: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_2035mhz: opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu7_opp_2208mhz: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu7_opp_2380mhz: opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <6832000 44851200>; + }; + + cpu7_opp_2400mhz: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_2515mhz: opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_2707mhz: opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <8532000 48537600>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */
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Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables
Quoted 127 lines · Sibi Sankar
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>---
V3:
* Rename cpu opp table nodes [Matthias]
* Rename opp phandles [Doug]Depends on the following patch series:
L3 Provider Support: https://lore.kernel.org/lkml/[email protected]/
CPUfreq Support: https://lore.kernel.org/lkml/[email protected]/
RPMH Provider Support: https://lore.kernel.org/lkml/[email protected]/It also depends on L3 and cpufreq dt nodes from the ^^ series to not have overlapping memory regions.
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +35
-0@@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc7280.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h>@@ -71,6 +72,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache";@@ -90,6 +94,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache";@@ -106,6 +113,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache";@@ -122,6 +132,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache";@@ -138,6 +151,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache";@@ -154,6 +170,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache";@@ -170,6 +189,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache";@@ -186,6 +208,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache";@@ -248,6 +273,196 @@ }; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_300mhz: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp_691mhz: opp-691200000 {
arch/arm64/boot/dts/qcom/sc7280.dtsi line 295
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <800000 17817600>; + }; + + cpu0_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <800000 20889600>; + }; + + cpu0_opp_940mhz: opp-940800000 {
nit: one could argue that rounded it's 941 MHz. Same for some other OPPs.
Not super-important though, so:
Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables
In reply to Sibi SankarHi,
Quoted 16 lines · Sibi Sankar
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>---
V3:
* Rename cpu opp table nodes [Matthias]
* Rename opp phandles [Doug]Depends on the following patch series:
L3 Provider Support: https://lore.kernel.org/lkml/[email protected]/
CPUfreq Support: https://lore.kernel.org/lkml/[email protected]/
RPMH Provider Support: https://lore.kernel.org/lkml/[email protected]/
Quoted 5 lines
It also depends on L3 and cpufreq dt nodes from the ^^ series to not have overlapping memory regions.
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+)
I see patch #1 in mainline now. Does that mean it's time to land patch #2 in the Qualcomm tree now? ...or maybe it needs to be re-posted?
-Doug
Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables
Quoted 19 lines · Doug Anderson
Hi,
Quoted 16 lines · Sibi Sankar
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
Reviewed-by Douglas Anderson <[email protected]>Signed-off-by Sibi Sankar <[email protected]>---
V3:
* Rename cpu opp table nodes [Matthias]
* Rename opp phandles [Doug]Depends on the following patch series:
L3 Provider Support: https://lore.kernel.org/lkml/[email protected]/
CPUfreq Support: https://lore.kernel.org/lkml/[email protected]/
RPMH Provider Support: https://lore.kernel.org/lkml/[email protected]/
Doug,
2 of the above 3 dependencies have
landed. L3 provider still needs a
re-spin.
https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
We also have a new series ^^ on the
list which will affect #2 merge.
Quoted 12 lines
Quoted 6 lines
It also depends on L3 and cpufreq dt nodes from the ^^ series to not have overlapping memory regions.
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+)I see patch #1 in mainline now. Does that mean it's time to land patch #2 in the Qualcomm tree now? ...or maybe it needs to be re-posted?
-Doug
Signature · 2 lines
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