FAILED: patch "[PATCH] drm/amdgpu: Init GFX10_ADDR_CONFIG for VCN v3 in DPG mode." failed to apply to 5.10-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 8bf073ca9235fe38d7b74a0b4e779cfa7cc70fc9 Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <[email protected]>
Date: Wed, 5 May 2021 03:27:49 +0200
Subject: [PATCH] drm/amdgpu: Init GFX10_ADDR_CONFIG for VCN v3 in DPG mode.
Otherwise tiling modes that require the values form this field (In particular _*_X) would be corrupted upon video decode.
Copied from the VCN v2 code.
Fixes 99541f392b4d ("drm/amdgpu: add mc resume DPG mode for VCN3.0")
Reviewed-and-Tested by: Leo Liu <[email protected]>
Signed-off-by Bas Nieuwenhuizen <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +4 -0
@@ -589,6 +589,10 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idxWREG32_SOC15_DPG_MODE (inst_idx,SOC15_DPG_MODE_OFFSET (VCN , inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),AMDGPU_GPU_PAGE_ALIGN (sizeof (struct amdgpu_fw_shared )),0 , indirect); + +/* VCN global tiling registers */ +WREG32_SOC15_DPG_MODE (0 ,SOC15_DPG_MODE_OFFSET ( +UVD ,0 , mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config,0 , indirect); }static void vcn_v3_0_disable_static_power_gating (struct amdgpu_device *adev,int inst)