Add CPT in Marvell CNXK common driver

new file mode 100644
index 0000000..d6a935c
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __CPT_HW_H__
+#define __CPT_HW_H__
+
+/* Register offsets */
+
+#define CPT_COMP_NOT_DONE (0x0ull)
+#define CPT_COMP_GOOD	  (0x1ull)
+#define CPT_COMP_FAULT	  (0x2ull)
+#define CPT_COMP_SWERR	  (0x3ull)
+#define CPT_COMP_HWERR	  (0x4ull)
+#define CPT_COMP_INSTERR  (0x5ull)
+#define CPT_COMP_WARN	  (0x6ull) /* [CN10K, .) */
+
+#define CPT_LF_INT_VEC_MISC	(0x0ull)
+#define CPT_LF_INT_VEC_DONE	(0x1ull)
+#define CPT_LF_CTL		(0x10ull)
+#define CPT_LF_DONE_WAIT	(0x30ull)
+#define CPT_LF_INPROG		(0x40ull)
+#define CPT_LF_DONE		(0x50ull)
+#define CPT_LF_DONE_ACK		(0x60ull)
+#define CPT_LF_DONE_INT_ENA_W1S (0x90ull)
+#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull)
+#define CPT_LF_MISC_INT		(0xb0ull)
+#define CPT_LF_MISC_INT_W1S	(0xc0ull)
+#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull)
+#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull)
+#define CPT_LF_Q_BASE		(0xf0ull)
+#define CPT_LF_Q_SIZE		(0x100ull)
+#define CPT_LF_Q_INST_PTR	(0x110ull)
+#define CPT_LF_Q_GRP_PTR	(0x120ull)
+#define CPT_LF_NQX(a)		(0x400ull | (uint64_t)(a) << 3)
+#define CPT_LF_CTX_CTL		(0x500ull)
+#define CPT_LF_CTX_FLUSH	(0x510ull)
+#define CPT_LF_CTX_ERR		(0x520ull)
+#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull)
+#define CPT_LF_CTX_ENC_PKT_CNT	(0x540ull)
+#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
+#define CPT_LF_CTX_DEC_PKT_CNT	(0x560ull)
+
+#define CPT_AF_LFX_CTL(a)  (0x27000ull | (uint64_t)(a) << 3)
+#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
+
+/* Structures definitions */
+
+union cpt_lf_ctl {
+	uint64_t u;
+	struct cpt_lf_ctl_s {
+		uint64_t ena : 1;
+		uint64_t fc_ena : 1;
+		uint64_t fc_up_crossing : 1;
+		uint64_t reserved_3_3 : 1;
+		uint64_t fc_hyst_bits : 4;
+		uint64_t reserved_8_63 : 56;
+	} s;
+};
+
+union cpt_lf_ctx_flush {
+	uint64_t u;
+	struct {
+		uint64_t cptr : 46;
+		uint64_t inval : 1;
+		uint64_t res : 1;
+		uint64_t pf_func : 16;
+	} s;
+};
+
+union cpt_lf_inprog {
+	uint64_t u;
+	struct cpt_lf_inprog_s {
+		uint64_t inflight : 9;
+		uint64_t reserved_9_15 : 7;
+		uint64_t eena : 1;
+		uint64_t grp_drp : 1;
+		uint64_t reserved_18_30 : 13;
+		uint64_t grb_partial : 1;
+		uint64_t grb_cnt : 8;
+		uint64_t gwb_cnt : 8;
+		uint64_t reserved_48_63 : 16;
+	} s;
+};
+
+union cpt_lf_q_base {
+	uint64_t u;
+	struct cpt_lf_q_base_s {
+		uint64_t fault : 1;
+		uint64_t stopped : 1;
+		uint64_t reserved_2_6 : 5;
+		uint64_t addr : 46;
+		uint64_t reserved_53_63 : 11;
+	} s;
+};
+
+union cpt_lf_q_size {
+	uint64_t u;
+	struct cpt_lf_q_size_s {
+		uint64_t size_div40 : 15;
+		uint64_t reserved_15_63 : 49;
+	} s;
+};
+
+union cpt_lf_misc_int {
+	uint64_t u;
+	struct cpt_lf_misc_int_s {
+		uint64_t reserved_0_0 : 1;
+		uint64_t nqerr : 1;
+		uint64_t irde : 1;
+		uint64_t nwrp : 1;
+		uint64_t reserved_4_4 : 1;
+		uint64_t hwerr : 1;
+		uint64_t fault : 1;
+		uint64_t reserved_7_63 : 57;
+	} s;
+};
+
+union cpt_inst_w4 {
+	uint64_t u64;
+	struct {
+		uint64_t dlen : 16;
+		uint64_t param2 : 16;
+		uint64_t param1 : 16;
+		uint64_t opcode_major : 8;
+		uint64_t opcode_minor : 8;
+	} s;
+};
+
+union cpt_inst_w7 {
+	uint64_t u64;
+	struct {
+		uint64_t cptr : 60;
+		uint64_t ctx_val : 1;
+		uint64_t egrp : 3;
+	} s;
+};
+
+struct cpt_inst_s {
+	union cpt_inst_w0 {
+		struct {
+			uint64_t nixtxl : 3;
+			uint64_t doneint : 1;
+			uint64_t nixtx_addr : 60;
+		} s;
+		uint64_t u64;
+	} w0;
+
+	uint64_t res_addr;
+
+	union cpt_inst_w2 {
+		struct {
+			uint64_t tag : 32;
+			uint64_t tt : 2;
+			uint64_t grp : 10;
+			uint64_t reserved_172_175 : 4;
+			uint64_t rvu_pf_func : 16;
+		} s;
+		uint64_t u64;
+	} w2;
+
+	union cpt_inst_w3 {
+		struct {
+			uint64_t qord : 1;
+			uint64_t reserved_194_193 : 2;
+			uint64_t wqe_ptr : 61;
+		} s;
+		uint64_t u64;
+	} w3;
+
+	union cpt_inst_w4 w4;
+
+	uint64_t dptr;
+
+	uint64_t rptr;
+
+	union cpt_inst_w7 w7;
+};
+
+union cpt_res_s {
+	struct cpt_cn10k_res_s {
+		uint64_t compcode : 7;
+		uint64_t doneint : 1;
+		uint64_t uc_compcode : 8;
+		uint64_t rlen : 16;
+		uint64_t spi : 32;
+
+		uint64_t esn;
+	} cn10k;
+
+	struct cpt_cn9k_res_s {
+		uint64_t compcode : 8;
+		uint64_t uc_compcode : 8;
+		uint64_t doneint : 1;
+		uint64_t reserved_17_63 : 47;
+
+		uint64_t reserved_64_127;
+	} cn9k;
+};
+
+#endif /* __CPT_HW_H__ */

index 67f5d13..049854d 100644
@@ -54,6 +54,11 @@
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
 
+#define PCI_DEVID_CN9K_RVU_CPT_PF  0xA0FD
+#define PCI_DEVID_CN9K_RVU_CPT_VF  0xA0FE
+#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2
+#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3
+
 #define PCI_SUBSYSTEM_DEVID_CN10KA  0xB900
 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
 

@@ -64,6 +69,7 @@
 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
 
 /* HW structure definition */
+#include "hw/cpt.h"
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"

index 049854d..88a5611 100644
@@ -106,4 +106,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* CPT */
+#include "roc_cpt.h"
+
 #endif /* _ROC_API_H_ */

273 lines not on this page · raw message

new file mode 100644
index 0000000..2630955
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_CPT_H_
+#define _ROC_CPT_H_
+
+#include "roc_api.h"
+
+#define ROC_CPT_MAX_LFS 64
+
+struct roc_cpt {
+	struct plt_pci_device *pci_dev;
+	struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];
+	uint16_t nb_lf;
+	uint16_t nb_lf_avail;
+	uintptr_t lmt_base;
+	/**< CPT device capabilities */
+	union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
+	uint8_t eng_grp[CPT_MAX_ENG_TYPES];
+
+#define ROC_CPT_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
+				  enum cpt_eng_type eng_type);
+int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
+void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
+#endif /* _ROC_CPT_H_ */

new file mode 100644
index 0000000..8cb2dbd
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_CPT_PRIV_H_
+#define _ROC_CPT_PRIV_H_
+
+/* Set number of number of hystbits to 6.
+ * This will trigger the FC writes whenever
+ * number of outstanding commands in the queue
+ * becomes multiple of 32.
+ */
+#define CPT_FC_NUM_HYST_BITS 6
+
+struct cpt {
+	struct plt_pci_device *pci_dev;
+	struct dev dev;
+	uint16_t lf_msix_off[ROC_CPT_MAX_LFS];
+	uint8_t lf_blkaddr[ROC_CPT_MAX_LFS];
+} __plt_cache_aligned;
+
+static inline struct cpt *
+roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt)
+{
+	return (struct cpt *)&roc_cpt->reserved[0];
+}
+
+#endif /* _ROC_CPT_PRIV_H_ */

index a39acc9..052ebe0 100644
@@ -870,6 +870,8 @@ dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev)
 		break;
 	case PCI_DEVID_CNXK_RVU_SSO_TIM_VF:
 	case PCI_DEVID_CNXK_RVU_NPA_VF:
+	case PCI_DEVID_CN10K_RVU_CPT_VF:
+	case PCI_DEVID_CN9K_RVU_CPT_VF:
 	case PCI_DEVID_CNXK_RVU_AF_VF:
 	case PCI_DEVID_CNXK_RVU_VF:
 	case PCI_DEVID_CNXK_RVU_SDP_VF:

index 910cfb6..f8277fb 100644
@@ -83,6 +83,7 @@ struct dev {
 	uint16_t maxvf;
 	struct dev_ops *ops;
 	void *roc_nix;
+	void *roc_cpt;
 	bool disable_shared_lmt; /* false(default): shared lmt mode enabled */
 } __plt_cache_aligned;
 

index 3999fce..74dbdec 100644
@@ -58,6 +58,7 @@ roc_plt_init(void)
 
 RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);
+RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);

index 7864fa4..524585f 100644
@@ -139,6 +139,7 @@
 /* Log */
 extern int cnxk_logtype_base;
 extern int cnxk_logtype_mbox;
+extern int cnxk_logtype_cpt;
 extern int cnxk_logtype_npa;
 extern int cnxk_logtype_nix;
 extern int cnxk_logtype_npc;

@@ -161,6 +162,7 @@ extern int cnxk_logtype_tm;
 		##args)
 
 #define plt_base_dbg(fmt, ...)	plt_dbg(base, fmt, ##__VA_ARGS__)
+#define plt_cpt_dbg(fmt, ...)	plt_dbg(cpt, fmt, ##__VA_ARGS__)
 #define plt_mbox_dbg(fmt, ...)	plt_dbg(mbox, fmt, ##__VA_ARGS__)
 #define plt_npa_dbg(fmt, ...)	plt_dbg(npa, fmt, ##__VA_ARGS__)
 #define plt_nix_dbg(fmt, ...)	plt_dbg(nix, fmt, ##__VA_ARGS__)

index 5e7564c..54c28fc 100644
@@ -32,4 +32,7 @@
 /* TIM */
 #include "roc_tim_priv.h"
 
+/* CPT */
+#include "roc_cpt_priv.h"
+
 #endif /* _ROC_PRIV_H_ */

index 3c0683c..11d8b9d 100644
@@ -5,6 +5,33 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+int
+roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rxc_time_cfg_req *req;
+	struct dev *dev = &cpt->dev;
+
+	req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->blkaddr = 0;
+
+	/* The step value is in microseconds. */
+	req->step = cfg->step;
+
+	/* The timeout will be: limit * step microseconds */
+	req->zombie_limit = cfg->zombie_limit;
+	req->zombie_thres = cfg->zombie_thres;
+
+	/* The timeout will be: limit * step microseconds */
+	req->active_limit = cfg->active_limit;
+	req->active_thres = cfg->active_thres;
+
+	return mbox_process(dev->mbox);
+}
+
 static int
 cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)
 {

index 2630955..5b84ec5 100644
@@ -23,6 +23,16 @@ struct roc_cpt {
 	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
 } __plt_cache_aligned;
 
+struct roc_cpt_rxc_time_cfg {
+	uint32_t step;
+	uint16_t active_limit;
+	uint16_t active_thres;
+	uint16_t zombie_limit;
+	uint16_t zombie_thres;
+};
+
+int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
+				   struct roc_cpt_rxc_time_cfg *cfg);
 int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,

index 11d8b9d..0ee3c02 100644
@@ -5,6 +5,119 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CPT_IQ_FC_LEN  128
+#define CPT_IQ_GRP_LEN 16
+
+#define CPT_IQ_NB_DESC_MULTIPLIER 40
+
+/* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8).
+ *
+ * CPT requires 320 free entries (+8). And 40 entries are required for
+ * allowing CPT to discard packet when the queues are full (+1).
+ */
+#define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc)                                     \
+	(PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8)
+
+#define CPT_IQ_GRP_SIZE(nb_desc)                                               \
+	(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN)
+
+#define CPT_LF_MAX_NB_DESC     128000
+#define CPT_LF_DEFAULT_NB_DESC 1024
+
+static void
+cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
+{
+	/* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */
+	if (enb)
+		plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
+			     BIT_ULL(1)),
+			    lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
+	else
+		plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
+			     BIT_ULL(1)),
+			    lf->rbase + CPT_LF_MISC_INT_ENA_W1C);
+}
+
+static void
+cpt_lf_misc_irq(void *param)
+{
+	struct roc_cpt_lf *lf = (struct roc_cpt_lf *)param;
+	struct dev *dev = lf->dev;
+	uint64_t intr;
+
+	intr = plt_read64(lf->rbase + CPT_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
+
+	/* Clear interrupt */
+	plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
+}
+
+static int
+cpt_lf_register_misc_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->roc_cpt->pci_dev;
+	struct plt_intr_handle *handle;
+	int rc, vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
+	/* Clear err interrupt */
+	cpt_lf_misc_intr_enb_dis(lf, false);
+	/* Set used interrupt vectors */
+	rc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec);
+	/* Enable all dev interrupt except for RQ_DISABLED */
+	cpt_lf_misc_intr_enb_dis(lf, true);
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->roc_cpt->pci_dev;
+	struct plt_intr_handle *handle;
+	int vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
+	/* Clear err interrupt */
+	cpt_lf_misc_intr_enb_dis(lf, false);
+	dev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec);
+}
+
+static int
+cpt_lf_register_irqs(struct roc_cpt_lf *lf)
+{
+	int rc;
+
+	if (lf->msixoff == MSIX_VECTOR_INVALID) {
+		plt_err("Invalid CPTLF MSIX vector offset vector: 0x%x",
+			lf->msixoff);
+		return -EINVAL;
+	}
+
+	/* Register lf err interrupt */
+	rc = cpt_lf_register_misc_irq(lf);
+	if (rc)
+		plt_err("Error registering IRQs");
+
+	/* TODO */
+	/* rc = cpt_lf_register_done_irq(cpt); */
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
+{
+	cpt_lf_unregister_misc_irq(lf);
+}
+
 int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {

@@ -135,6 +248,69 @@ cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
 	return 0;
 }
 
+static uint32_t
+cpt_lf_iq_mem_calc(uint32_t nb_desc)
+{
+	uint32_t len;
+
+	/* Space for instruction group memory */
+	len = CPT_IQ_GRP_SIZE(nb_desc);
+
+	/* Align to 128B */
+	len = PLT_ALIGN(len, ROC_ALIGN);
+
+	/* Space for FC */
+	len += CPT_IQ_FC_LEN;
+
+	/* For instruction queues */
+	len += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER *
+	       sizeof(struct cpt_inst_s);
+
+	return len;
+}
+
+static inline void
+cpt_iq_init(struct roc_cpt_lf *lf)
+{
+	union cpt_lf_q_size lf_q_size = {.u = 0x0};
+	union cpt_lf_q_base lf_q_base = {.u = 0x0};
+	union cpt_lf_inprog lf_inprog;
+	union cpt_lf_ctl lf_ctl;
+	uintptr_t addr;
+
+	lf->io_addr = lf->rbase + CPT_LF_NQX(0);
+
+	/* Disable command queue */
+	roc_cpt_iq_disable(lf);
+
+	/* Set command queue base address */
+	addr = (uintptr_t)lf->iq_vaddr +
+	       PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN);
+
+	lf_q_base.u = addr;
+
+	plt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE);
+
+	/* Set command queue size */
+	lf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc);
+	plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
+
+	/* Enable command queue execution */
+	lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
+	lf_inprog.s.eena = 1;
+	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
+
+	/* Enable instruction queue enqueuing */
+	lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
+	lf_ctl.s.ena = 1;
+	lf_ctl.s.fc_ena = 1;
+	lf_ctl.s.fc_up_crossing = 1;
+	lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;
+	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
+
+	lf->fc_addr = (uint64_t *)addr;
+}
+
 int
 roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 {

@@ -178,6 +354,49 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 }
 
 int
+roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)
+{
+	struct cpt *cpt;
+	void *iq_mem;
+	int rc;
+
+	cpt = roc_cpt_to_cpt_priv(roc_cpt);
+
+	if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)
+		lf->nb_desc = CPT_LF_DEFAULT_NB_DESC;
+
+	/* Allocate memory for instruction queue for CPT LF. */
+	iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);
+
+	plt_cpt_dbg("Initializing %d CPT LF", lf->lf_id);
+
+	lf->dev = &cpt->dev;
+	lf->roc_cpt = roc_cpt;
+	lf->msixoff = cpt->lf_msix_off[lf->lf_id];
+	lf->rbase = cpt->dev.bar2 +
+		    ((RVU_BLOCK_ADDR_CPT0 << 20) | (lf->lf_id << 12));
+	lf->iq_vaddr = iq_mem;
+	lf->lmt_base = cpt->dev.lmt_base;
+
+	/* Initialize instruction queue */
+	cpt_iq_init(lf);
+
+	rc = cpt_lf_register_irqs(lf);
+	if (rc)
+		goto lf_destroy;
+
+	lf->pf_func = cpt->dev.pf_func;
+
+	return 0;
+
+lf_destroy:
+	roc_cpt_iq_disable(lf);
+	plt_free(iq_mem);
+
+	return rc;
+}
+
+int
 roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 {
 	struct plt_pci_device *pci_dev;

@@ -228,6 +447,18 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	return rc;
 }
 
+void
+roc_cpt_lf_fini(struct roc_cpt_lf *lf)
+{
+	if (lf == NULL)
+		return;
+
+	cpt_lf_unregister_irqs(lf);
+
+	roc_cpt_iq_disable(lf);
+	plt_free(lf->iq_vaddr);
+}
+
 int
 roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
 {

@@ -298,3 +529,34 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
 
 	return rsp->eng_grp_num;
 }
+
+void
+roc_cpt_iq_disable(struct roc_cpt_lf *lf)
+{
+	union cpt_lf_ctl lf_ctl = {.u = 0x0};
+	union cpt_lf_inprog lf_inprog;
+	int timeout = 20;
+
+	/* Disable instructions enqueuing */
+	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
+
+	/* Wait for instruction queue to become empty */
+	do {
+		lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
+		if (!lf_inprog.s.inflight)
+			break;
+
+		plt_delay_ms(20);
+		if (timeout-- < 0) {
+			plt_err("CPT LF %d is still busy", lf->lf_id);
+			break;
+		}
+
+	} while (1);
+
+	/* Disable executions in the LF's queue.
+	 * The queue should be empty at this point
+	 */
+	lf_inprog.s.eena = 0x0;
+	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
+}

index 5b84ec5..abe492e 100644
@@ -9,6 +9,23 @@
 
 #define ROC_CPT_MAX_LFS 64
 
+struct roc_cpt_lf {
+	/* Input parameters */
+	uint16_t lf_id;
+	uint32_t nb_desc;
+	/* End of Input parameters */
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	struct roc_cpt *roc_cpt;
+	uintptr_t rbase;
+	uintptr_t lmt_base;
+	uint16_t msixoff;
+	uint16_t pf_func;
+	uint64_t *fc_addr;
+	uint64_t io_addr;
+	uint8_t *iq_vaddr;
+} __plt_cache_aligned;
+
 struct roc_cpt {
 	struct plt_pci_device *pci_dev;
 	struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];

@@ -39,4 +56,7 @@ int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
 				  enum cpt_eng_type eng_type);
 int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
+void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
 #endif /* _ROC_CPT_H_ */

index 0ee3c02..a23e4bb 100644
@@ -118,6 +118,34 @@ cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
 	cpt_lf_unregister_misc_irq(lf);
 }
 
+static void
+cpt_lf_dump(struct roc_cpt_lf *lf)
+{
+	plt_cpt_dbg("CPT LF");
+	plt_cpt_dbg("RBASE: 0x%016lx", lf->rbase);
+	plt_cpt_dbg("LMT_BASE: 0x%016lx", lf->lmt_base);
+	plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff);
+	plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id);
+	plt_cpt_dbg("NB DESC: %d", lf->nb_desc);
+	plt_cpt_dbg("FC_ADDR: 0x%016lx", (uintptr_t)lf->fc_addr);
+	plt_cpt_dbg("CQ.VADDR: 0x%016lx", (uintptr_t)lf->iq_vaddr);
+
+	plt_cpt_dbg("CPT LF REG:");
+	plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016lx", CPT_LF_CTL,
+		    plt_read64(lf->rbase + CPT_LF_CTL));
+	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016lx", CPT_LF_INPROG,
+		    plt_read64(lf->rbase + CPT_LF_INPROG));
+
+	plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016lx", CPT_LF_Q_BASE,
+		    plt_read64(lf->rbase + CPT_LF_Q_BASE));
+	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016lx", CPT_LF_Q_SIZE,
+		    plt_read64(lf->rbase + CPT_LF_Q_SIZE));
+	plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016lx", CPT_LF_Q_INST_PTR,
+		    plt_read64(lf->rbase + CPT_LF_Q_INST_PTR));
+	plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016lx", CPT_LF_Q_GRP_PTR,
+		    plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR));
+}
+
 int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {

@@ -387,6 +415,8 @@ roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)
 
 	lf->pf_func = cpt->dev.pf_func;
 
+	cpt_lf_dump(lf);
+
 	return 0;
 
 lf_destroy:

@@ -530,6 +560,158 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
 	return rsp->eng_grp_num;
 }
 
+static int
+cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rd_wr_reg_msg *msg;
+	struct dev *dev = &cpt->dev;
+	int ret;
+
+	msg = mbox_alloc_msg_cpt_rd_wr_register(dev->mbox);
+	if (msg == NULL)
+		return -EIO;
+
+	msg->hdr.pcifunc = dev->pf_func;
+
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+
+	ret = mbox_process_msg(dev->mbox, (void *)&msg);
+	if (ret)
+		return -EIO;
+
+	*val = msg->val;
+
+	return 0;
+}
+
+static int
+cpt_sts_print(struct roc_cpt *roc_cpt)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct dev *dev = &cpt->dev;
+	struct cpt_sts_req *req;
+	struct cpt_sts_rsp *rsp;
+	int ret;
+
+	req = mbox_alloc_msg_cpt_sts_get(dev->mbox);
+	if (req == NULL)
+		return -EIO;
+
+	req->blkaddr = 0;
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	plt_print("    %s:\t0x%016lx", "inst_req_pc", rsp->inst_req_pc);
+	plt_print("    %s:\t0x%016lx", "inst_lat_pc", rsp->inst_lat_pc);
+	plt_print("    %s:\t\t0x%016lx", "rd_req_pc", rsp->rd_req_pc);
+	plt_print("    %s:\t\t0x%016lx", "rd_lat_pc", rsp->rd_lat_pc);
+	plt_print("    %s:\t\t0x%016lx", "rd_uc_pc", rsp->rd_uc_pc);
+	plt_print("    %s:\t0x%016lx", "active_cycles_pc",
+		  rsp->active_cycles_pc);
+	plt_print("    %s:\t\t0x%016lx", "ctx_mis_pc", rsp->ctx_mis_pc);
+	plt_print("    %s:\t\t0x%016lx", "ctx_hit_pc", rsp->ctx_hit_pc);
+	plt_print("    %s:\t\t0x%016lx", "ctx_aop_pc", rsp->ctx_aop_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_aop_lat_pc", rsp->ctx_aop_lat_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_ifetch_pc", rsp->ctx_ifetch_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_ifetch_lat_pc",
+		  rsp->ctx_ifetch_lat_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_ffetch_pc", rsp->ctx_ffetch_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_ffetch_lat_pc",
+		  rsp->ctx_ffetch_lat_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_wback_pc", rsp->ctx_wback_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_wback_lat_pc",
+		  rsp->ctx_wback_lat_pc);
+	plt_print("    %s:\t\t0x%016lx", "ctx_psh_pc", rsp->ctx_psh_pc);
+	plt_print("    %s:\t0x%016lx", "ctx_psh_lat_pc", rsp->ctx_psh_lat_pc);
+	plt_print("    %s:\t\t0x%016lx", "ctx_err", rsp->ctx_err);
+	plt_print("    %s:\t\t0x%016lx", "ctx_enc_id", rsp->ctx_enc_id);
+	plt_print("    %s:\t0x%016lx", "ctx_flush_timer", rsp->ctx_flush_timer);
+	plt_print("    %s:\t\t0x%016lx", "rxc_time", rsp->rxc_time);
+	plt_print("    %s:\t0x%016lx", "rxc_time_cfg", rsp->rxc_time_cfg);
+	plt_print("    %s:\t0x%016lx", "rxc_active_sts", rsp->rxc_active_sts);
+	plt_print("    %s:\t0x%016lx", "rxc_zombie_sts", rsp->rxc_zombie_sts);
+	plt_print("    %s:\t0x%016lx", "rxc_dfrg", rsp->rxc_dfrg);
+	plt_print("    %s:\t0x%016lx", "x2p_link_cfg0", rsp->x2p_link_cfg0);
+	plt_print("    %s:\t0x%016lx", "x2p_link_cfg1", rsp->x2p_link_cfg1);
+	plt_print("    %s:\t0x%016lx", "busy_sts_ae", rsp->busy_sts_ae);
+	plt_print("    %s:\t0x%016lx", "free_sts_ae", rsp->free_sts_ae);
+	plt_print("    %s:\t0x%016lx", "busy_sts_se", rsp->busy_sts_se);
+	plt_print("    %s:\t0x%016lx", "free_sts_se", rsp->free_sts_se);
+	plt_print("    %s:\t0x%016lx", "busy_sts_ie", rsp->busy_sts_ie);
+	plt_print("    %s:\t0x%016lx", "free_sts_ie", rsp->free_sts_ie);
+	plt_print("    %s:\t0x%016lx", "exe_err_info", rsp->exe_err_info);
+	plt_print("    %s:\t\t0x%016lx", "cptclk_cnt", rsp->cptclk_cnt);
+	plt_print("    %s:\t\t0x%016lx", "diag", rsp->diag);
+
+	return 0;
+}
+
+int
+roc_cpt_afs_print(struct roc_cpt *roc_cpt)
+{
+	uint64_t reg_val;
+
+	plt_print("CPT AF registers:");
+
+	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), &reg_val))
+		return -EIO;
+
+	plt_print("    CPT_AF_LF0_CTL:\t0x%016lx", reg_val);
+
+	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), &reg_val))
+		return -EIO;
+
+	plt_print("    CPT_AF_LF0_CTL2:\t0x%016lx", reg_val);
+
+	cpt_sts_print(roc_cpt);
+
+	return 0;
+}
+
+static void
+cpt_lf_print(struct roc_cpt_lf *lf)
+{
+	uint64_t reg_val;
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
+	plt_print("    Encrypted byte count:\t%ld", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
+	plt_print("    Encrypted packet count:\t%ld", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
+	plt_print("    Decrypted byte count:\t%ld", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
+	plt_print("    Decrypted packet count:\t%ld", reg_val);
+}
+
+int
+roc_cpt_lfs_print(struct roc_cpt *roc_cpt)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct roc_cpt_lf *lf;
+	int lf_id;
+
+	if (cpt == NULL)
+		return -EINVAL;
+
+	for (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) {
+		lf = roc_cpt->lf[lf_id];
+		if (lf == NULL)
+			continue;
+
+		plt_print("Count registers for CPT LF%d:", lf_id);
+		cpt_lf_print(lf);
+	}
+
+	return 0;
+}
+
 void
 roc_cpt_iq_disable(struct roc_cpt_lf *lf)
 {

index abe492e..692fa79 100644
@@ -58,5 +58,7 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
 #endif /* _ROC_CPT_H_ */

index a23e4bb..d95b94c 100644
@@ -477,6 +477,24 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	return rc;
 }
 
+int
+roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr)
+{
+	union cpt_lf_ctx_flush reg;
+
+	if (lf == NULL)
+		return -ENOTSUP;
+
+	reg.u = 0;
+	reg.s.pf_func = lf->pf_func;
+	reg.s.inval = 1;
+	reg.s.cptr = cptr;
+
+	plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH);
+
+	return 0;
+}
+
 void
 roc_cpt_lf_fini(struct roc_cpt_lf *lf)
 {

index 692fa79..2b43a5a 100644
@@ -58,6 +58,7 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr);
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);

index 88a5611..6511614 100644
@@ -109,4 +109,7 @@
 /* CPT */
 #include "roc_cpt.h"
 
+/* CPT microcode */
+#include "roc_se.h"
+
 #endif /* _ROC_API_H_ */

287 lines not on this page · raw message

index 6511614..d545bb9 100644
@@ -110,6 +110,8 @@
 #include "roc_cpt.h"
 
 /* CPT microcode */
+#include "roc_ie_on.h"
+#include "roc_ie_ot.h"
 #include "roc_se.h"
 
 #endif /* _ROC_API_H_ */

new file mode 100644
index 0000000..a330ea1
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_H__
+#define __ROC_IE_H__
+
+/* CNXK IPSEC helper macros */
+#define ROC_IE_AH_HDR_LEN      12
+#define ROC_IE_AES_GCM_IV_LEN  8
+#define ROC_IE_AES_GCM_MAC_LEN 16
+#define ROC_IE_AES_CBC_IV_LEN  16
+#define ROC_IE_SHA1_HMAC_LEN   12
+#define ROC_IE_AUTH_KEY_LEN_MAX 64
+
+#define ROC_IE_AES_GCM_ROUNDUP_BYTE_LEN 4
+#define ROC_IE_AES_CBC_ROUNDUP_BYTE_LEN 16
+
+#endif /* __ROC_IE_H__ */

new file mode 100644
index 0000000..72ea037
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_ON_H__
+#define __ROC_IE_ON_H__
+
+/* CN9K IPSEC LA opcodes */
+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_OUTBOUND   0x20
+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_INBOUND	   0x21
+#define ROC_IE_ONL_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23
+#define ROC_IE_ONL_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x24
+
+/* CN9K IPSEC FP opcodes */
+#define ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x25
+#define ROC_IE_ONF_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x26
+
+#endif /* __ROC_IE_ON_H__ */

588 lines not on this page · raw message

index 524585f..97da87a 100644
@@ -49,6 +49,7 @@
 #define PLT_MODEL_MZ_NAME	 "roc_model_mz"
 #define PLT_CACHE_LINE_SIZE      RTE_CACHE_LINE_SIZE
 #define BITMASK_ULL		 GENMASK_ULL
+#define PLT_ALIGN_CEIL		 RTE_ALIGN_CEIL
 
 /** Divide ceil */
 #define PLT_DIV_CEIL(x, y)			\

new file mode 100644
index 0000000..c549e18
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_AE_H__
+#define __ROC_AE_H__
+
+/* AE opcodes */
+#define ROC_AE_MAJOR_OP_MODEX	     0x03
+#define ROC_AE_MAJOR_OP_ECDSA	     0x04
+#define ROC_AE_MAJOR_OP_ECC	     0x05
+#define ROC_AE_MINOR_OP_MODEX	     0x01
+#define ROC_AE_MINOR_OP_PKCS_ENC     0x02
+#define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03
+#define ROC_AE_MINOR_OP_PKCS_DEC     0x04
+#define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05
+#define ROC_AE_MINOR_OP_MODEX_CRT    0x06
+#define ROC_AE_MINOR_OP_ECDSA_SIGN   0x01
+#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02
+#define ROC_AE_MINOR_OP_ECC_UMP	     0x03
+
+/**
+ * Enumeration roc_ae_ec_id
+ *
+ * Enumerates supported elliptic curves
+ */
+typedef enum {
+	ROC_AE_EC_ID_P192 = 0,
+	ROC_AE_EC_ID_P224 = 1,
+	ROC_AE_EC_ID_P256 = 2,
+	ROC_AE_EC_ID_P384 = 3,
+	ROC_AE_EC_ID_P521 = 4,
+	ROC_AE_EC_ID_PMAX = 5
+} roc_ae_ec_id;
+
+/* Prime and order fields of built-in elliptic curves */
+struct roc_ae_ec_group {
+	struct {
+		/* P521 maximum length */
+		uint8_t data[66];
+		unsigned int length;
+	} prime;
+
+	struct {
+		/* P521 maximum length */
+		uint8_t data[66];
+		unsigned int length;
+	} order;
+};
+
+struct roc_ae_ec_ctx {
+	/* Prime length defined by microcode for EC operations */
+	uint8_t curveid;
+};
+
+#endif /* __ROC_AE_H__ */

index 2b43a5a..1e7a208 100644
@@ -7,6 +7,9 @@
 
 #include "roc_api.h"
 
+#define ROC_AE_CPT_BLOCK_TYPE1 0
+#define ROC_AE_CPT_BLOCK_TYPE2 1
+
 #define ROC_CPT_MAX_LFS 64
 
 struct roc_cpt_lf {

index d95b94c..6f344ee 100644
@@ -760,3 +760,23 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf)
 	lf_inprog.s.eena = 0x0;
 	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
 }
+
+int
+roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline,
+		     int lf_id)
+{
+	struct roc_cpt_lf *lf;
+
+	lf = roc_cpt->lf[lf_id];
+	if (lf == NULL)
+		return -ENOTSUP;
+
+	lmtline->io_addr = lf->io_addr;
+	if (roc_model_is_cn10k())
+		lmtline->io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4;
+
+	lmtline->fc_addr = lf->fc_addr;
+	lmtline->lmt_base = lf->lmt_base;
+
+	return 0;
+}

index 1e7a208..885c84d 100644
@@ -11,6 +11,34 @@
 #define ROC_AE_CPT_BLOCK_TYPE2 1
 
 #define ROC_CPT_MAX_LFS 64
+#define ROC_CN10K_CPT_INST_DW_M1                                               \
+	((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7))
+
+/* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of
+ * APT_LMT_ARG_S
+ */
+#define ROC_CN10K_CPT_LMT_ARG                                                  \
+	(ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14))
+
+struct roc_cpt_lmtline {
+	uint64_t io_addr;
+	uint64_t *fc_addr;
+	uintptr_t lmt_base;
+};
 
 struct roc_cpt_lf {
 	/* Input parameters */

@@ -65,4 +93,7 @@ int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr);
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt,
+				   struct roc_cpt_lmtline *lmtline, int lf_id);
+
 #endif /* _ROC_CPT_H_ */

1,140 lines not on this page · raw message

new file mode 100644
index 0000000..1cc5b02
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_AE_FPM_TABLES_H_
+#define _ROC_AE_FPM_TABLES_H_
+
+#include "roc_api.h"
+
+int __roc_api roc_ae_fpm_get(uint64_t *tbl);
+void __roc_api roc_ae_fpm_put(void);
+
+#endif /* _ROC_AE_FPM_TABLES_H_ */