arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card
Subsystems (5)
PATCH v4 1/1 arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card
Add nodes for eMMC and SD card on sc7280.
---
This change is depends on the below patch series:
https://lore.kernel.org/patchwork/cover/1418814/
Changes since V3:
- Changed pinconfig names as suggested by Konrad Dybcio.
- Removed extra lines and aligned some of lines as suggested by Bjorn Andersson.
Change since V2:
- Added leading zero's for register address and "qcom,sc7280-sdhci" string in compatible as suggested by Stephen Boyd and Doug.
- Removed max-frequency flag, no-mmc and no-sdio flags for Sd card as suggested by Doug and Stephen Boyd.
- Moved non-removable, no-sd, no-sdio and some pin config changes from soc to board dts file as suggested by Doug.
- Removed sleep state for CD line and drive-strength for input pins as suggested by Doug.
- Updated bus vote numbers for eMMC and SD card.
Changes since V1:
- Moved SDHC nodes as suggested by Bjorn Andersson.
- Dropped "pinconf-" prefix as suggested by Bjorn Andersson.
- Removed extra newlines as suggested by Konrad Dybcio.
- Changed sd-cd pin to bias-pull-up in sdc2_off as suggested by Veerabhadrarao Badiganti.
- Added bandwidth votes for eMMC and SD card.
--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 81 +++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 ++++++++++++++++++++++++++++++++ 2 files changed, 230 insertions(+)
arch/arm64/boot/dts/qcom/sc7280-idp.dts +81 -0
@@ -11,6 +11,7 @@ #include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/gpio/gpio.h> #include "sc7280.dtsi" #include "pm7325.dtsi" #include "pmr735a.dtsi"
@@ -272,6 +273,34 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &uart5 { status = "okay"; };
@@ -291,3 +320,55 @@ bias-pull-up; }; }; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + }; + }; +};
arch/arm64/boot/dts/qcom/sc7280.dtsi +149 -0
173 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quoting Shaik Sajida Bhanu (2021-06-16 02:23:01)
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 14
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0@@ -11,6 +11,7 @@ #include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/gpio/gpio.h>
The letter g comes before i, please move this higher in the list.
Quoted 39 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +28
-0#include "sc7280.dtsi" #include "pm7325.dtsi" #include "pmr735a.dtsi"@@ -272,6 +273,34 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &uart5 { status = "okay"; };
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 327
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +5
-0@@ -291,3 +320,55 @@ bias-pull-up; }; }; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk";
Can the pins property at least be moved into sc7280.dtsi? Then this can add bias and drive strength overrides in the board file?
Quoted 71 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +47
-0+ bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + }; + }; +};arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0@@ -974,6 +1033,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + status = "disabled"; + + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
arch/arm64/boot/dts/qcom/sc7280.dtsi line 1061
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + qcom,dll-config = <0x0007642c>; + + sdhc2_opp_table: sdhc2-opp-table {
Any reason the node shouldn't be called opp-table?
Quoted 12 lines · Stephen Boyd
Quoting Shaik Sajida Bhanu (2021-06-16 02:23:01)
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 14
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +1
-0@@ -11,6 +11,7 @@ #include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/gpio/gpio.h>The letter g comes before i, please move this higher in the list.
Sure i will adrress this in my next patchset.
Quoted 43 lines
Quoted 43 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +28
-0#include "sc7280.dtsi" #include "pm7325.dtsi" #include "pmr735a.dtsi"@@ -272,6 +273,34 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &uart5 { status = "okay"; };@@ -291,3 +320,55 @@ bias-pull-up; }; };
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts line 327
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +5
-0+ +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk";Can the pins property at least be moved into
sc7280.dtsi? Then this can add bias and drive strength overrides in the board file?
Sure i will adrress this in my next patchset.
Quoted 81 lines
Quoted 81 lines
arch/arm64/boot/dts/qcom/sc7280-idp.dts +47
-0+ bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + }; + }; +};arch/arm64/boot/dts/qcom/sc7280.dtsi +16
-0@@ -974,6 +1033,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + status = "disabled"; + + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0
&mc_virtSLAVE_EBI10>,
+ <&gem_nocMASTER_APPSS_PROC0
&cnoc2SLAVE_SDCC_20>;arch/arm64/boot/dts/qcom/sc7280.dtsi +3
-0+ interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>;
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 1061
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +6
-0+ + bus-width = <4>; + + qcom,dll-config = <0x0007642c>; + + sdhc2_opp_table: sdhc2-opp-table {Any reason the node shouldn't be called opp-table?
Yes, it can be called but for consistency, we are using the same node names as that on sc7180.