Add CPT in Marvell CNXK common driver

new file mode 100644
index 0000000..84ebf2d
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __CPT_HW_H__
+#define __CPT_HW_H__
+
+/* Register offsets */
+
+#define CPT_COMP_NOT_DONE (0x0ull)
+#define CPT_COMP_GOOD	  (0x1ull)
+#define CPT_COMP_FAULT	  (0x2ull)
+#define CPT_COMP_SWERR	  (0x3ull)
+#define CPT_COMP_HWERR	  (0x4ull)
+#define CPT_COMP_INSTERR  (0x5ull)
+#define CPT_COMP_WARN	  (0x6ull) /* [CN10K, .) */
+
+#define CPT_LF_INT_VEC_MISC	(0x0ull)
+#define CPT_LF_INT_VEC_DONE	(0x1ull)
+#define CPT_LF_CTL		(0x10ull)
+#define CPT_LF_DONE_WAIT	(0x30ull)
+#define CPT_LF_INPROG		(0x40ull)
+#define CPT_LF_DONE		(0x50ull)
+#define CPT_LF_DONE_ACK		(0x60ull)
+#define CPT_LF_DONE_INT_ENA_W1S (0x90ull)
+#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull)
+#define CPT_LF_MISC_INT		(0xb0ull)
+#define CPT_LF_MISC_INT_W1S	(0xc0ull)
+#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull)
+#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull)
+#define CPT_LF_Q_BASE		(0xf0ull)
+#define CPT_LF_Q_SIZE		(0x100ull)
+#define CPT_LF_Q_INST_PTR	(0x110ull)
+#define CPT_LF_Q_GRP_PTR	(0x120ull)
+#define CPT_LF_NQX(a)		(0x400ull | (uint64_t)(a) << 3)
+#define CPT_LF_CTX_CTL		(0x500ull)
+#define CPT_LF_CTX_FLUSH	(0x510ull)
+#define CPT_LF_CTX_ERR		(0x520ull)
+#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull)
+#define CPT_LF_CTX_ENC_PKT_CNT	(0x540ull)
+#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
+#define CPT_LF_CTX_DEC_PKT_CNT	(0x560ull)
+
+#define CPT_AF_LFX_CTL(a)  (0x27000ull | (uint64_t)(a) << 3)
+#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
+
+/* Structures definitions */
+
+union cpt_lf_ctl {
+	uint64_t u;
+	struct cpt_lf_ctl_s {
+		uint64_t ena : 1;
+		uint64_t fc_ena : 1;
+		uint64_t fc_up_crossing : 1;
+		uint64_t reserved_3_3 : 1;
+		uint64_t fc_hyst_bits : 4;
+		uint64_t reserved_8_63 : 56;
+	} s;
+};
+
+union cpt_lf_ctx_flush {
+	uint64_t u;
+	struct {
+		uint64_t cptr : 46;
+		uint64_t inval : 1;
+		uint64_t res : 1;
+		uint64_t pf_func : 16;
+	} s;
+};
+
+union cpt_lf_inprog {
+	uint64_t u;
+	struct cpt_lf_inprog_s {
+		uint64_t inflight : 9;
+		uint64_t reserved_9_15 : 7;
+		uint64_t eena : 1;
+		uint64_t grp_drp : 1;
+		uint64_t reserved_18_30 : 13;
+		uint64_t grb_partial : 1;
+		uint64_t grb_cnt : 8;
+		uint64_t gwb_cnt : 8;
+		uint64_t reserved_48_63 : 16;
+	} s;
+};
+
+union cpt_lf_q_base {
+	uint64_t u;
+	struct cpt_lf_q_base_s {
+		uint64_t fault : 1;
+		uint64_t stopped : 1;
+		uint64_t reserved_2_6 : 5;
+		uint64_t addr : 46;
+		uint64_t reserved_53_63 : 11;
+	} s;
+};
+
+union cpt_lf_q_size {
+	uint64_t u;
+	struct cpt_lf_q_size_s {
+		uint64_t size_div40 : 15;
+		uint64_t reserved_15_63 : 49;
+	} s;
+};
+
+union cpt_lf_misc_int {
+	uint64_t u;
+	struct cpt_lf_misc_int_s {
+		uint64_t reserved_0_0 : 1;
+		uint64_t nqerr : 1;
+		uint64_t irde : 1;
+		uint64_t nwrp : 1;
+		uint64_t reserved_4_4 : 1;
+		uint64_t hwerr : 1;
+		uint64_t fault : 1;
+		uint64_t reserved_7_63 : 57;
+	} s;
+};
+
+union cpt_inst_w4 {
+	uint64_t u64;
+	struct {
+		uint64_t dlen : 16;
+		uint64_t param2 : 16;
+		uint64_t param1 : 16;
+		uint64_t opcode_major : 8;
+		uint64_t opcode_minor : 8;
+	} s;
+};
+
+union cpt_inst_w7 {
+	uint64_t u64;
+	struct {
+		uint64_t cptr : 60;
+		uint64_t ctx_val : 1;
+		uint64_t egrp : 3;
+	} s;
+};
+
+struct cpt_inst_s {
+	union cpt_inst_w0 {
+		struct {
+			uint64_t nixtxl : 3;
+			uint64_t doneint : 1;
+			uint64_t nixtx_addr : 60;
+		} s;
+		uint64_t u64;
+	} w0;
+
+	uint64_t res_addr;
+
+	union cpt_inst_w2 {
+		struct {
+			uint64_t tag : 32;
+			uint64_t tt : 2;
+			uint64_t grp : 10;
+			uint64_t reserved_172_175 : 4;
+			uint64_t rvu_pf_func : 16;
+		} s;
+		uint64_t u64;
+	} w2;
+
+	union cpt_inst_w3 {
+		struct {
+			uint64_t qord : 1;
+			uint64_t reserved_194_193 : 2;
+			uint64_t wqe_ptr : 61;
+		} s;
+		uint64_t u64;
+	} w3;
+
+	union cpt_inst_w4 w4;
+
+	uint64_t dptr;
+
+	uint64_t rptr;
+
+	union cpt_inst_w7 w7;
+};
+
+union cpt_res_s {
+	struct cpt_cn10k_res_s {
+		uint64_t compcode : 7;
+		uint64_t doneint : 1;
+		uint64_t uc_compcode : 8;
+		uint64_t rlen : 16;
+		uint64_t spi : 32;
+
+		uint64_t esn;
+	} cn10k;
+
+	struct cpt_cn9k_res_s {
+		uint64_t compcode : 8;
+		uint64_t uc_compcode : 8;
+		uint64_t doneint : 1;
+		uint64_t reserved_17_63 : 47;
+
+		uint64_t reserved_64_127;
+	} cn9k;
+};
+
+/* [CN10K, .) */
+struct cpt_parse_hdr_s {
+	/* WORD 0 */
+	union {
+		uint64_t u64;
+		struct {
+			uint8_t pad_len : 3;
+			uint8_t num_frags : 3;
+			uint8_t pkt_out : 2;
+
+			uint8_t err_sum : 1;
+			uint8_t reas_sts : 4;
+			uint8_t reserved_53 : 1;
+			uint8_t et_owr : 1;
+			uint8_t pkt_fmt : 1;
+
+			uint16_t match_id : 16;
+
+			uint32_t cookie : 32;
+		};
+	} w0;
+
+	/* WORD 1 */
+	uint64_t wqe_ptr;
+
+	/* WORD 2 */
+	union {
+		uint64_t u64;
+		struct {
+			uint8_t fi_pad : 3;
+			uint8_t fi_offset : 5;
+			uint8_t il3_off;
+			uint16_t orig_pf_func;
+			uint16_t reserved_145_160;
+			uint16_t frag_age;
+		};
+	} w2;
+
+	/* WORD 3 */
+	union {
+		uint64_t u64;
+		struct {
+			uint32_t spi;
+			uint16_t reserved_209_224;
+			uint8_t uc_ccode;
+			uint8_t hw_ccode;
+		};
+	} w3;
+
+	/* WORD 4 */
+	union {
+		uint64_t u64;
+		uint64_t esn;
+		uint64_t frag1_wqe_ptr;
+	};
+};
+
+union cpt_frag_info {
+	uint16_t info;
+	struct {
+		uint16_t f_off : 13;
+		uint16_t f_mf : 1;
+		uint16_t f_rsv : 2;
+	};
+};
+
+struct cpt_frag_info_s {
+	/* WORD 0 */
+	union {
+		uint64_t u64;
+		struct {
+			union cpt_frag_info f3;
+			union cpt_frag_info f2;
+			union cpt_frag_info f1;
+			union cpt_frag_info f0;
+		};
+	} w0;
+
+	/* WORD 1 */
+	union {
+		uint64_t u64;
+		struct {
+			uint16_t frag_size3;
+			uint16_t frag_size2;
+			uint16_t frag_size1;
+			uint16_t frag_size0;
+		};
+	} w1;
+};
+
+#endif /* __CPT_HW_H__ */

index 67f5d13..049854d 100644
@@ -54,6 +54,11 @@
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
 
+#define PCI_DEVID_CN9K_RVU_CPT_PF  0xA0FD
+#define PCI_DEVID_CN9K_RVU_CPT_VF  0xA0FE
+#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2
+#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3
+
 #define PCI_SUBSYSTEM_DEVID_CN10KA  0xB900
 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
 

@@ -64,6 +69,7 @@
 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
 
 /* HW structure definition */
+#include "hw/cpt.h"
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"

index f6b11b6..fe4df21 100644
@@ -1328,6 +1328,9 @@ struct cpt_rxc_time_cfg_req {
 struct cpt_rx_inline_lf_cfg_msg {
 	struct mbox_msghdr hdr;
 	uint16_t __io sso_pf_func;
+	uint16_t __io param1;
+	uint16_t __io param2;
+	uint16_t __io reserved;
 };
 
 enum cpt_eng_type {

index 049854d..88a5611 100644
@@ -106,4 +106,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* CPT */
+#include "roc_cpt.h"
+
 #endif /* _ROC_API_H_ */

308 lines not on this page · raw message

new file mode 100644
index 0000000..4e1cf84
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_CPT_H_
+#define _ROC_CPT_H_
+
+#include "roc_api.h"
+
+/* Default engine groups */
+#define ROC_CPT_DFLT_ENG_GRP_SE	   0UL
+#define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
+#define ROC_CPT_DFLT_ENG_GRP_AE	   2UL
+
+#define ROC_CPT_MAX_LFS 64
+
+struct roc_cpt {
+	struct plt_pci_device *pci_dev;
+	struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];
+	uint16_t nb_lf;
+	uint16_t nb_lf_avail;
+	uintptr_t lmt_base;
+	/**< CPT device capabilities */
+	union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
+	uint8_t eng_grp[CPT_MAX_ENG_TYPES];
+
+#define ROC_CPT_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
+				  enum cpt_eng_type eng_type);
+int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
+void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
+#endif /* _ROC_CPT_H_ */

new file mode 100644
index 0000000..0ef6774
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_CPT_PRIV_H_
+#define _ROC_CPT_PRIV_H_
+
+/* Set number of hystbits to 6.
+ * This will trigger the FC writes whenever number of outstanding commands in
+ * the queue becomes multiple of 32.
+ */
+#define CPT_FC_NUM_HYST_BITS 6
+
+struct cpt {
+	struct plt_pci_device *pci_dev;
+	struct dev dev;
+	uint16_t lf_msix_off[ROC_CPT_MAX_LFS];
+	uint8_t lf_blkaddr[ROC_CPT_MAX_LFS];
+} __plt_cache_aligned;
+
+static inline struct cpt *
+roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt)
+{
+	return (struct cpt *)&roc_cpt->reserved[0];
+}
+
+int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify,
+		   uint16_t nb_lf);
+int cpt_lfs_detach(struct dev *dev);
+int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,
+		  bool inl_dev_sso);
+int cpt_lfs_free(struct dev *dev);
+
+int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
+uint64_t cpt_get_blkaddr(struct dev *dev);
+
+#endif /* _ROC_CPT_PRIV_H_ */

index a39acc9..052ebe0 100644
@@ -870,6 +870,8 @@ dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev)
 		break;
 	case PCI_DEVID_CNXK_RVU_SSO_TIM_VF:
 	case PCI_DEVID_CNXK_RVU_NPA_VF:
+	case PCI_DEVID_CN10K_RVU_CPT_VF:
+	case PCI_DEVID_CN9K_RVU_CPT_VF:
 	case PCI_DEVID_CNXK_RVU_AF_VF:
 	case PCI_DEVID_CNXK_RVU_VF:
 	case PCI_DEVID_CNXK_RVU_SDP_VF:

index 910cfb6..f8277fb 100644
@@ -83,6 +83,7 @@ struct dev {
 	uint16_t maxvf;
 	struct dev_ops *ops;
 	void *roc_nix;
+	void *roc_cpt;
 	bool disable_shared_lmt; /* false(default): shared lmt mode enabled */
 } __plt_cache_aligned;
 

index 3999fce..74dbdec 100644
@@ -58,6 +58,7 @@ roc_plt_init(void)
 
 RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);
+RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);

index 7864fa4..daee100 100644
@@ -139,6 +139,7 @@
 /* Log */
 extern int cnxk_logtype_base;
 extern int cnxk_logtype_mbox;
+extern int cnxk_logtype_cpt;
 extern int cnxk_logtype_npa;
 extern int cnxk_logtype_nix;
 extern int cnxk_logtype_npc;

@@ -161,6 +162,7 @@ extern int cnxk_logtype_tm;
 		##args)
 
 #define plt_base_dbg(fmt, ...)	plt_dbg(base, fmt, ##__VA_ARGS__)
+#define plt_cpt_dbg(fmt, ...)	plt_dbg(cpt, fmt, ##__VA_ARGS__)
 #define plt_mbox_dbg(fmt, ...)	plt_dbg(mbox, fmt, ##__VA_ARGS__)
 #define plt_npa_dbg(fmt, ...)	plt_dbg(npa, fmt, ##__VA_ARGS__)
 #define plt_nix_dbg(fmt, ...)	plt_dbg(nix, fmt, ##__VA_ARGS__)

@@ -169,6 +171,12 @@ extern int cnxk_logtype_tm;
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
 
+/* Datapath logs */
+#define plt_dp_err(fmt, args...)                                               \
+	RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
+#define plt_dp_info(fmt, args...)                                              \
+	RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
+
 #ifdef __cplusplus
 #define CNXK_PCI_ID(subsystem_dev, dev)                                        \
 	{                                                                      \

index 5e7564c..54c28fc 100644
@@ -32,4 +32,7 @@
 /* TIM */
 #include "roc_tim_priv.h"
 
+/* CPT */
+#include "roc_cpt_priv.h"
+
 #endif /* _ROC_PRIV_H_ */

index 2376125..d891a3b 100644
@@ -230,6 +230,10 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 
 	dev->roc_cpt = roc_cpt;
 
+	/* Set it to idev if not already present */
+	if (!roc_idev_cpt_get())
+		roc_idev_cpt_set(roc_cpt);
+
 	return 0;
 
 fail:

@@ -244,6 +248,10 @@ roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
 	if (cpt == NULL)
 		return -EINVAL;
 
+	/* Remove idev references */
+	if (roc_idev_cpt_get() == roc_cpt)
+		roc_idev_cpt_set(NULL);
+
 	roc_cpt->nb_lf_avail = 0;
 
 	roc_cpt->lmt_base = 0;

index 63cc040..b40ae82 100644
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
 	idev->lmt_pf_func = 0;
 	idev->lmt_base_addr = 0;
 	idev->num_lmtlines = 0;
+	idev->cpt = NULL;
 	__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
 }
 

@@ -170,6 +171,26 @@ roc_idev_num_lmtlines_get(void)
 	return num_lmtlines;
 }
 
+struct roc_cpt *
+roc_idev_cpt_get(void)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+
+	if (idev != NULL)
+		return idev->cpt;
+
+	return NULL;
+}
+
+void
+roc_idev_cpt_set(struct roc_cpt *cpt)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+
+	if (idev != NULL)
+		__atomic_store_n(&idev->cpt, cpt, __ATOMIC_RELEASE);
+}
+
 struct roc_nix *
 roc_idev_npa_nix_get(void)
 {

index 043e8af..16793c2 100644
@@ -12,6 +12,9 @@ void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools);
 uint64_t __roc_api roc_idev_lmt_base_addr_get(void);
 uint16_t __roc_api roc_idev_num_lmtlines_get(void);
 
+struct roc_cpt *__roc_api roc_idev_cpt_get(void);
+void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt);
+
 struct roc_nix *__roc_api roc_idev_npa_nix_get(void);
 
 #endif /* _ROC_IDEV_H_ */

index ff10a90..95b2389 100644
@@ -7,6 +7,7 @@
 
 /* Intra device related functions */
 struct npa_lf;
+struct roc_cpt;
 struct idev_cfg {
 	uint16_t sso_pf_func;
 	uint16_t npa_pf_func;

@@ -16,6 +17,7 @@ struct idev_cfg {
 	uint16_t lmt_pf_func;
 	uint16_t num_lmtlines;
 	uint64_t lmt_base_addr;
+	struct roc_cpt *cpt;
 };
 
 /* Generic */

index d891a3b..e723ee7 100644
@@ -6,6 +6,33 @@
 #include "roc_priv.h"
 
 int
+roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rxc_time_cfg_req *req;
+	struct dev *dev = &cpt->dev;
+
+	req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->blkaddr = 0;
+
+	/* The step value is in microseconds. */
+	req->step = cfg->step;
+
+	/* The timeout will be: limit * step microseconds */
+	req->zombie_limit = cfg->zombie_limit;
+	req->zombie_thres = cfg->zombie_thres;
+
+	/* The timeout will be: limit * step microseconds */
+	req->active_limit = cfg->active_limit;
+	req->active_thres = cfg->active_thres;
+
+	return mbox_process(dev->mbox);
+}
+
+int
 cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)
 {
 	struct mbox *mbox = dev->mbox;

index 4e1cf84..bae472f 100644
@@ -28,6 +28,16 @@ struct roc_cpt {
 	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
 } __plt_cache_aligned;
 
+struct roc_cpt_rxc_time_cfg {
+	uint32_t step;
+	uint16_t active_limit;
+	uint16_t active_thres;
+	uint16_t zombie_limit;
+	uint16_t zombie_thres;
+};
+
+int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
+				   struct roc_cpt_rxc_time_cfg *cfg);
 int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,

index e723ee7..02062c1 100644
@@ -5,6 +5,189 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CPT_IQ_FC_LEN  128
+#define CPT_IQ_GRP_LEN 16
+
+#define CPT_IQ_NB_DESC_MULTIPLIER 40
+
+/* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8).
+ *
+ * CPT requires 320 free entries (+8). And 40 entries are required for
+ * allowing CPT to discard packet when the queues are full (+1).
+ */
+#define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc)                                     \
+	(PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8)
+
+#define CPT_IQ_GRP_SIZE(nb_desc)                                               \
+	(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN)
+
+#define CPT_LF_MAX_NB_DESC     128000
+#define CPT_LF_DEFAULT_NB_DESC 1024
+
+static void
+cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
+{
+	/* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */
+	if (enb)
+		plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
+			     BIT_ULL(1)),
+			    lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
+	else
+		plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
+			     BIT_ULL(1)),
+			    lf->rbase + CPT_LF_MISC_INT_ENA_W1C);
+}
+
+static void
+cpt_lf_misc_irq(void *param)
+{
+	struct roc_cpt_lf *lf = (struct roc_cpt_lf *)param;
+	struct dev *dev = lf->dev;
+	uint64_t intr;
+
+	intr = plt_read64(lf->rbase + CPT_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
+
+	/* Clear interrupt */
+	plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
+}
+
+static int
+cpt_lf_register_misc_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int rc, vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
+	/* Clear err interrupt */
+	cpt_lf_misc_intr_enb_dis(lf, false);
+	/* Set used interrupt vectors */
+	rc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec);
+	/* Enable all dev interrupt except for RQ_DISABLED */
+	cpt_lf_misc_intr_enb_dis(lf, true);
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
+	/* Clear err interrupt */
+	cpt_lf_misc_intr_enb_dis(lf, false);
+	dev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec);
+}
+
+static void
+cpt_lf_done_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
+{
+	if (enb)
+		plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1S);
+	else
+		plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1C);
+}
+
+static void
+cpt_lf_done_irq(void *param)
+{
+	struct roc_cpt_lf *lf = param;
+	uint64_t done_wait;
+	uint64_t intr;
+
+	/* Read the number of completed requests */
+	intr = plt_read64(lf->rbase + CPT_LF_DONE);
+	if (intr == 0)
+		return;
+
+	done_wait = plt_read64(lf->rbase + CPT_LF_DONE_WAIT);
+
+	/* Acknowledge the number of completed requests */
+	plt_write64(intr, lf->rbase + CPT_LF_DONE_ACK);
+
+	plt_write64(done_wait, lf->rbase + CPT_LF_DONE_WAIT);
+}
+
+static int
+cpt_lf_register_done_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int rc, vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
+
+	/* Clear done interrupt */
+	cpt_lf_done_intr_enb_dis(lf, false);
+
+	/* Set used interrupt vectors */
+	rc = dev_irq_register(handle, cpt_lf_done_irq, lf, vec);
+
+	/* Enable done interrupt */
+	cpt_lf_done_intr_enb_dis(lf, true);
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_done_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
+
+	/* Clear done interrupt */
+	cpt_lf_done_intr_enb_dis(lf, false);
+	dev_irq_unregister(handle, cpt_lf_done_irq, lf, vec);
+}
+
+static int
+cpt_lf_register_irqs(struct roc_cpt_lf *lf)
+{
+	int rc;
+
+	if (lf->msixoff == MSIX_VECTOR_INVALID) {
+		plt_err("Invalid CPTLF MSIX vector offset vector: 0x%x",
+			lf->msixoff);
+		return -EINVAL;
+	}
+
+	/* Register lf err interrupt */
+	rc = cpt_lf_register_misc_irq(lf);
+	if (rc)
+		plt_err("Error registering IRQs");
+
+	rc = cpt_lf_register_done_irq(lf);
+	if (rc)
+		plt_err("Error registering IRQs");
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
+{
+	cpt_lf_unregister_misc_irq(lf);
+	cpt_lf_unregister_done_irq(lf);
+}
+
 int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {

@@ -146,6 +329,69 @@ cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
 	return 0;
 }
 
+static uint32_t
+cpt_lf_iq_mem_calc(uint32_t nb_desc)
+{
+	uint32_t len;
+
+	/* Space for instruction group memory */
+	len = CPT_IQ_GRP_SIZE(nb_desc);
+
+	/* Align to 128B */
+	len = PLT_ALIGN(len, ROC_ALIGN);
+
+	/* Space for FC */
+	len += CPT_IQ_FC_LEN;
+
+	/* For instruction queues */
+	len += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER *
+	       sizeof(struct cpt_inst_s);
+
+	return len;
+}
+
+static inline void
+cpt_iq_init(struct roc_cpt_lf *lf)
+{
+	union cpt_lf_q_size lf_q_size = {.u = 0x0};
+	union cpt_lf_q_base lf_q_base = {.u = 0x0};
+	union cpt_lf_inprog lf_inprog;
+	union cpt_lf_ctl lf_ctl;
+	uintptr_t addr;
+
+	lf->io_addr = lf->rbase + CPT_LF_NQX(0);
+
+	/* Disable command queue */
+	roc_cpt_iq_disable(lf);
+
+	/* Set command queue base address */
+	addr = (uintptr_t)lf->iq_vaddr +
+	       PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN);
+
+	lf_q_base.u = addr;
+
+	plt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE);
+
+	/* Set command queue size */
+	lf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc);
+	plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
+
+	/* Enable command queue execution */
+	lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
+	lf_inprog.s.eena = 1;
+	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
+
+	/* Enable instruction queue enqueuing */
+	lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
+	lf_ctl.s.ena = 1;
+	lf_ctl.s.fc_ena = 1;
+	lf_ctl.s.fc_up_crossing = 1;
+	lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;
+	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
+
+	lf->fc_addr = (uint64_t *)addr;
+}
+
 int
 roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 {

@@ -210,6 +456,63 @@ cpt_get_blkaddr(struct dev *dev)
 }
 
 int
+cpt_lf_init(struct roc_cpt_lf *lf)
+{
+	struct dev *dev = lf->dev;
+	uint64_t blkaddr;
+	void *iq_mem;
+	int rc;
+
+	if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)
+		lf->nb_desc = CPT_LF_DEFAULT_NB_DESC;
+
+	/* Allocate memory for instruction queue for CPT LF. */
+	iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);
+	if (iq_mem == NULL)
+		return -ENOMEM;
+
+	blkaddr = cpt_get_blkaddr(dev);
+	lf->rbase = dev->bar2 + ((blkaddr << 20) | (lf->lf_id << 12));
+	lf->iq_vaddr = iq_mem;
+	lf->lmt_base = dev->lmt_base;
+	lf->pf_func = dev->pf_func;
+
+	/* Initialize instruction queue */
+	cpt_iq_init(lf);
+
+	rc = cpt_lf_register_irqs(lf);
+	if (rc)
+		goto disable_iq;
+
+	return 0;
+
+disable_iq:
+	roc_cpt_iq_disable(lf);
+	plt_free(iq_mem);
+	return rc;
+}
+
+int
+roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	int rc;
+
+	lf->dev = &cpt->dev;
+	lf->roc_cpt = roc_cpt;
+	lf->msixoff = cpt->lf_msix_off[lf->lf_id];
+	lf->pci_dev = cpt->pci_dev;
+
+	rc = cpt_lf_init(lf);
+	if (rc)
+		return rc;
+
+	/* LF init successful */
+	roc_cpt->lf[lf->lf_id] = lf;
+	return rc;
+}
+
+int
 roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 {
 	struct plt_pci_device *pci_dev;

@@ -267,6 +570,29 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	return rc;
 }
 
+void
+cpt_lf_fini(struct roc_cpt_lf *lf)
+{
+	/* Unregister IRQ's */
+	cpt_lf_unregister_irqs(lf);
+
+	/* Disable IQ */
+	roc_cpt_iq_disable(lf);
+
+	/* Free memory */
+	plt_free(lf->iq_vaddr);
+	lf->iq_vaddr = NULL;
+}
+
+void
+roc_cpt_lf_fini(struct roc_cpt_lf *lf)
+{
+	if (lf == NULL)
+		return;
+	lf->roc_cpt->lf[lf->lf_id] = NULL;
+	cpt_lf_fini(lf);
+}
+
 int
 roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
 {

@@ -341,3 +667,34 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
 
 	return rsp->eng_grp_num;
 }
+
+void
+roc_cpt_iq_disable(struct roc_cpt_lf *lf)
+{
+	union cpt_lf_ctl lf_ctl = {.u = 0x0};
+	union cpt_lf_inprog lf_inprog;
+	int timeout = 20;
+
+	/* Disable instructions enqueuing */
+	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
+
+	/* Wait for instruction queue to become empty */
+	do {
+		lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
+		if (!lf_inprog.s.inflight)
+			break;
+
+		plt_delay_ms(20);
+		if (timeout-- < 0) {
+			plt_err("CPT LF %d is still busy", lf->lf_id);
+			break;
+		}
+
+	} while (1);
+
+	/* Disable executions in the LF's queue.
+	 * The queue should be empty at this point
+	 */
+	lf_inprog.s.eena = 0x0;
+	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
+}

index bae472f..e258ca5 100644
@@ -14,6 +14,23 @@
 
 #define ROC_CPT_MAX_LFS 64
 
+struct roc_cpt_lf {
+	/* Input parameters */
+	uint16_t lf_id;
+	uint32_t nb_desc;
+	/* End of Input parameters */
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	struct roc_cpt *roc_cpt;
+	uintptr_t rbase;
+	uintptr_t lmt_base;
+	uint16_t msixoff;
+	uint16_t pf_func;
+	uint64_t *fc_addr;
+	uint64_t io_addr;
+	uint8_t *iq_vaddr;
+} __plt_cache_aligned;
+
 struct roc_cpt {
 	struct plt_pci_device *pci_dev;
 	struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];

@@ -44,4 +61,7 @@ int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
 				  enum cpt_eng_type eng_type);
 int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
+void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
 #endif /* _ROC_CPT_H_ */

index 0ef6774..6cfa4df 100644
@@ -30,6 +30,8 @@ int cpt_lfs_detach(struct dev *dev);
 int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,
 		  bool inl_dev_sso);
 int cpt_lfs_free(struct dev *dev);
+int cpt_lf_init(struct roc_cpt_lf *lf);
+void cpt_lf_fini(struct roc_cpt_lf *lf);
 
 int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
 uint64_t cpt_get_blkaddr(struct dev *dev);

index 02062c1..21c7704 100644
@@ -188,6 +188,34 @@ cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
 	cpt_lf_unregister_done_irq(lf);
 }
 
+static void
+cpt_lf_dump(struct roc_cpt_lf *lf)
+{
+	plt_cpt_dbg("CPT LF");
+	plt_cpt_dbg("RBASE: 0x%016" PRIx64, lf->rbase);
+	plt_cpt_dbg("LMT_BASE: 0x%016" PRIx64, lf->lmt_base);
+	plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff);
+	plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id);
+	plt_cpt_dbg("NB DESC: %d", lf->nb_desc);
+	plt_cpt_dbg("FC_ADDR: 0x%016" PRIx64, (uintptr_t)lf->fc_addr);
+	plt_cpt_dbg("CQ.VADDR: 0x%016" PRIx64, (uintptr_t)lf->iq_vaddr);
+
+	plt_cpt_dbg("CPT LF REG:");
+	plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL,
+		    plt_read64(lf->rbase + CPT_LF_CTL));
+	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
+		    plt_read64(lf->rbase + CPT_LF_INPROG));
+
+	plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE,
+		    plt_read64(lf->rbase + CPT_LF_Q_BASE));
+	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_SIZE,
+		    plt_read64(lf->rbase + CPT_LF_Q_SIZE));
+	plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_INST_PTR,
+		    plt_read64(lf->rbase + CPT_LF_Q_INST_PTR));
+	plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_GRP_PTR,
+		    plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR));
+}
+
 int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {

@@ -484,6 +512,7 @@ cpt_lf_init(struct roc_cpt_lf *lf)
 	if (rc)
 		goto disable_iq;
 
+	cpt_lf_dump(lf);
 	return 0;
 
 disable_iq:

index e258ca5..73ecb4e 100644
@@ -63,5 +63,8 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
+
 #endif /* _ROC_CPT_H_ */

167 lines not on this page · raw message

index 21c7704..fd92de3 100644
@@ -599,6 +599,24 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	return rc;
 }
 
+int
+roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr)
+{
+	union cpt_lf_ctx_flush reg;
+
+	if (lf == NULL)
+		return -ENOTSUP;
+
+	reg.u = 0;
+	reg.s.pf_func = lf->pf_func;
+	reg.s.inval = 1;
+	reg.s.cptr = cptr;
+
+	plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH);
+
+	return 0;
+}
+
 void
 cpt_lf_fini(struct roc_cpt_lf *lf)
 {

index 73ecb4e..022c8ad 100644
@@ -63,6 +63,7 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr);
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);

index fd92de3..81e8b15 100644
@@ -217,6 +217,67 @@ cpt_lf_dump(struct roc_cpt_lf *lf)
 }
 
 int
+cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
+		uint8_t lf_id, bool ena)
+{
+	struct cpt_inline_ipsec_cfg_msg *req;
+	struct mbox *mbox = dev->mbox;
+
+	req = mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->dir = CPT_INLINE_OUTBOUND;
+	req->slot = lf_id;
+	if (ena) {
+		req->enable = 1;
+		req->sso_pf_func = sso_pf_func;
+		req->nix_pf_func = nix_pf_func;
+	} else {
+		req->enable = 0;
+	}
+
+	return mbox_process(mbox);
+}
+
+int
+roc_cpt_inline_ipsec_cfg(struct dev *cpt_dev, uint8_t lf_id,
+			 struct roc_nix *roc_nix)
+{
+	bool ena = roc_nix ? true : false;
+	uint16_t nix_pf_func = 0;
+	uint16_t sso_pf_func = 0;
+
+	if (ena) {
+		nix_pf_func = roc_nix_get_pf_func(roc_nix);
+		sso_pf_func = idev_sso_pffunc_get();
+	}
+
+	return cpt_lf_outb_cfg(cpt_dev, sso_pf_func, nix_pf_func, lf_id, ena);
+}
+
+int
+roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1,
+			     uint16_t param2)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rx_inline_lf_cfg_msg *req;
+	struct mbox *mbox;
+
+	mbox = cpt->dev.mbox;
+
+	req = mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->sso_pf_func = idev_sso_pffunc_get();
+	req->param1 = param1;
+	req->param2 = param2;
+
+	return mbox_process(mbox);
+}
+
+int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {
 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);

index 022c8ad..83ef5c7 100644
@@ -29,6 +29,7 @@ struct roc_cpt_lf {
 	uint64_t *fc_addr;
 	uint64_t io_addr;
 	uint8_t *iq_vaddr;
+	struct roc_nix *inl_outb_nix;
 } __plt_cache_aligned;
 
 struct roc_cpt {

@@ -64,6 +65,10 @@ void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
 int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr);
+int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot,
+				       struct roc_nix *nix);
+int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
+					   uint16_t param1, uint16_t param2);
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);

index 6cfa4df..0880ec0 100644
@@ -33,6 +33,8 @@ int cpt_lfs_free(struct dev *dev);
 int cpt_lf_init(struct roc_cpt_lf *lf);
 void cpt_lf_fini(struct roc_cpt_lf *lf);
 
+int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
+		    uint8_t lf_id, bool ena);
 int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
 uint64_t cpt_get_blkaddr(struct dev *dev);
 

index 88a5611..6511614 100644
@@ -109,4 +109,7 @@
 /* CPT */
 #include "roc_cpt.h"
 
+/* CPT microcode */
+#include "roc_se.h"
+
 #endif /* _ROC_API_H_ */

index 83ef5c7..cb2838e 100644
@@ -14,6 +14,40 @@
 
 #define ROC_CPT_MAX_LFS 64
 
+/* CPT helper macros */
+#define ROC_CPT_AH_HDR_LEN	 12
+#define ROC_CPT_AES_GCM_IV_LEN	 8
+#define ROC_CPT_AES_GCM_MAC_LEN	 16
+#define ROC_CPT_AES_CBC_IV_LEN	 16
+#define ROC_CPT_SHA1_HMAC_LEN	 12
+#define ROC_CPT_AUTH_KEY_LEN_MAX 64
+
+#define ROC_CPT_DES3_KEY_LEN	  24
+#define ROC_CPT_AES128_KEY_LEN	  16
+#define ROC_CPT_AES192_KEY_LEN	  24
+#define ROC_CPT_AES256_KEY_LEN	  32
+#define ROC_CPT_MD5_KEY_LENGTH	  16
+#define ROC_CPT_SHA1_KEY_LENGTH	  20
+#define ROC_CPT_SHA256_KEY_LENGTH 32
+#define ROC_CPT_SHA384_KEY_LENGTH 48
+#define ROC_CPT_SHA512_KEY_LENGTH 64
+#define ROC_CPT_AUTH_KEY_LEN_MAX  64
+
+#define ROC_CPT_DES_BLOCK_LENGTH 8
+#define ROC_CPT_AES_BLOCK_LENGTH 16
+
+#define ROC_CPT_AES_GCM_ROUNDUP_BYTE_LEN 4
+#define ROC_CPT_AES_CBC_ROUNDUP_BYTE_LEN 16
+
+/* Salt length for AES-CTR/GCM/CCM and AES-GMAC */
+#define ROC_CPT_SALT_LEN 4
+
+#define ROC_CPT_ESP_HDR_LEN	    8
+#define ROC_CPT_ESP_TRL_LEN	    2
+#define ROC_CPT_AH_HDR_LEN	    12
+#define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
+#define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
+
 struct roc_cpt_lf {
 	/* Input parameters */
 	uint16_t lf_id;

267 lines not on this page · raw message

index 6511614..d545bb9 100644
@@ -110,6 +110,8 @@
 #include "roc_cpt.h"
 
 /* CPT microcode */
+#include "roc_ie_on.h"
+#include "roc_ie_ot.h"
 #include "roc_se.h"
 
 #endif /* _ROC_API_H_ */

new file mode 100644
index 0000000..a330ea1
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_H__
+#define __ROC_IE_H__
+
+/* CNXK IPSEC helper macros */
+#define ROC_IE_AH_HDR_LEN      12
+#define ROC_IE_AES_GCM_IV_LEN  8
+#define ROC_IE_AES_GCM_MAC_LEN 16
+#define ROC_IE_AES_CBC_IV_LEN  16
+#define ROC_IE_SHA1_HMAC_LEN   12
+#define ROC_IE_AUTH_KEY_LEN_MAX 64
+
+#define ROC_IE_AES_GCM_ROUNDUP_BYTE_LEN 4
+#define ROC_IE_AES_CBC_ROUNDUP_BYTE_LEN 16
+
+#endif /* __ROC_IE_H__ */

152 lines not on this page · raw message

534 lines not on this page · raw message

index daee100..685ec29 100644
@@ -49,6 +49,7 @@
 #define PLT_MODEL_MZ_NAME	 "roc_model_mz"
 #define PLT_CACHE_LINE_SIZE      RTE_CACHE_LINE_SIZE
 #define BITMASK_ULL		 GENMASK_ULL
+#define PLT_ALIGN_CEIL		 RTE_ALIGN_CEIL
 
 /** Divide ceil */
 #define PLT_DIV_CEIL(x, y)			\

new file mode 100644
index 0000000..c549e18
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_AE_H__
+#define __ROC_AE_H__
+
+/* AE opcodes */
+#define ROC_AE_MAJOR_OP_MODEX	     0x03
+#define ROC_AE_MAJOR_OP_ECDSA	     0x04
+#define ROC_AE_MAJOR_OP_ECC	     0x05
+#define ROC_AE_MINOR_OP_MODEX	     0x01
+#define ROC_AE_MINOR_OP_PKCS_ENC     0x02
+#define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03
+#define ROC_AE_MINOR_OP_PKCS_DEC     0x04
+#define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05
+#define ROC_AE_MINOR_OP_MODEX_CRT    0x06
+#define ROC_AE_MINOR_OP_ECDSA_SIGN   0x01
+#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02
+#define ROC_AE_MINOR_OP_ECC_UMP	     0x03
+
+/**
+ * Enumeration roc_ae_ec_id
+ *
+ * Enumerates supported elliptic curves
+ */
+typedef enum {
+	ROC_AE_EC_ID_P192 = 0,
+	ROC_AE_EC_ID_P224 = 1,
+	ROC_AE_EC_ID_P256 = 2,
+	ROC_AE_EC_ID_P384 = 3,
+	ROC_AE_EC_ID_P521 = 4,
+	ROC_AE_EC_ID_PMAX = 5
+} roc_ae_ec_id;
+
+/* Prime and order fields of built-in elliptic curves */
+struct roc_ae_ec_group {
+	struct {
+		/* P521 maximum length */
+		uint8_t data[66];
+		unsigned int length;
+	} prime;
+
+	struct {
+		/* P521 maximum length */
+		uint8_t data[66];
+		unsigned int length;
+	} order;
+};
+
+struct roc_ae_ec_ctx {
+	/* Prime length defined by microcode for EC operations */
+	uint8_t curveid;
+};
+
+#endif /* __ROC_AE_H__ */

index d545bb9..546818d 100644
@@ -110,6 +110,7 @@
 #include "roc_cpt.h"
 
 /* CPT microcode */
+#include "roc_ae.h"
 #include "roc_ie_on.h"
 #include "roc_ie_ot.h"
 #include "roc_se.h"

index cb2838e..5577fea 100644
@@ -7,6 +7,9 @@
 
 #include "roc_api.h"
 
+#define ROC_AE_CPT_BLOCK_TYPE1 0
+#define ROC_AE_CPT_BLOCK_TYPE2 1
+
 /* Default engine groups */
 #define ROC_CPT_DFLT_ENG_GRP_SE	   0UL
 #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL

index 81e8b15..788b28a 100644
@@ -806,3 +806,23 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf)
 	lf_inprog.s.eena = 0x0;
 	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
 }
+
+int
+roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline,
+		     int lf_id)
+{
+	struct roc_cpt_lf *lf;
+
+	lf = roc_cpt->lf[lf_id];
+	if (lf == NULL)
+		return -ENOTSUP;
+
+	lmtline->io_addr = lf->io_addr;
+	if (roc_model_is_cn10k())
+		lmtline->io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4;
+
+	lmtline->fc_addr = lf->fc_addr;
+	lmtline->lmt_base = lf->lmt_base;
+
+	return 0;
+}

index 5577fea..8dd2b5e 100644
@@ -16,6 +16,30 @@
 #define ROC_CPT_DFLT_ENG_GRP_AE	   2UL
 
 #define ROC_CPT_MAX_LFS 64
+#define ROC_CN10K_CPT_INST_DW_M1                                               \
+	((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7))
+#define ROC_CN10K_TWO_CPT_INST_DW_M1                                           \
+	((uint64_t)(((sizeof(struct cpt_inst_s) * 2 / 16) - 1) & 0x7))
+
+/* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of
+ * APT_LMT_ARG_S
+ */
+#define ROC_CN10K_CPT_LMT_ARG                                                  \
+	(ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14))
 
 /* CPT helper macros */
 #define ROC_CPT_AH_HDR_LEN	 12

@@ -51,6 +75,12 @@
 #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
 
+struct roc_cpt_lmtline {
+	uint64_t io_addr;
+	uint64_t *fc_addr;
+	uintptr_t lmt_base;
+};
+
 struct roc_cpt_lf {
 	/* Input parameters */
 	uint16_t lf_id;

@@ -109,5 +139,7 @@ int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt,
+				   struct roc_cpt_lmtline *lmtline, int lf_id);
 
 #endif /* _ROC_CPT_H_ */

1,140 lines not on this page · raw message

new file mode 100644
index 0000000..1cc5b02
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_AE_FPM_TABLES_H_
+#define _ROC_AE_FPM_TABLES_H_
+
+#include "roc_api.h"
+
+int __roc_api roc_ae_fpm_get(uint64_t *tbl);
+void __roc_api roc_ae_fpm_put(void);
+
+#endif /* _ROC_AE_FPM_TABLES_H_ */

index 546818d..37c151e 100644
@@ -111,6 +111,7 @@
 
 /* CPT microcode */
 #include "roc_ae.h"
+#include "roc_ae_fpm_tables.h"
 #include "roc_ie_on.h"
 #include "roc_ie_ot.h"
 #include "roc_se.h"

142 lines not on this page · raw message

index c549e18..5072cc5 100644
@@ -53,4 +53,11 @@ struct roc_ae_ec_ctx {
 	uint8_t curveid;
 };
 
+/* Buffer pointer */
+struct roc_ae_buf_ptr {
+	void *vaddr;
+};
+
+int __roc_api roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl);
+void __roc_api roc_ae_ec_grp_put(void);
 #endif /* __ROC_AE_H__ */

new file mode 100644
index 0000000..17889bb
@@ -0,0 +1,468 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "cnxk_security.h"
+
+static int
+ot_ipsec_sa_common_param_fill(union roc_ot_ipsec_sa_word2 *w2,
+			      uint8_t *cipher_key, uint8_t *salt_key,
+			      struct rte_security_ipsec_xform *ipsec_xfrm,
+			      struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	const uint8_t *key;
+	uint32_t *tmp_salt;
+	uint64_t *tmp_key;
+	int length, i;
+
+	/* Set direction */
+	switch (ipsec_xfrm->direction) {
+	case RTE_SECURITY_IPSEC_SA_DIR_INGRESS:
+		w2->s.dir = ROC_IE_OT_SA_DIR_INBOUND;
+		break;
+	case RTE_SECURITY_IPSEC_SA_DIR_EGRESS:
+		w2->s.dir = ROC_IE_OT_SA_DIR_OUTBOUND;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set protocol - ESP vs AH */
+	switch (ipsec_xfrm->proto) {
+	case RTE_SECURITY_IPSEC_SA_PROTO_ESP:
+		w2->s.protocol = ROC_IE_OT_SA_PROTOCOL_ESP;
+		break;
+	case RTE_SECURITY_IPSEC_SA_PROTO_AH:
+		w2->s.protocol = ROC_IE_OT_SA_PROTOCOL_AH;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set mode - transport vs tunnel */
+	switch (ipsec_xfrm->mode) {
+	case RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT:
+		w2->s.mode = ROC_IE_OT_SA_MODE_TRANSPORT;
+		break;
+	case RTE_SECURITY_IPSEC_SA_MODE_TUNNEL:
+		w2->s.mode = ROC_IE_OT_SA_MODE_TUNNEL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set encryption algorithm */
+	if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+		key = crypto_xfrm->aead.key.data;
+		length = crypto_xfrm->aead.key.length;
+
+		switch (crypto_xfrm->aead.algo) {
+		case RTE_CRYPTO_AEAD_AES_GCM:
+			w2->s.enc_type = ROC_IE_OT_SA_ENC_AES_GCM;
+			w2->s.auth_type = ROC_IE_OT_SA_AUTH_NULL;
+			memcpy(salt_key, &ipsec_xfrm->salt, 4);
+			tmp_salt = (uint32_t *)salt_key;
+			*tmp_salt = rte_be_to_cpu_32(*tmp_salt);
+			break;
+		default:
+			return -ENOTSUP;
+		}
+	} else {
+		return -ENOTSUP;
+	}
+
+	w2->s.spi = ipsec_xfrm->spi;
+
+	/* Copy encryption key */
+	memcpy(cipher_key, key, length);
+	tmp_key = (uint64_t *)cipher_key;
+	for (i = 0; i < (int)(ROC_CTX_MAX_CKEY_LEN / sizeof(uint64_t)); i++)
+		tmp_key[i] = rte_be_to_cpu_64(tmp_key[i]);
+
+	switch (length) {
+	case ROC_CPT_AES128_KEY_LEN:
+		w2->s.aes_key_len = ROC_IE_OT_SA_AES_KEY_LEN_128;
+		break;
+	case ROC_CPT_AES192_KEY_LEN:
+		w2->s.aes_key_len = ROC_IE_OT_SA_AES_KEY_LEN_192;
+		break;
+	case ROC_CPT_AES256_KEY_LEN:
+		w2->s.aes_key_len = ROC_IE_OT_SA_AES_KEY_LEN_256;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static size_t
+ot_ipsec_inb_ctx_size(struct roc_ot_ipsec_inb_sa *sa)
+{
+	size_t size;
+
+	/* Variable based on Anti-replay Window */
+	size = offsetof(struct roc_ot_ipsec_inb_sa, ctx) +
+	       offsetof(struct roc_ot_ipsec_inb_ctx_update_reg, ar_winbits);
+
+	if (sa->w0.s.ar_win)
+		size += (1 << (sa->w0.s.ar_win - 1)) * sizeof(uint64_t);
+
+	return size;
+}
+
+int
+cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
+			  struct rte_security_ipsec_xform *ipsec_xfrm,
+			  struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	union roc_ot_ipsec_sa_word2 w2;
+	uint32_t replay_win_sz;
+	size_t offset;
+	int rc;
+
+	w2.u64 = 0;
+	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
+					   ipsec_xfrm, crypto_xfrm);
+	if (rc)
+		return rc;
+
+	/* Updata common word2 data */
+	sa->w2.u64 = w2.u64;
+
+	/* Only support power-of-two window sizes supported */
+	replay_win_sz = ipsec_xfrm->replay_win_sz;
+	if (replay_win_sz) {
+		if (!rte_is_power_of_2(replay_win_sz) ||
+		    replay_win_sz > ROC_AR_WIN_SIZE_MAX)
+			return -ENOTSUP;
+
+		sa->w0.s.ar_win = rte_log2_u32(replay_win_sz) - 5;
+	}
+
+	/* Default options for pkt_out and pkt_fmt are with
+	 * second pass meta and no defrag.
+	 */
+	sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
+	sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
+	sa->w0.s.pkind = ROC_OT_CPT_META_PKIND;
+
+	/* ESN */
+	sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
+
+	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
+	/* Word offset for HW managed SA field */
+	sa->w0.s.hw_ctx_off = offset / 8;
+	/* Context push size for inbound spans up to hw_ctx including
+	 * ar_base field, in 8b units
+	 */
+	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+	/* Entire context size in 128B units */
+	sa->w0.s.ctx_size =
+		(PLT_ALIGN_CEIL(ot_ipsec_inb_ctx_size(sa), ROC_CTX_UNIT_128B) /
+		 ROC_CTX_UNIT_128B) -
+		1;
+
+	/* There are two words of CPT_CTX_HW_S for ucode to skip */
+	sa->w0.s.ctx_hdr_size = 1;
+	sa->w0.s.aop_valid = 1;
+
+	rte_wmb();
+
+	/* Enable SA */
+	sa->w2.s.valid = 1;
+	return 0;
+}
+
+int
+cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
+			   struct rte_security_ipsec_xform *ipsec_xfrm,
+			   struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	struct rte_security_ipsec_tunnel_param *tunnel = &ipsec_xfrm->tunnel;
+	union roc_ot_ipsec_sa_word2 w2;
+	size_t offset;
+	int rc;
+
+	w2.u64 = 0;
+	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->iv.s.salt,
+					   ipsec_xfrm, crypto_xfrm);
+	if (rc)
+		return rc;
+
+	/* Update common word2 data */
+	sa->w2.u64 = w2.u64;
+
+	if (ipsec_xfrm->mode != RTE_SECURITY_IPSEC_SA_MODE_TUNNEL)
+		goto skip_tunnel_info;
+
+	/* Tunnel header info */
+	switch (tunnel->type) {
+	case RTE_SECURITY_IPSEC_TUNNEL_IPV4:
+		sa->w2.s.outer_ip_ver = ROC_IE_OT_SA_IP_VERSION_4;
+		memcpy(&sa->outer_hdr.ipv4.src_addr, &tunnel->ipv4.src_ip,
+		       sizeof(struct in_addr));
+		memcpy(&sa->outer_hdr.ipv4.dst_addr, &tunnel->ipv4.dst_ip,
+		       sizeof(struct in_addr));
+
+		/* IP Source and Dest seems to be in LE/CPU endian */
+		sa->outer_hdr.ipv4.src_addr =
+			rte_be_to_cpu_32(sa->outer_hdr.ipv4.src_addr);
+		sa->outer_hdr.ipv4.dst_addr =
+			rte_be_to_cpu_32(sa->outer_hdr.ipv4.dst_addr);
+
+		/* Outer header DF bit source */
+		if (!ipsec_xfrm->options.copy_df) {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_SA;
+			sa->w10.s.ipv4_df_or_ipv6_flw_lbl = tunnel->ipv4.df;
+		} else {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+
+		/* Outer header DSCP source */
+		if (!ipsec_xfrm->options.copy_dscp) {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_SA;
+			sa->w10.s.dscp = tunnel->ipv4.dscp;
+		} else {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+		break;
+	case RTE_SECURITY_IPSEC_TUNNEL_IPV6:
+		sa->w2.s.outer_ip_ver = ROC_IE_OT_SA_IP_VERSION_6;
+		memcpy(&sa->outer_hdr.ipv6.src_addr, &tunnel->ipv6.src_addr,
+		       sizeof(struct in6_addr));
+		memcpy(&sa->outer_hdr.ipv6.dst_addr, &tunnel->ipv6.dst_addr,
+		       sizeof(struct in6_addr));
+
+		/* Outer header flow label source */
+		if (!ipsec_xfrm->options.copy_flabel) {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_SA;
+
+			sa->w10.s.ipv4_df_or_ipv6_flw_lbl = tunnel->ipv6.flabel;
+		} else {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+
+		/* Outer header DSCP source */
+		if (!ipsec_xfrm->options.copy_dscp) {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_SA;
+			sa->w10.s.dscp = tunnel->ipv6.dscp;
+		} else {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Default options of DSCP and Flow label/DF */
+	sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_SA;
+	sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src = ROC_IE_OT_SA_COPY_FROM_SA;
+
+skip_tunnel_info:
+	/* ESN */
+	sa->w0.s.esn_en = !!ipsec_xfrm->options.esn;
+
+	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
+	/* Word offset for HW managed SA field */
+	sa->w0.s.hw_ctx_off = offset / 8;
+	/* Context push size is up to hmac_opad_ipad */
+	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off;
+	/* Entire context size in 128B units */
+	offset = sizeof(struct roc_ot_ipsec_outb_sa);
+	sa->w0.s.ctx_size = (PLT_ALIGN_CEIL(offset, ROC_CTX_UNIT_128B) /
+			     ROC_CTX_UNIT_128B) -
+			    1;
+
+	/* IPID gen */
+	sa->w2.s.ipid_gen = 1;
+
+	/* There are two words of CPT_CTX_HW_S for ucode to skip */
+	sa->w0.s.ctx_hdr_size = 1;
+	sa->w0.s.aop_valid = 1;
+
+	rte_wmb();
+
+	/* Enable SA */
+	sa->w2.s.valid = 1;
+	return 0;
+}
+
+bool
+cnxk_ot_ipsec_inb_sa_valid(struct roc_ot_ipsec_inb_sa *sa)
+{
+	return !!sa->w2.s.valid;
+}
+
+bool
+cnxk_ot_ipsec_outb_sa_valid(struct roc_ot_ipsec_outb_sa *sa)
+{
+	return !!sa->w2.s.valid;
+}
+
+uint8_t
+cnxk_ipsec_ivlen_get(enum rte_crypto_cipher_algorithm c_algo,
+		     enum rte_crypto_auth_algorithm a_algo,
+		     enum rte_crypto_aead_algorithm aead_algo)
+{
+	uint8_t ivlen = 0;
+
+	if (aead_algo == RTE_CRYPTO_AEAD_AES_GCM)
+		ivlen = 8;
+
+	switch (c_algo) {
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		ivlen = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		ivlen = ROC_CPT_DES_BLOCK_LENGTH;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		ivlen = ROC_CPT_AES_BLOCK_LENGTH;
+		break;
+	default:
+		break;
+	}
+
+	switch (a_algo) {
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		ivlen = 8;
+		break;
+	default:
+		break;
+	}
+
+	return ivlen;
+}
+
+uint8_t
+cnxk_ipsec_icvlen_get(enum rte_crypto_cipher_algorithm c_algo,
+		      enum rte_crypto_auth_algorithm a_algo,
+		      enum rte_crypto_aead_algorithm aead_algo)
+{
+	uint8_t icv = 0;
+
+	(void)c_algo;
+
+	switch (a_algo) {
+	case RTE_CRYPTO_AUTH_NULL:
+		icv = 0;
+		break;
+	case RTE_CRYPTO_AUTH_SHA1:
+		icv = 12;
+		break;
+	case RTE_CRYPTO_AUTH_SHA256:
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		icv = 16;
+		break;
+	case RTE_CRYPTO_AUTH_SHA384:
+		icv = 24;
+		break;
+	case RTE_CRYPTO_AUTH_SHA512:
+		icv = 32;
+		break;
+	default:
+		break;
+	}
+
+	switch (aead_algo) {
+	case RTE_CRYPTO_AEAD_AES_GCM:
+		icv = 16;
+		break;
+	default:
+		break;
+	}
+
+	return icv;
+}
+
+uint8_t
+cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm c_algo,
+			     enum rte_crypto_aead_algorithm aead_algo)
+{
+	uint8_t roundup_byte = 4;
+
+	if (aead_algo == RTE_CRYPTO_AEAD_AES_GCM)
+		return roundup_byte;
+
+	switch (c_algo) {
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		roundup_byte = 4;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		roundup_byte = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		roundup_byte = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_NULL:
+		roundup_byte = 4;
+		break;
+	default:
+		break;
+	}
+
+	return roundup_byte;
+}
+
+int
+cnxk_ipsec_outb_rlens_get(struct cnxk_ipsec_outb_rlens *rlens,
+			  struct rte_security_ipsec_xform *ipsec_xfrm,
+			  struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	struct rte_security_ipsec_tunnel_param *tunnel = &ipsec_xfrm->tunnel;
+	enum rte_crypto_cipher_algorithm c_algo = RTE_CRYPTO_CIPHER_NULL;
+	enum rte_crypto_auth_algorithm a_algo = RTE_CRYPTO_AUTH_NULL;
+	enum rte_crypto_aead_algorithm aead_algo = 0;
+	uint16_t partial_len = 0;
+	uint8_t roundup_byte = 0;
+	int8_t roundup_len = 0;
+
+	memset(rlens, 0, sizeof(struct cnxk_ipsec_outb_rlens));
+
+	/* Get Cipher and Auth algo */
+	if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+		aead_algo = crypto_xfrm->aead.algo;
+	} else {
+		if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
+			c_algo = crypto_xfrm->cipher.algo;
+		else
+			a_algo = crypto_xfrm->auth.algo;
+
+		if (crypto_xfrm->next) {
+			if (crypto_xfrm->next->type ==
+			    RTE_CRYPTO_SYM_XFORM_CIPHER)
+				c_algo = crypto_xfrm->next->cipher.algo;
+			else
+				a_algo = crypto_xfrm->next->auth.algo;
+		}
+	}
+
+	if (ipsec_xfrm->proto == RTE_SECURITY_IPSEC_SA_PROTO_ESP) {
+		partial_len = ROC_CPT_ESP_HDR_LEN;
+		roundup_len = ROC_CPT_ESP_TRL_LEN;
+	} else {
+		partial_len = ROC_CPT_AH_HDR_LEN;
+	}
+
+	if (ipsec_xfrm->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {
+		if (tunnel->type == RTE_SECURITY_IPSEC_TUNNEL_IPV4)
+			partial_len += ROC_CPT_TUNNEL_IPV4_HDR_LEN;
+		else
+			partial_len += ROC_CPT_TUNNEL_IPV6_HDR_LEN;
+	}
+
+	partial_len += cnxk_ipsec_ivlen_get(c_algo, a_algo, aead_algo);
+	partial_len += cnxk_ipsec_icvlen_get(c_algo, a_algo, aead_algo);
+	roundup_byte = cnxk_ipsec_outb_roundup_byte(c_algo, aead_algo);
+
+	rlens->partial_len = partial_len;
+	rlens->roundup_len = roundup_len;
+	rlens->roundup_byte = roundup_byte;
+	rlens->max_extended_len = partial_len + roundup_len + roundup_byte;
+	return 0;
+}

49 lines not on this page · raw message

342 lines not on this page · raw message

index ffae065..43a40dd 100644
@@ -264,4 +264,12 @@ struct roc_se_ctx {
 	uint8_t auth_key[1024];
 };
 
+int __roc_api roc_se_auth_key_set(struct roc_se_ctx *se_ctx,
+				  roc_se_auth_type type, const uint8_t *key,
+				  uint16_t key_len, uint16_t mac_len);
+
+int __roc_api roc_se_ciph_key_set(struct roc_se_ctx *se_ctx,
+				  roc_se_cipher_type type, const uint8_t *key,
+				  uint16_t key_len, uint8_t *salt);
+
 #endif /* __ROC_SE_H__ */