ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue
cover ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue
From: Prasanna Kumar <[email protected]>
Hello all,
This patch set is for "for-next" branch.
In this patch set, the first patch adds device tree support for G-Scaler and MFC power domains of Exynos5.
The second patch enables power domain support for exynos5 in Kconfig
The last patch provides a software fix for hardware issue found in exynos5 while powergating the power domains.
Prasanna Kumar (3):
ARM: dts: exynos5: Set up power domain for MFC and G-scaler
arm: exynos5: Enable PM generic domain support in Kconfig
ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++ arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 3 files changed, 43 insertions(+), 0 deletions(-)
PATCH 1/3 ARM: dts: exynos5: Set up power domain for MFC and G-scaler
From: Prasanna Kumar <[email protected]>
This patch adds device tree nodes for MFC and G-scaler power domains of exynos5. It binds these power-domain nodes to repsective device tree nodes.
--- arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-)
arch/arm/boot/dts/exynos5250.dtsi +15 -0
@@ -83,6 +83,7 @@ compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; + samsung,power-domain = <&pd_mfc>; }; rtc {
@@ -578,28 +579,42 @@ }; }; + pd_gsc: gsc-power-domain@0x10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + }; + + pd_mfc: mfc-power-domain@0x10044040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044040 0x20>; + }; + gsc_0: gsc@0x13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_1: gsc@0x13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_2: gsc@0x13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_3: gsc@0x13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; + samsung,power-domain = <&pd_gsc>; }; hdmi {
Signature · 1 line
1.7.0.4
PATCH 1/3 ARM: dts: exynos5: Set up power domain for MFC and G-scaler
Quoted 6 lines · Prasanna Kumar
From: Prasanna Kumar <[email protected]>
This patch adds device tree nodes for MFC and G-scaler power domains of exynos5. It binds these power-domain nodes to repsective device tree nodes.
Signed-off-by Prasanna Kumar <[email protected]>
Quoted 66 lines
--- arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-)arch/arm/boot/dts/exynos5250.dtsi +15
-1@@ -83,6 +83,7 @@ compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; + samsung,power-domain = <&pd_mfc>; }; rtc {@@ -578,28 +579,42 @@ }; }; + pd_gsc: gsc-power-domain at 0x10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + }; + + pd_mfc: mfc-power-domain at 0x10044040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044040 0x20>; + }; + gsc_0: gsc at 0x13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_1: gsc at 0x13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_2: gsc at 0x13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_3: gsc at 0x13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; + samsung,power-domain = <&pd_gsc>; }; hdmi { --1.7.0.4
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PATCH 2/3 arm: exynos5: Enable PM generic domain support in Kconfig
In reply to Prasanna KumarFrom: Prasanna Kumar <[email protected]>
This patch adds support to enable PM generic domains under Exynos5 family
--- arch/arm/mach-exynos/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/Kconfig +1 -0
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250 depends on ARCH_EXYNOS5 select S5P_PM if PM select S5P_SLEEP if PM + select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC select SAMSUNG_DMADEV help
Signature · 1 line
1.7.0.4
PATCH 2/3 arm: exynos5: Enable PM generic domain support in Kconfig
Quoted 6 lines · Prasanna Kumar
From: Prasanna Kumar <[email protected]>
This patch adds support to enable PM generic domains under Exynos5 family
Signed-off-by Prasanna Kumar <[email protected]>
Quoted 23 lines
--- arch/arm/mach-exynos/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)arch/arm/mach-exynos/Kconfig +1
-1@@ -63,6 +63,7 @@ config SOC_EXYNOS5250 depends on ARCH_EXYNOS5 select S5P_PM if PM select S5P_SLEEP if PM + select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC select SAMSUNG_DMADEV help --1.7.0.4
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PATCH 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
In reply to Prasanna KumarFrom: Prasanna Kumar <[email protected]>
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that CLK_TOP_SRC3 register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.
The value of clock source register is restored once the powergating operation is completed.
--- arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/pm_domains.c +27 -0
@@ -24,6 +24,8 @@#include <mach/regs-pmu.h> #include <plat/devs.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> /* * Exynos specific wrapper around the generic power domain
@@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)void __iomem *base;u32 timeout, pwr;char *op; +u32 tmp =0 ; pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base;
@@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) pwr = power_on ?S5P_INT_LOCAL_PWR_EN :0 ;__raw_writel (pwr, base); +/* +*It is found that the CLK SRC register in exynos5 +*gets modified when power domain of gsc/mfc/isp/disp1 +*is powered off.This happens only after the system is +*suspended and resumed and not before that. +*The following fix adresses this hardware issue. +*It saves the value of clock source register and +*resores it later +*/ + +if (soc_is_exynos5250 ()) { +if (!power_on) { +/* save clock source register */ + tmp =__raw_readl (EXYNOS5_CLKSRC_TOP3 ); + } + } +/* Wait max 1ms */ timeout =10 ;
@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)cpu_relax ();usleep_range (80 ,100 ); } + +if (soc_is_exynos5250 ()) { +if (!power_on) { +/* restore clock source register */ +__raw_writel (tmp,EXYNOS5_CLKSRC_TOP3 ); + } + }return 0 ; }
Signature · 1 line
1.7.0.4
PATCH 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Quoted 50 lines · Prasanna Kumar
From: Prasanna Kumar <[email protected]>
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Signed-off-by Prasanna Kumar <[email protected]>--- arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)arch/arm/mach-exynos/pm_domains.c +9
-0@@ -24,6 +24,8 @@#include <mach/regs-pmu.h> #include <plat/devs.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> /* * Exynos specific wrapper around the generic power domain @@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)void __iomem *base;u32 timeout, pwr;char *op; +u32 tmp =0 ; pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base;@@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) pwr = power_on ?S5P_INT_LOCAL_PWR_EN :0 ;__raw_writel (pwr, base); +/* +*It is found that the CLK SRC register in exynos5 +*gets modified when power domain of gsc/mfc/isp/disp1 +*is powered off.This happens only after the system is +*suspended and resumed and not before that. +*The following fix adresses this hardware issue.
arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) · line 69
Quoted 10 lines
arch/arm/mach-exynos/pm_domains.c +10
-0+*It saves the value of clock source register and +*resores it later +*/ + +if (soc_is_exynos5250 ()) { +if (!power_on) { +/* save clock source register */ + tmp =__raw_readl (EXYNOS5_CLKSRC_TOP3 ); + } + }
Does the value of EXYNOS5_CLKSRC_TOP3 register change as soon as the G-Scaler/MFC devices are power gated?
- If yes, the value of CLKSRC register should be saved before the power domain register is programmed.
- If not, as mentioned in the comment, if this issue occurs during a suspend-resume cycle, the value of this register can be saved and restored in the clock driver code itself.
The other thing that needs to be relooked into here is the use of EXYNOS5_CLKSRC_TOP3 register address. Currently, the clock registers are statically io-remapped. With the upcoming migration to common clock for Exynos5, the clock registers will not be statically io-remapped but instead remapped during clock initialization. So the use of EXYNOS5_CLKSRC_TOP3 will not hold and so we need to relook into this.
arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) · line 85
Quoted 10 lines
arch/arm/mach-exynos/pm_domains.c +3
-0+/* Wait max 1ms */ timeout =10 ;@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)cpu_relax ();usleep_range (80 ,100 ); } + +if (soc_is_exynos5250 ()) {
We could use the of_machine_is_compatible api here instead of soc_is_exynos5250() macro.
arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) · line 92
Quoted 7 lines
arch/arm/mach-exynos/pm_domains.c +5
-0+if (!power_on) { +/* restore clock source register */ +__raw_writel (tmp,EXYNOS5_CLKSRC_TOP3 ); + } + }return 0 ; }
Thanks,
Thomas.
PATCH 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Thomas,
Thanks for the comments.Please find my reply inline.
Quoted 51 lines · Thomas Abraham
Quoted 35 lines · Prasanna Kumar
From: Prasanna Kumar <[email protected]>
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Signed-off-by Prasanna Kumar <[email protected]>--- arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)arch/arm/mach-exynos/pm_domains.c +6
-0@@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) pwr = power_on ?S5P_INT_LOCAL_PWR_EN :0 ;__raw_writel (pwr, base); +/* +*It is found that the CLK SRC register in exynos5 +*gets modified when power domain of gsc/mfc/isp/disp1 +*is powered off.This happens only after the system is +*suspended and resumed and not before that. +*The following fix adresses this hardware issue. arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain · line 70
Quoted 10 lines
arch/arm/mach-exynos/pm_domains.c +10
-0+*It saves the value of clock source register and +*resores it later +*/ + +if (soc_is_exynos5250 ()) { +if (!power_on) { +/* save clock source register */ + tmp =__raw_readl (EXYNOS5_CLKSRC_TOP3 ); + } + }Does the value of
EXYNOS5_CLKSRC_TOP3register change as soon as the G-Scaler/MFC devices are power gated?
Quoted 7 lines
- If yes, the value of CLKSRC register should be saved before the power domain register is programmed.
- If not, as mentioned in the comment, if this issue occurs during a suspend-resume cycle, the value of this register can be saved and restored in the clock driver code itself.
During a normal power gating sequence, this problem is not seen But Once the suspend-resume cycle is done, if we try to turn on or turn off domain,
this issue occurs.
I agree that CLKSRC register should be saved
before the power domain register is programmed.
Saving of CLKSRC_TOP3 register is already being done in clock driver code.i.e in exynos5_clock_save[]. But the problem remains. So i feel an exclusive saving of the register in pm_domain driver is required.
Kindly let me know your opinion
Quoted 7 lines
The other thing that needs to be relooked into here is the use of
EXYNOS5_CLKSRC_TOP3register address. Currently, the clock registers are statically io-remapped. With the upcoming migration to common clock for Exynos5, the clock registers will not be statically io-remapped but instead remapped during clock initialization. So the use ofEXYNOS5_CLKSRC_TOP3will not hold and so we need to relook into this.
Yes , we can look into this, once the clock migration happens for Exynos5 Until then, can it be used as statically io-remapped ?
Quoted 11 lines
arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain · line 86
Quoted 7 lines
arch/arm/mach-exynos/pm_domains.c +2
-0@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)cpu_relax ();usleep_range (80 ,100 ); } + +if (soc_is_exynos5250 ()) {We could use the
of_machine_is_compatibleapi here instead ofsoc_is_exynos5250()macro.
Yes, of_machine_is_compatible function will be used instead of soc_is_exynos5250()
Quoted 4 lines
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Thanks
Prasanna Kumar
v2 cover ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue
Hello,
This patch set is for "for-next" branch.
Changes since v1:
[exynos5250.dtsi]
Added power domain support for MAU and ISP power domains in exynos5 dts [pm_domains.c]
CLKSRC register is saved before PMU register is programmed Replaced soc_is_exynos5250 with of_machine_is_compatible
Prasanna Kumar (3):
ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP
arm: exynos5: Enable PM generic domain support in Kconfig
ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
arch/arm/boot/dts/exynos5250.dtsi | 25 +++++++++++++++++++++++++ arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 0 deletions(-)
PATCH v2 1/3 ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP
In reply to Prasanna KumarThis patch adds device tree nodes for MFC,G-scaler,MAU and ISP power domains of exynos5.It binds these power-domain nodes to repsective device tree nodes.
--- arch/arm/boot/dts/exynos5250.dtsi | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-)
arch/arm/boot/dts/exynos5250.dtsi +25 -0
@@ -83,6 +83,7 @@ compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; + samsung,power-domain = <&pd_mfc>; }; rtc {
@@ -283,6 +284,7 @@ samsung,supports-rstclr; samsung,supports-secdai; samsung,idma-addr = <0x03000000>; + samsung,power-domain = <&pd_mau>; }; i2s_1: i2s@12D60000 {
@@ -578,28 +580,51 @@ }; }; + pd_gsc: gsc-power-domain@0x10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + }; + + pd_isp: isp-power-domain@0x10044020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044020 0x20>; + }; + + pd_mfc: mfc-power-domain@0x10044040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044040 0x20>; + }; + + pd_mau: mau-power-domain@0x100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + }; gsc_0: gsc@0x13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_1: gsc@0x13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_2: gsc@0x13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_3: gsc@0x13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; + samsung,power-domain = <&pd_gsc>; }; hdmi {
Signature · 1 line
1.7.0.4
PATCH v2 1/3 ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP
Hi all,
Any comments on this patch ?
Thanks,
Prasanna
Quoted 88 lines · Prasanna Kumar
This patch adds device tree nodes for MFC,G-scaler,MAU and ISP power domains of exynos5.It binds these power-domain nodes to repsective device tree nodes.
Signed-off-by Prasanna Kumar <[email protected]>--- arch/arm/boot/dts/exynos5250.dtsi | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-)arch/arm/boot/dts/exynos5250.dtsi +25
-1@@ -83,6 +83,7 @@ compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; + samsung,power-domain = <&pd_mfc>; }; rtc {@@ -283,6 +284,7 @@ samsung,supports-rstclr; samsung,supports-secdai; samsung,idma-addr = <0x03000000>; + samsung,power-domain = <&pd_mau>; }; i2s_1: i2s at 12D60000 {@@ -578,28 +580,51 @@ }; }; + pd_gsc: gsc-power-domain at 0x10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + }; + + pd_isp: isp-power-domain at 0x10044020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044020 0x20>; + }; + + pd_mfc: mfc-power-domain at 0x10044040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044040 0x20>; + }; + + pd_mau: mau-power-domain at 0x100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + }; gsc_0: gsc at 0x13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_1: gsc at 0x13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_2: gsc at 0x13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; + samsung,power-domain = <&pd_gsc>; }; gsc_3: gsc at 0x13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; + samsung,power-domain = <&pd_gsc>; }; hdmi { --1.7.0.4
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Signature · 2 lines
Thanks Prasanna Kumar
PATCH v2 2/3 arm: exynos5: Enable PM generic domain support in Kconfig
In reply to Prasanna KumarThis patch adds support to enable PM generic domains under Exynos5 family
---
This patch is same as v1
arch/arm/mach-exynos/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/Kconfig +1 -0
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250 depends on ARCH_EXYNOS5 select S5P_PM if PM select S5P_SLEEP if PM + select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC select SAMSUNG_DMADEV help
Signature · 1 line
1.7.0.4
PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
In reply to Prasanna KumarThis patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that CLK_TOP_SRC3 register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.
The value of clock source register is restored once the powergating operation is completed.
--- arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/pm_domains.c +27 -0
@@ -24,6 +24,8 @@#include <mach/regs-pmu.h> #include <plat/devs.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> /* * Exynos specific wrapper around the generic power domain
@@ -41,6 +43,24 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)void __iomem *base;u32 timeout, pwr;char *op; +u32 tmp =0 ; + +/* +*It is found that the CLK SRC register in exynos5 +*gets modified when power domain of gsc/mfc/isp/disp1 +*is powered off.This happens only after the system is +*suspended and resumed and not before that. +*The following fix adresses this hardware issue. +*It saves the value of clock source register and +*resores it later +*/ + +if (of_machine_is_compatible ("samsung,exynos5250" )) { +if (!power_on) { +/* save clock source register */ + tmp =__raw_readl (EXYNOS5_CLKSRC_TOP3 ); + } + } pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base;
@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)cpu_relax ();usleep_range (80 ,100 ); } + +if (of_machine_is_compatible ("samsung,exynos5250" )) { +if (!power_on) { +/* restore clock source register */ +__raw_writel (tmp,EXYNOS5_CLKSRC_TOP3 ); + } + }return 0 ; }
Signature · 1 line
1.7.0.4
PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Prasanna,
Quoted 11 lines · On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code.
Altering clock configuration registers from power domain code looks really ugly...
Best regards,
Tomasz Figa
PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi~
This code should be changed.
I insert this code (save/restore clock source register - CLK_SRC_TOP3) temporary.
But we removed this code. And we use another method to fix it.
I think this is not right way.
Thanks.
Quoted 24 lines · On Fri, Dec 21, 2012 at 6:06 AM, <[email protected]> wrote:
Hi Prasanna,
Quoted 11 lines · On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code.
Altering clock configuration registers from power domain code looks really ugly...
Quoted 9 lines
Best regards,
Tomasz Figa--
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PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Choi,
The method "Save/restore clock source register - CLK_SRC_TOP3" was suggested as well as preferred by our hardware team.
Would it be possible to give more information on this alternate method ?
Quoted 57 lines · jonghwan Choi
Hi~
This code should be changed.
I insert this code (save/restore clock source register -
CLK_SRC_TOP3) temporary.But we removed this code. And we use another method to fix it.
I think this is not right way.
Thanks.
Quoted 25 lines · On Fri, Dec 21, 2012 at 6:06 AM, <[email protected]> wrote:
Hi Prasanna,
Quoted 11 lines · On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code.
Altering clock configuration registers from power domain code looks really ugly...
Quoted 8 lines
Best regards,
Tomasz Figa--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
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Signature · 2 lines
Thanks Prasanna Kumar
PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Choi,
Quoted 7 lines · Prasanna Kumar
Hi Choi,
The method "Save/restore clock source register -
CLK_SRC_TOP3" was suggested as well as preferred by our hardware team.Would it be possible to give more information on this alternate method ?
I just wanted to be more clear on the last sentence of my previous email. Here alternate method means, the method you have used to fix the issue. Kindly share information on that.
--
Thanks
Quoted 65 lines · jonghwan Choi
Quoted 52 lines
Hi~
This code should be changed.
I insert this code (save/restore clock source register -
CLK_SRC_TOP3) temporary.But we removed this code. And we use another method to fix it.
I think this is not right way.
Thanks.
Quoted 25 lines · On Fri, Dec 21, 2012 at 6:06 AM, <[email protected]> wrote:
Hi Prasanna,
Quoted 11 lines · On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code.
Altering clock configuration registers from power domain code looks really ugly...
Quoted 8 lines
Best regards,
Tomasz Figa--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.htmlQuoted 5 lines
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel--
Thanks
Prasanna Kumar
PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
In reply to tomasz.figa at gmail.comHi tomasz,
Quoted 12 lines · On Fri, Dec 21, 2012 at 2:36 AM, <[email protected]> wrote:
Hi Prasanna,
Quoted 9 lines · On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.
Quoted 8 lines
Quoted 2 lines
The value of clock source register is restored once the powergating operation is completed.
Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code.
The problem is only seen in following sequence.
1. Suspend and then Resume the system
2. Power Gating ( On-> Off ) of the associated power domain ( Gscaler , MFC ...)
I rechecked clock save/restore part of power
management code.The register is already being saved clock save/restore part of power
management code. ( exynos5_clock_save. in clock-exynos5.c).
I hope you have understood the situation here.
Quoted 8 lines
Best regards,
Tomasz Figa_______________________________________________
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linux-arm-kernel at lists.infradead.org
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Signature · 2 lines
Thanks Prasanna Kumar
PATCH v2 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
In reply to Prasanna KumarHi Prasanna,
Quoted 40 lines · On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Signed-off-by Prasanna Kumar <[email protected]>--- arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-exynos/pm_domains.cindex 9f1351d..bd8a41e 100644arch/arm/mach-exynos/pm_domains.c +8
-0@@ -24,6 +24,8 @@#include <mach/regs-pmu.h> #include <plat/devs.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> /* * Exynos specific wrapper around the generic power domain @@ -41,6 +43,24 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) void __iomem *base;u32 timeout, pwr;char *op; +u32 tmp =0 ; + +/* +*It is found that the CLK SRC register in exynos5 +*gets modified when power domain of gsc/mfc/isp/disp1 +*is powered off.This happens only after the system is
arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain · line 61
Quoted 10 lines
arch/arm/mach-exynos/pm_domains.c +10
-0+*suspended and resumed and not before that. +*The following fix adresses this hardware issue. +*It saves the value of clock source register and +*resores it later +*/ + +if (of_machine_is_compatible ("samsung,exynos5250" )) { +if (!power_on) { +/* save clock source register */ + tmp =__raw_readl (EXYNOS5_CLKSRC_TOP3 );
I really think this problem needs more investigation, but if gating a power domain can really change a clock source register and save/restore when gating is really required, then the code must be reworked so it does not access clock registers directly.
At the moment it is not a problem, but we are going to have Exynos support for Common Clock Framework merged in near future and it will remove static mapping of clock registers.
Best regards,
Signature · 3 lines
Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform
PATCH 3/3 ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
In reply to Thomas AbrahamHi Thomas,
Quoted 1 line · On Tuesday 04 of December 2012 14:29:24 Thomas Abraham wrote:
On 27 November 2012 17:52, Prasanna Kumar <[email protected]>
Quoted 97 lines · wrote:
Quoted 58 lines
From: Prasanna Kumar <[email protected]>
This patch adds a software workaround to the hardware problem found in exynos5 while powergating.
It is observed that
CLK_TOP_SRC3register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC.The value of clock source register is restored once the powergating operation is completed.
Signed-off-by Prasanna Kumar <[email protected]>---
arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-exynos/pm_domains.cindex 9f1351d..955cbe3 100644arch/arm/mach-exynos/pm_domains.c +2
-0@@ -24,6 +24,8 @@#include <mach/regs-pmu.h> #include <plat/devs.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> /* * Exynos specific wrapper around the generic power domain
arch/arm/mach-exynos/pm_domains.c +1
-0@@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)> void__iomem *base;u32 timeout, pwr;char *op; +u32 tmp =0 ;pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base;arch/arm/mach-exynos/pm_domains.c +6
-0@@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)> pwr = power_on ?S5P_INT_LOCAL_PWR_EN :0 ;__raw_writel (pwr, base); +/* +*It is found that the CLK SRC register in exynos5 +*gets modified when power domain of gsc/mfc/isp/disp1 +*is powered off.This happens only after the system is +*suspended and resumed and not before that. +*The following fix adresses this hardware issue. arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain · line 70
Quoted 10 lines
arch/arm/mach-exynos/pm_domains.c +10
-0+*It saves the value of clock source register and +*resores it later +*/ + +if (soc_is_exynos5250 ()) { +if (!power_on) { +/* save clock source register */ + tmp =__raw_readl (EXYNOS5_CLKSRC_TOP3 ); + } + }Does the value of
EXYNOS5_CLKSRC_TOP3register change as soon as the G-Scaler/MFC devices are power gated?- If yes, the value of CLKSRC register should be saved before the power domain register is programmed.
- If not, as mentioned in the comment, if this issue occurs during a suspend-resume cycle, the value of this register can be saved and restored in the clock driver code itself.
The other thing that needs to be relooked into here is the use of
EXYNOS5_CLKSRC_TOP3register address. Currently, the clock registers are statically io-remapped. With the upcoming migration to common clock for Exynos5, the clock registers will not be statically io-remapped but instead remapped during clock initialization. So the use ofEXYNOS5_CLKSRC_TOP3will not hold and so we need to relook into this.Quoted 10 lines
arch/arm/mach-exynos/pm_domains.c +1
-0+/* Wait max 1ms */ timeout = 10;arch/arm/mach-exynos/pm_domains.c +0
-0@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)>cpu_relax ();usleep_range (80 ,100 );
Quoted 7 lines
arch/arm/mach-exynos/pm_domains.c static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) · line 64
Quoted 4 lines
arch/arm/mach-exynos/pm_domains.c +2
-0} + +if (soc_is_exynos5250 ()) {We could use the
of_machine_is_compatibleapi here instead ofsoc_is_exynos5250()macro.
I don't think that of_machine_is_compatible() is preferred over soc_is_xxx(). The former has dependencies on OF support and requires a string comparison, while the latter is just a single integer check.
Best regards,
Signature · 3 lines
Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform