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FAILED: patch "[PATCH] PCI: xilinx-nwl: Enable the clock through CCF" failed to apply to 4.9-stable tree

PATCH [email protected] 1 participant 1 message Sep 15, 2021

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Stable branch PCI Arm/Zynq architecture PCI native host bridge and endpoint drivers
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The patch below does not apply to the 4.9-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From de0a01f5296651d3a539f2d23d0db8f359483696 Mon Sep 17 00:00:00 2001
From: Hyun Kwon <[email protected]>
Date: Fri, 25 Jun 2021 12:48:23 +0200
Subject: [PATCH] PCI: xilinx-nwl: Enable the clock through CCF

Enable PCIe reference clock. There is no remove function that's why this should be enough for simple operation.
Normally this clock is enabled by default by firmware but there are usecases where this clock should be enabled by driver itself. It is also good that PCIe clock is recorded in a clock framework.

Link https://lore.kernel.org/r/ee6997a08fab582b1c6de05f8be184f3fe8d5357.1624618100.git.michal.simek@xilinx.com open here
Fixes ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller")
Signed-off-by Hyun Kwon <[email protected]>
Signed-off-by Bharat Kumar Gogada <[email protected]>
Signed-off-by Michal Simek <[email protected]>
Signed-off-by Lorenzo Pieralisi <[email protected]>
Cc [email protected]
drivers/pci/controller/pcie-xilinx-nwl.c +12 -0
index 8689311c5ef6..1c3d5b87ef20 100644
@@ -6,6 +6,7 @@
  * (C) Copyright 2014 - 2015, Xilinx, Inc.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>

@@ -169,6 +170,7 @@ struct nwl_pcie {
 	u8 last_busno;
 	struct nwl_msi msi;
 	struct irq_domain *legacy_irq_domain;
+	struct clk *clk;
 	raw_spinlock_t leg_mask_lock;
 };
 

@@ -823,6 +825,16 @@ static int nwl_pcie_probe(struct platform_device *pdev)
 		return err;
 	}
 
+	pcie->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(pcie->clk))
+		return PTR_ERR(pcie->clk);
+
+	err = clk_prepare_enable(pcie->clk);
+	if (err) {
+		dev_err(dev, "can't enable PCIe ref clock\n");
+		return err;
+	}
+
 	err = nwl_pcie_bridge_init(pcie);
 	if (err) {
 		dev_err(dev, "HW Initialization failed\n");