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FAILED: patch "[PATCH] drm/i915: Replace the unconditional clflush with" failed to apply to 5.15-stable tree

PATCH [email protected] 1 participant 1 message Nov 23, 2021

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The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From ef7ec41f17cbc0861891ccc0634d06a0c8dcbf09 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <[email protected]>
Date: Thu, 14 Oct 2021 12:09:38 +0300
Subject: [PATCH] drm/i915: Replace the unconditional clflush with
drm_clflush_virt_range()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Not all machines have clflush, so don't go assuming they do. Not really sure why the clflush is even here since hwsp is supposed to get snooped I thought.

Although in my case we're talking about a i830 machine where render/blitter snooping is definitely busted. But it might work for the hswp perhaps. Haven't really reverse engineered that one fully.

Cc Chris Wilson <[email protected]>
Cc Mika Kuoppala <[email protected]>
Fixes b436a5f8b6c8 ("drm/i915/gt: Track all timelines created using the HWSP")
drivers/gpu/drm/i915/gt/intel_ring_submission.c +1 -1
index 593524195707..586dca1731ce 100644
@@ -292,7 +292,7 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
 	sanitize_hwsp(engine);
 
 	/* And scrub the dirty cachelines for the HWSP */
-	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
 	intel_engine_reset_pinned_contexts(engine);
 }