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FAILED: patch "[PATCH] i2c: stm32f7: flush TX FIFO upon transfer errors" failed to apply to 4.19-stable tree

PATCH [email protected] 1 participant 1 message Dec 5, 2021

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Stable branch Arm STM32 I2C subsystem host drivers ST STM32 I2C/smbus driver
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The patch below does not apply to the 4.19-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 0c21d02ca469574d2082379db52d1a27b99eed0c Mon Sep 17 00:00:00 2001
From: Alain Volmat <[email protected]>
Date: Mon, 20 Sep 2021 17:21:29 +0200
Subject: [PATCH] i2c: stm32f7: flush TX FIFO upon transfer errors

While handling an error during transfer (ex: NACK), it could happen that the driver has already written data into TXDR before the transfer get stopped.
This commit add TXDR Flush after end of transfer in case of error to avoid sending a wrong data on any other slave upon next transfer.

Fixes aeb068c57214 ("i2c: i2c-stm32f7: add driver")
Signed-off-by Alain Volmat <[email protected]>
Reviewed-by Pierre-Yves MORDRET <[email protected]>
Signed-off-by Wolfram Sang <[email protected]>
drivers/i2c/busses/i2c-stm32f7.c +19 -1
index b9b19a2a2ffa..ed977b6f7ab6 100644
@@ -1696,6 +1696,16 @@ static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
 	time_left = wait_for_completion_timeout(&i2c_dev->complete,
 						i2c_dev->adap.timeout);
 	ret = f7_msg->result;
+	if (ret) {
+		/*
+		 * It is possible that some unsent data have already been
+		 * written into TXDR. To avoid sending old data in a
+		 * further transfer, flush TXDR in case of any error
+		 */
+		writel_relaxed(STM32F7_I2C_ISR_TXE,
+			       i2c_dev->base + STM32F7_I2C_ISR);
+		goto pm_free;
+	}
 
 	if (!time_left) {
 		dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",

@@ -1744,8 +1754,16 @@ static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
 	timeout = wait_for_completion_timeout(&i2c_dev->complete,
 					      i2c_dev->adap.timeout);
 	ret = f7_msg->result;
-	if (ret)
+	if (ret) {
+		/*
+		 * It is possible that some unsent data have already been
+		 * written into TXDR. To avoid sending old data in a
+		 * further transfer, flush TXDR in case of any error
+		 */
+		writel_relaxed(STM32F7_I2C_ISR_TXE,
+			       i2c_dev->base + STM32F7_I2C_ISR);
 		goto pm_free;
+	}
 
 	if (!timeout) {
 		dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);