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ARM: dts: ls1021a: add PCIe dts node

PATCH New Minghuan Lian 3 participants 7 messages Feb 2, 2016 – Feb 3, 2016

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Minghuan Lian

author
#0 lore raw

PATCH 1/4 ARM: dts: ls1021a: add PCIe dts node

LS1021a contains two PCIe controllers. The patch adds their node to dts file.

Signed-off-by Minghuan Lian <[email protected]>
---
 arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
arch/arm/boot/dts/ls1021a.dtsi +44 -0
index 2c84ca2..274d647 100644
@@ -560,5 +560,49 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
+			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			fsl,pcie-scfg = <&scfg 0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
+			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,pcie-scfg = <&scfg 1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};
 };
Signature · 1 line
1.9.1
#1 lore raw

PATCH 1/4 ARM: dts: ls1021a: add PCIe dts node

Quoted 8 lines · On Tuesday 02 February 2016 16:30:07 Minghuan Lian wrote:

LS1021a contains two PCIe controllers. The patch adds their node to dts file.

Signed-off-by Minghuan Lian <[email protected]>
---
 arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

Looks ok to me, please submit to the ARM imx maintainers for merging.

Arnd

author
#2 lore raw

PATCH 1/4 ARM: dts: ls1021a: add PCIe dts node

In reply to Minghuan Lian

Hi Shawn,

Could you please help to review the patch? Thank you very much. There is only one patch not a set of patch, please ignore [1/4] :(

Arnd has given a ack.

Thanks,
Minghuan

Quoted 91 lines

-----Original Message-----
From: Minghuan Lian [mailto:Minghuan.Lian at nxp.com]
Sent: Tuesday, February 02, 2016 4:30 PM
To: linux-pci at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; Roy Zang <[email protected]>; Mingkai Hu <[email protected]>; Stuart Yoder <[email protected]>; Yang-Leo Li <[email protected]>; Arnd Bergmann <[email protected]>; Bjorn Helgaas <[email protected]>; Minghuan Lian <[email protected]>
Subject: [PATCH 1/4] ARM: dts: ls1021a: add PCIe dts node

LS1021a contains two PCIe controllers. The patch adds their node to dts file.

Signed-off-by Minghuan Lian <[email protected]>
---
 arch/arm/boot/dts/ls1021a.dtsi | 44
++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
arch/arm/boot/dts/ls1021a.dtsi +4 -0
index 2c84ca2..274d647 100644
@@ -560,5 +560,49 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x00010000   /* controller

registers */

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+			       0x40 0x00000000 0x0 0x00002000>; /* configuration

space */

arch/arm/boot/dts/ls1021a.dtsi +2 -0
+			reg-names = "regs", "config";
+			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*

controller interrupt */

arch/arm/boot/dts/ls1021a.dtsi +7 -0
+			fsl,pcie-scfg = <&scfg 0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0

0x00010000 /* downstream I/O */

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0

0x40000000>; /* non-prefetchable memory */

arch/arm/boot/dts/ls1021a.dtsi +3 -0
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+					<0000 0 0 2 &gic GIC_SPI 188

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+					<0000 0 0 3 &gic GIC_SPI 190

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+					<0000 0 0 4 &gic GIC_SPI 192

IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/ls1021a.dtsi +5 -0
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x00010000   /* controller

registers */

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+			       0x48 0x00000000 0x0 0x00002000>; /* configuration

space */

arch/arm/boot/dts/ls1021a.dtsi +9 -0
+			reg-names = "regs", "config";
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,pcie-scfg = <&scfg 1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0

0x00010000 /* downstream I/O */

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0

0x40000000>; /* non-prefetchable memory */

arch/arm/boot/dts/ls1021a.dtsi +3 -0
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+					<0000 0 0 2 &gic GIC_SPI 189

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+					<0000 0 0 3 &gic GIC_SPI 191

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/ls1021a.dtsi +1 -0
+					<0000 0 0 4 &gic GIC_SPI 193

IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/ls1021a.dtsi +1 -1
+		};
 	};
 };
--

1.9.1

#3 lore raw

PATCH 1/4 ARM: dts: ls1021a: add PCIe dts node

Quoted 6 lines · On Tuesday 02 February 2016 08:48:36 Minghuan Lian wrote:

Hi Shawn,

Could you please help to review the patch? Thank you very much. There is only one patch not a set of patch, please ignore [1/4]

Arnd has given a ack.

For some reason, I did not get the other three patches though, I was going to look at them, but I can't tell if this was a series of patches doing PCI support, or patches doing other dts changes.

If you have additional patches for the PCI driver, let's review it all together first.

Arnd

author
#4 lore raw

PATCH 1/4 ARM: dts: ls1021a: add PCIe dts node

Hi Arnd,

I am sorry.
Other patches are for MSI test, and not need to be summited.
There is only one patch, should be [1/1] not [1/4]. I forgot to remove "1/4" :( Should I re-summit to fix it?

Thanks,
Minghuan

Quoted 26 lines

-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Tuesday, February 02, 2016 5:32 PM
To: linux-arm-kernel at lists.infradead.org
Cc: Minghuan Lian <[email protected]>; linux-pci at vger.kernel.org; Shawn Guo <[email protected]>; Sascha Hauer <[email protected]>; Roy Zang <[email protected]>; Stuart Yoder <[email protected]>; Yang-Leo Li <[email protected]>; Bjorn Helgaas <[email protected]>; Mingkai Hu <[email protected]>
Subject: Re: [PATCH 1/4] ARM: dts: ls1021a: add PCIe dts node

Quoted 6 lines · On Tuesday 02 February 2016 08:48:36 Minghuan Lian wrote:

Hi Shawn,

Could you please help to review the patch? Thank you very much. There is only one patch not a set of patch, please ignore [1/4]

Arnd has given a ack.

For some reason, I did not get the other three patches though, I was going to look at them, but I can't tell if this was a series of patches doing PCI support, or patches doing other dts changes.

If you have additional patches for the PCI driver, let's review it all together first.

Arnd

#5 lore raw

PATCH 1/4 ARM: dts: ls1021a: add PCIe dts node

Quoted 7 lines · On Wednesday 03 February 2016 02:11:06 Minghuan Lian wrote:

Hi Arnd,

I am sorry.
Other patches are for MSI test, and not need to be summited. There is only one patch, should be [1/1] not [1/4]. I forgot to remove "1/4" Should I re-summit to fix it?

Ok, I see. It's up to Shawn then, I guess he can pick it up from this submission if he's ok with the patch.

Arnd