Linux 5.10.95
Greg Kroah-Hartman
maintainerI'm announcing the release of the 5.10.95 kernel.
All users of the 5.10 kernel series must upgrade.
The updated 5.10.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git linux-5.10.y
and can be browsed at the normal kernel.org git web browser:
https://git.kernel.org/?p=linux/kernel/git/stable/linux-stable.git;a=summary
thanks,
greg k-h
------------
Makefile | 2 arch/x86/kvm/mmu/tdp_mmu.c | 6 - drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 + drivers/gpu/drm/i915/gt/intel_gt.c | 102 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 2 drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 drivers/gpu/drm/i915/i915_reg.h | 11 ++ drivers/gpu/drm/i915/i915_vma.c | 3 drivers/gpu/drm/i915/intel_uncore.c | 26 ++++- drivers/gpu/drm/i915/intel_uncore.h | 2 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 5 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 33 +++--- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 2 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 2 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 11 +- drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 6 - drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h | 2 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h | 3 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 75 ++++++++++---- drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c | 13 ++ fs/select.c | 63 ++++++------ kernel/rcu/tree.c | 7 - 23 files changed, 297 insertions(+), 92 deletions(-)
David Matlack (1):
KVM: x86/mmu: Fix write-protection of PTs mapped by the TDP MMU
Greg Kroah-Hartman (1):
Linux 5.10.95
Jan Kara (1):
select: Fix indefinitely sleeping task in poll_schedule_timeout()
Manish Chopra (2):
bnx2x: Utilize firmware 7.13.21.0
bnx2x: Invalidate fastpath HSI version for VFs
Mathias Krause (1):
drm/vmwgfx: Fix stale file descriptors on failed usercopy
Paul E. McKenney (1):
rcu: Tighten rcu_advance_cbs_nowake() checks
Tvrtko Ursulin (1):
drm/i915: Flush TLBs before releasing backing store
Greg Kroah-Hartman
maintainerMakefile +1 -1
@@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 5 PATCHLEVEL = 10 -SUBLEVEL = 94 +SUBLEVEL = 95 EXTRAVERSION = NAME = Dare mighty things
arch/x86/kvm/mmu/tdp_mmu.c +3 -3
@@ -1130,12 +1130,12 @@ static bool write_protect_gfn(struct kvm *kvm, struct kvm_mmu_page *root,bool spte_set = false;tdp_root_for_each_leaf_pte (iter, root, gfn, gfn +1 ) { -if (!is_writable_pte (iter.old_spte)) -break ; - new_spte = iter.old_spte & ~(PT_WRITABLE_MASK |SPTE_MMU_WRITEABLE ); +if (new_spte == iter.old_spte) +break ; +tdp_mmu_set_spte (kvm, &iter, new_spte); spte_set = true; }
drivers/gpu/drm/i915/gem/i915_gem_object_types.h +1 -0
@@ -159,6 +159,7 @@ struct drm_i915_gem_object {#define I915_BO_ALLOC_VOLATILE BIT(1)#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)#define I915_BO_READONLY BIT(2) +#define I915_BO_WAS_BOUND_BIT 3/* * Is the object to be mapped as read-only to the GPU
drivers/gpu/drm/i915/gem/i915_gem_pages.c +10 -0
@@ -10,6 +10,8 @@#include "i915_gem_lmem.h" #include "i915_gem_mman.h" +#include "gt/intel_gt.h" +void __i915_gem_object_set_pages (struct drm_i915_gem_object *obj,struct sg_table *pages,unsigned int sg_page_sizes)
@@ -186,6 +188,14 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)__i915_gem_object_reset_page_iter (obj); obj->mm.page_sizes.phys = obj->mm.page_sizes.sg =0 ; +if (test_and_clear_bit (I915_BO_WAS_BOUND_BIT , &obj->flags)) { +struct drm_i915_private *i915 =to_i915 (obj->base.dev); +intel_wakeref_t wakeref; + + with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref) +intel_gt_invalidate_tlbs (&i915->gt); + } +return pages; }
drivers/gpu/drm/i915/gt/intel_gt.c +102 -0
111 lines not on this page · raw message
drivers/gpu/drm/i915/gt/intel_gt.h +2 -0
@@ -77,4 +77,6 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)void intel_gt_info_print (const struct intel_gt_info *info,struct drm_printer *p); +void intel_gt_invalidate_tlbs (struct intel_gt *gt); +#endif /* __INTEL_GT_H__ */
drivers/gpu/drm/i915/gt/intel_gt_types.h +2 -0
@@ -36,6 +36,8 @@ struct intel_gt {struct intel_uc uc; +struct mutex tlb_invalidate_lock; +struct intel_gt_timelines {spinlock_t lock;/* protects active_list */ struct list_head active_list;
drivers/gpu/drm/i915/i915_reg.h +11 -0
@@ -2639,6 +2639,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) +#define GEN8_RTCR _MMIO(0x4260) +#define GEN8_M1TCR _MMIO(0x4264) +#define GEN8_M2TCR _MMIO(0x4268) +#define GEN8_BTCR _MMIO(0x426c) +#define GEN8_VTCR _MMIO(0x4270) +#if 0 #define PRB0_TAIL _MMIO(0x2030)#define PRB0_HEAD _MMIO(0x2034)
@@ -2728,6 +2734,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)#define FAULT_VA_HIGH_BITS (0xf << 0)#define FAULT_GTT_SEL (1 << 4) +#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8) +#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc) +#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0) +#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4) +#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)#define FPGA_DBG _MMIO(0x42300)
drivers/gpu/drm/i915/i915_vma.c +3 -0
@@ -439,6 +439,9 @@ int i915_vma_bind(struct i915_vma *vma, vma->ops->bind_vma (vma->vm,NULL , vma, cache_level, bind_flags); } +if (vma->obj) +set_bit (I915_BO_WAS_BOUND_BIT , &vma->obj->flags); +atomic_or (bind_flags, &vma->flags);return 0 ; }
drivers/gpu/drm/i915/intel_uncore.c +22 -4
@@ -694,7 +694,8 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, }static void __intel_uncore_forcewake_put (struct intel_uncore *uncore, -enum forcewake_domains fw_domains) +enum forcewake_domains fw_domains, +bool delayed) {struct intel_uncore_forcewake_domain *domain;unsigned int tmp;
@@ -709,7 +710,11 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,continue ; } - uncore->funcs.force_wake_put (uncore, domain->mask); +if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) +fw_domain_arm_timer (domain); +else + uncore->funcs.force_wake_put (uncore, domain->mask); } }
@@ -730,7 +735,20 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,return ;spin_lock_irqsave (&uncore->lock, irqflags); -__intel_uncore_forcewake_put (uncore, fw_domains); +__intel_uncore_forcewake_put (uncore, fw_domains, false); +spin_unlock_irqrestore (&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed (struct intel_uncore *uncore, +enum forcewake_domains fw_domains) +{ +unsigned long irqflags; + +if (!uncore->funcs.force_wake_put) +return ; + +spin_lock_irqsave (&uncore->lock, irqflags); +__intel_uncore_forcewake_put (uncore, fw_domains, true);spin_unlock_irqrestore (&uncore->lock, irqflags); }
@@ -772,7 +790,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,if (!uncore->funcs.force_wake_put)return ; -__intel_uncore_forcewake_put (uncore, fw_domains); +__intel_uncore_forcewake_put (uncore, fw_domains, false); }void assert_forcewakes_inactive (struct intel_uncore *uncore)
drivers/gpu/drm/i915/intel_uncore.h +2 -0
@@ -211,6 +211,8 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore, enum forcewake_domains domains);void intel_uncore_forcewake_put (struct intel_uncore *uncore,enum forcewake_domains domains); +void intel_uncore_forcewake_put_delayed (struct intel_uncore *uncore, +enum forcewake_domains domains);void intel_uncore_forcewake_flush (struct intel_uncore *uncore,enum forcewake_domains fw_domains);
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +2 -3
@@ -1088,15 +1088,14 @@ extern int vmw_execbuf_fence_commands(struct drm_file *file_priv,struct vmw_private *dev_priv, struct vmw_fence_obj **p_fence, uint32_t *p_handle); -extern void vmw_execbuf_copy_fence_user (struct vmw_private *dev_priv, +extern int vmw_execbuf_copy_fence_user (struct vmw_private *dev_priv,struct vmw_fpriv *vmw_fp,int ret,struct drm_vmw_fence_rep __user *user_fence_rep,struct vmw_fence_obj *fence,uint32_t fence_handle, -int32_t out_fence_fd, -struct sync_file *sync_file); +int32_t out_fence_fd);bool vmw_cmd_describe (const void *buf,u32 *size,char const **cmd);/**
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +17 -16
@@ -3816,17 +3816,17 @@ int vmw_execbuf_fence_commands(struct drm_file *file_priv,* Also if copying fails, user-space will be unable to signal the fence object * so we wait for it immediately, and then unreference the user-space reference. */ -void +int vmw_execbuf_copy_fence_user (struct vmw_private *dev_priv,struct vmw_fpriv *vmw_fp,int ret,struct drm_vmw_fence_rep __user *user_fence_rep,struct vmw_fence_obj *fence,uint32_t fence_handle, -int32_t out_fence_fd,struct sync_file *sync_file) +int32_t out_fence_fd) {struct drm_vmw_fence_rep fence_rep;if (user_fence_rep ==NULL ) -return ; +return 0 ;memset (&fence_rep,0 ,sizeof (fence_rep));
@@ -3854,20 +3854,14 @@ vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv,* handle. */ if (unlikely (ret !=0 ) && (fence_rep.error ==0 )) { -if (sync_file) -fput (sync_file->file); - -if (fence_rep.fd !=-1 ) { -put_unused_fd (fence_rep.fd); - fence_rep.fd =-1 ; - } -ttm_ref_object_base_unref (vmw_fp->tfile, fence_handle,TTM_REF_USAGE );VMW_DEBUG_USER ("Fence copy error. Syncing.\n" ); (void )vmw_fence_obj_wait (fence, false, false,VMW_FENCE_WAIT_TIMEOUT ); } + +return ret ? -EFAULT :0 ; }/**
@@ -4209,16 +4203,23 @@ int vmw_execbuf_process(struct drm_file *file_priv, (void )vmw_fence_obj_wait (fence, false, false,VMW_FENCE_WAIT_TIMEOUT ); + } + } + + ret =vmw_execbuf_copy_fence_user (dev_priv,vmw_fpriv (file_priv), ret, + user_fence_rep, fence, handle, out_fence_fd); + +if (sync_file) { +if (ret) { +/* usercopy of fence failed, put the file object */ +fput (sync_file->file); +put_unused_fd (out_fence_fd); }else {/* Link the fence with the FD created earlier */ fd_install (out_fence_fd, sync_file->file); } } -vmw_execbuf_copy_fence_user (dev_priv,vmw_fpriv (file_priv), ret, - user_fence_rep, fence, handle, out_fence_fd, - sync_file); -/* Don't unreference when handing fence out */ if (unlikely (out_fence !=NULL )) { *out_fence = fence;
@@ -4236,7 +4237,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,*/ vmw_validation_unref_lists (&val_ctx); -return 0 ; +return ret; out_unlock_binding:mutex_unlock (&dev_priv->binding_mutex);
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +1 -1
@@ -1171,7 +1171,7 @@ int vmw_fence_event_ioctl(struct drm_device *dev, void *data, }vmw_execbuf_copy_fence_user (dev_priv, vmw_fp,0 , user_fence_rep, fence, - handle,-1 ,NULL ); + handle,-1 );vmw_fence_obj_unreference (&fence);return 0 ; out_no_create:
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +1 -1
@@ -2479,7 +2479,7 @@ void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv,if (file_priv)vmw_execbuf_copy_fence_user (dev_priv,vmw_fpriv (file_priv), ret, user_fence_rep, fence, - handle,-1 ,NULL ); + handle,-1 );if (out_fence) *out_fence = fence;else
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h +10 -1
@@ -1850,6 +1850,14 @@ struct bnx2x {/* Vxlan/Geneve related information */ u16 udp_tunnel_ports[BNX2X_UDP_PORT_MAX ]; + +#define FW_CAP_INVALIDATE_VF_FP_HSI BIT(0) +u32 fw_cap; + +u32 fw_major; +u32 fw_minor; +u32 fw_rev; +u32 fw_eng; };/* Tx queues may be less or equal to Rx queues */
@@ -2526,5 +2534,6 @@ void bnx2x_register_phc(struct bnx2x *bp);* Meant for implicit re-load flows. */ int bnx2x_vlan_reconfigure_vid (struct bnx2x *bp); - +int bnx2x_init_firmware (struct bnx2x *bp); +void bnx2x_release_firmware (struct bnx2x *bp);#endif /* bnx2x.h */
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c +2 -4
@@ -2364,10 +2364,8 @@ int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err)if (load_code !=FW_MSG_CODE_DRV_LOAD_COMMON_CHIP && load_code !=FW_MSG_CODE_DRV_LOAD_COMMON ) {/* build my FW version dword */ -u32 my_fw = (BCM_5710_FW_MAJOR_VERSION ) + - (BCM_5710_FW_MINOR_VERSION <<8 ) + - (BCM_5710_FW_REVISION_VERSION <<16 ) + - (BCM_5710_FW_ENGINEERING_VERSION <<24 ); +u32 my_fw = (bp->fw_major) + (bp->fw_minor <<8 ) + + (bp->fw_rev <<16 ) + (bp->fw_eng <<24 );/* read loaded FW from chip */ u32 loaded_fw =REG_RD (bp,XSEM_REG_PRAM );
drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h +2 -0
@@ -241,6 +241,8 @@ IRO[221].m2))#define XSTORM_VF_TO_PF_OFFSET (funcId) \ (IRO[48].base + ((funcId) * IRO[48].m1)) +#define XSTORM_ETH_FUNCTION_INFO_FP_HSI_VALID_E2_OFFSET (fid) \ + (IRO[386].base + ((fid) * IRO[386].m1))#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0/* eth hsi version */
drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h +2 -1
@@ -3024,7 +3024,8 @@ struct afex_stats {#define BCM_5710_FW_MAJOR_VERSION 7#define BCM_5710_FW_MINOR_VERSION 13 -#define BCM_5710_FW_REVISION_VERSION 15 +#define BCM_5710_FW_REVISION_VERSION 21 +#define BCM_5710_FW_REVISION_VERSION_V15 15#define BCM_5710_FW_ENGINEERING_VERSION 0#define BCM_5710_FW_COMPILE_FLAGS 1
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +53 -22
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drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c +11 -2
@@ -758,9 +758,18 @@ static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf)void bnx2x_vf_enable_access (struct bnx2x *bp,u8 abs_vfid) { +u16 abs_fid; + + abs_fid =FW_VF_HANDLE (abs_vfid); +/* set the VF-PF association in the FW */ -storm_memset_vf_to_pf (bp,FW_VF_HANDLE (abs_vfid),BP_FUNC (bp)); -storm_memset_func_en (bp,FW_VF_HANDLE (abs_vfid),1 ); +storm_memset_vf_to_pf (bp, abs_fid,BP_FUNC (bp)); +storm_memset_func_en (bp, abs_fid,1 ); + +/* Invalidate fp_hsi version for vfs */ +if (bp->fw_cap &FW_CAP_INVALIDATE_VF_FP_HSI ) +REG_WR8 (bp,BAR_XSTRORM_INTMEM + +XSTORM_ETH_FUNCTION_INFO_FP_HSI_VALID_E2_OFFSET (abs_fid),0 );/* clear vf errors*/ bnx2x_vf_semi_clear_err (bp, abs_vfid);
fs/select.c +33 -30
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kernel/rcu/tree.c +4 -3
@@ -1581,10 +1581,11 @@ static void __maybe_unused rcu_advance_cbs_nowake(struct rcu_node *rnp, struct rcu_data *rdp) {rcu_lockdep_assert_cblist_protected (rdp); -if (!rcu_seq_state (rcu_seq_current (&rnp->gp_seq)) || - !raw_spin_trylock_rcu_node (rnp)) +if (!rcu_seq_state (rcu_seq_current (&rnp->gp_seq)) || !raw_spin_trylock_rcu_node (rnp))return ; -WARN_ON_ONCE (rcu_advance_cbs (rnp, rdp)); +// The grace period cannot end while we hold the rcu_node lock. +if (rcu_seq_state (rcu_seq_current (&rnp->gp_seq))) +WARN_ON_ONCE (rcu_advance_cbs (rnp, rdp));raw_spin_unlock_rcu_node (rnp); }