pinctrl: sh-pfc: r7s72100 SCIF2 support

PATCH Superseded Magnus Damm 4 participants 11 messages Nov 27, 2013 – Dec 4, 2013

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Magnus Damm

author

2013-11-27 08:05 UTC #0 lore raw

cover pinctrl: sh-pfc: r7s72100 SCIF2 support

pinctrl: sh-pfc: r7s72100 SCIF2 support

[PATCH 01/03] pinctrl: sh-pfc: r7s72100 SCIF2 port3 support [PATCH 02/03] pinctrl: sh-pfc: r7s72100 SCIF2 macro conversion [PATCH 03/03] pinctrl: sh-pfc: r7s72100 SCIF2 port4, 6 and 8 support

Add PINCTL support for one channel of on-chip UART included in the r7s72100 SoC. This UART is called SCIF2 and happens to be the console port on the Genmai board.

These patches are written in a broken out way to show how the r7s72100 hardware allows fine grained control of the pins, and proposes code that
a) allows individual assignment of TxD and RxD signals.
b) introduces macros to allow less verbose tables
c) lists single-pin functions with one pin per line

Basically, just using "clk", "data" and "ctrl" to describe groups is not fine grained enough for this SoC. For such fine grained on-chip devices there will be single-pin groups, and in the case of the Genmai board the groups to enable SCIF2 will be "scif2_txd_p3_0" and "scif2_rxd_p3_2".

If you prefer me to adjust this code somehow then please let me know.

Signed-off-by Magnus Damm <[email protected]>

---

Written against renesas.git tag renesas-devel-v3.13-rc1-20131125 and [PATCH] pinctrl: sh-pfc: Initial r7s72100 support

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  117 ++++++++++++++++++++++-----------
 1 file changed, 80 insertions(+), 37 deletions(-)

Magnus Damm

author

2013-11-27 08:05 UTC #1 lore raw

PATCH 1/3 pinctrl: sh-pfc: r7s72100 SCIF2 port3 support

From: Magnus Damm <[email protected]>

Add support for SCIF2 port3 pin functions SCK, TXD and RXD to the r7s72100 PINCTRL code. There are two possible pins that can be used for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and because of that are the data pins broken out in separate TXD and RXD.

This format is similar to other sh-pfc code, but a following patch converts this to less verbose and less readable code.

Signed-off-by Magnus Damm <[email protected]>

---

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +41 -0

@@ -103,10 +103,51 @@ static struct sh_pfc_pin pinmux_pins[] =
 	_P_ALL(_P_GPIO),
 };
 
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_txd_p3_0_pins[] = {
+	/* TX */
+	RZ_PORT_PIN(3, 0),
+};
+static const unsigned int scif2_txd_p3_0_mux[] = {
+	P_3_0_MARK_FN6,
+};
+static const unsigned int scif2_txd_p3_1_pins[] = {
+	/* TX */
+	RZ_PORT_PIN(3, 1),
+};
+static const unsigned int scif2_txd_p3_1_mux[] = {
+	P_3_1_MARK_FN4,
+};
+static const unsigned int scif2_rxd_p3_2_pins[] = {
+	/* RX */
+	RZ_PORT_PIN(3, 2),
+};
+static const unsigned int scif2_rxd_p3_2_mux[] = {
+	P_3_2_MARK_FN4,
+};
+static const unsigned int scif2_clk_p3_0_pins[] = {
+	/* SCK */
+	RZ_PORT_PIN(3, 0),
+};
+static const unsigned int scif2_clk_p3_0_mux[] = {
+	P_3_0_MARK_FN4,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(scif2_txd_p3_0),
+	SH_PFC_PIN_GROUP(scif2_txd_p3_1),
+	SH_PFC_PIN_GROUP(scif2_rxd_p3_2),
+	SH_PFC_PIN_GROUP(scif2_clk_p3_0),
 };
 
+static const char * const scif2_groups[] = {
+	"scif2_txd_p3_0",
+	"scif2_txd_p3_1",
+	"scif2_rxd_p3_2",
+	"scif2_clk_p3_0",
+};
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scif2),
 };
 
 #define PFC_REG(idx, name, reg)						\

Laurent Pinchart

2013-11-27 10:56 UTC #2 lore raw

Re: [PATCH 01/03] pinctrl: sh-pfc: r7s72100 SCIF2 port3 support

Hi Magnus,

Thank you for the patch.

Quoted 9 lines · On Wednesday 27 November 2013 17:06:21 Magnus Damm wrote:

From: Magnus Damm <[email protected]>
Add support for SCIF2 port3 pin functions SCK, TXD and RXD to the r7s72100 PINCTRL code. There are two possible pins that can be used for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and because of that are the data pins broken out in separate TXD and RXD.
This format is similar to other sh-pfc code, but a following patch converts this to less verbose and less readable code.

You hopefully mean more readable :-)

It would help me reviewing this patch if I could get access to the SoC datasheet.

drivers/pinctrl/sh-pfc/pfc-r7s72100.c

Quoted 8 lines

Signed-off-by Magnus Damm <[email protected]>
---
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   41 ++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r7s72100.c +0 -0

15:22:16.000000000

Quoted 51 lines

+0900 @@ -103,10 +103,51 @@ static struct sh_pfc_pin pinmux_pins[] > _P_ALL(_P_GPIO),
};

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +41 -0

+/* - SCIF2 ------------------------------------------------------------- */
+static const unsigned int scif2_txd_p3_0_pins[] = {
+	/* TX */
+	RZ_PORT_PIN(3, 0),
+};
+static const unsigned int scif2_txd_p3_0_mux[] = {
+	P_3_0_MARK_FN6,
+};
+static const unsigned int scif2_txd_p3_1_pins[] = {
+	/* TX */
+	RZ_PORT_PIN(3, 1),
+};
+static const unsigned int scif2_txd_p3_1_mux[] = {
+	P_3_1_MARK_FN4,
+};
+static const unsigned int scif2_rxd_p3_2_pins[] = {
+	/* RX */
+	RZ_PORT_PIN(3, 2),
+};
+static const unsigned int scif2_rxd_p3_2_mux[] = {
+	P_3_2_MARK_FN4,
+};
+static const unsigned int scif2_clk_p3_0_pins[] = {
+	/* SCK */
+	RZ_PORT_PIN(3, 0),
+};
+static const unsigned int scif2_clk_p3_0_mux[] = {
+	P_3_0_MARK_FN4,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(scif2_txd_p3_0),
+	SH_PFC_PIN_GROUP(scif2_txd_p3_1),
+	SH_PFC_PIN_GROUP(scif2_rxd_p3_2),
+	SH_PFC_PIN_GROUP(scif2_clk_p3_0),
 };
 
+static const char * const scif2_groups[] = {
+	"scif2_txd_p3_0",
+	"scif2_txd_p3_1",
+	"scif2_rxd_p3_2",
+	"scif2_clk_p3_0",
+};
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scif2),
 };
 
 #define PFC_REG(idx, name, reg)						\

Signature · 3 lines

Regards,

Laurent Pinchart

Linus Walleij

2013-11-29 10:29 UTC #3 lore raw

Re: [PATCH 01/03] pinctrl: sh-pfc: r7s72100 SCIF2 port3 support

In reply to Magnus Damm

Quoted 11 lines · Magnus Damm

From: Magnus Damm <[email protected]>
Add support for SCIF2 port3 pin functions SCK, TXD and RXD to the r7s72100 PINCTRL code. There are two possible pins that can be used for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and because of that are the data pins broken out in separate TXD and RXD.
This format is similar to other sh-pfc code, but a following patch converts this to less verbose and less readable code.
Signed-off-by Magnus Damm <[email protected]>

Regarding this and other PFC patches: Laurent can you help me out with collecting the patches for my pinctrl tree and send me a pull request when it's all tested together, like you did in the last kernel cycle?

Yours,
Linus Walleij

Laurent Pinchart

2013-11-29 13:53 UTC #4 lore raw

Re: [PATCH 01/03] pinctrl: sh-pfc: r7s72100 SCIF2 port3 support

Hi Linus,

Quoted 11 lines · On Friday 29 November 2013 11:29:51 Linus Walleij wrote:

Quoted 10 lines · Magnus Damm
From: Magnus Damm <[email protected]>
Add support for SCIF2 port3 pin functions SCK, TXD and RXD to the r7s72100 PINCTRL code. There are two possible pins that can be used for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and because of that are the data pins broken out in separate TXD and RXD.
This format is similar to other sh-pfc code, but a following patch converts this to less verbose and less readable code.

Quoted 6 lines

Quoted 1 line
Signed-off-by Magnus Damm <[email protected]>
Regarding this and other PFC patches: Laurent can you help me out with collecting the patches for my pinctrl tree and send me a pull request when it's all tested together, like you did in the last kernel cycle?

Sure, will do.

Signature · 3 lines

Regards,

Laurent Pinchart

Magnus Damm

author

2013-11-27 08:06 UTC #5 lore raw

PATCH 2/3 pinctrl: sh-pfc: r7s72100 SCIF2 macro conversion

In reply to Magnus Damm

From: Magnus Damm <[email protected]>

Convert from rather verbose description of single pin groups to making use of macros to describe one pin per line. The actual bulk of the SCIF2 description is kept in the SCIF2 macro.

Compresses the description of each pin from 9 to 1 line.

Signed-off-by Magnus Damm <[email protected]>

---

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   64 ++++++++++++++-------------------
 1 file changed, 28 insertions(+), 36 deletions(-)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +28 ~~-36~~

@@ -103,48 +103,40 @@ static struct sh_pfc_pin pinmux_pins[] =
 	_P_ALL(_P_GPIO),
 };
 
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_txd_p3_0_pins[] = {
-	/* TX */
-	RZ_PORT_PIN(3, 0),
-};
-static const unsigned int scif2_txd_p3_0_mux[] = {
-	P_3_0_MARK_FN6,
-};
-static const unsigned int scif2_txd_p3_1_pins[] = {
-	/* TX */
-	RZ_PORT_PIN(3, 1),
-};
-static const unsigned int scif2_txd_p3_1_mux[] = {
-	P_3_1_MARK_FN4,
-};
-static const unsigned int scif2_rxd_p3_2_pins[] = {
-	/* RX */
-	RZ_PORT_PIN(3, 2),
-};
-static const unsigned int scif2_rxd_p3_2_mux[] = {
-	P_3_2_MARK_FN4,
-};
-static const unsigned int scif2_clk_p3_0_pins[] = {
-	/* SCK */
-	RZ_PORT_PIN(3, 0),
-};
-static const unsigned int scif2_clk_p3_0_mux[] = {
-	P_3_0_MARK_FN4,
+#define __RZ_STR(pfx, hw, bank, pin, sfx)		\
+	pfx##_##hw##_p##bank##_##pin####sfx
+
+#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)				\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {	\
+	RZ_PORT_PIN(bank, pin),						\
+};									\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {	\
+	P_##bank##_##pin##_MARK_FN##fn,					\
 };
 
+#define RZ_PMX_GRP(pfx, hw, bank, pin, fn) \
+	SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
+
+#define __RZ_GPRS(x) #x
+
+#define RZ_GRPS(pfx, hw, bank, pin, fn) \
+	__RZ_GPRS(pfx##_##hw##_p##bank##_##pin),
+
+
+#define SCIF2(fn)			\
+	fn(scif2, txd, 3, 0, 6)		\
+	fn(scif2, txd, 3, 1, 4)		\
+	fn(scif2, rxd, 3, 2, 4)		\
+	fn(scif2, clk, 3, 0, 4)
+
+SCIF2(RZ_PIN_AND_MUX)
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(scif2_txd_p3_0),
-	SH_PFC_PIN_GROUP(scif2_txd_p3_1),
-	SH_PFC_PIN_GROUP(scif2_rxd_p3_2),
-	SH_PFC_PIN_GROUP(scif2_clk_p3_0),
+	SCIF2(RZ_PMX_GRP)
 };
 
 static const char * const scif2_groups[] = {
-	"scif2_txd_p3_0",
-	"scif2_txd_p3_1",
-	"scif2_rxd_p3_2",
-	"scif2_clk_p3_0",
+	SCIF2(RZ_GRPS)
 };
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif2),

Laurent Pinchart

2013-11-27 11:02 UTC #6 lore raw

Re: [PATCH 02/03] pinctrl: sh-pfc: r7s72100 SCIF2 macro conversion

Hi Magnus,

Thank you for the patch.

drivers/pinctrl/sh-pfc/pfc-r7s72100.c

Quoted 16 lines · On Wednesday 27 November 2013 17:06:30 Magnus Damm wrote:

From: Magnus Damm <[email protected]>
Convert from rather verbose description of single pin groups to making use of macros to describe one pin per line. The actual bulk of the SCIF2 description is kept in the SCIF2 macro.
Compresses the description of each pin from 9 to 1 line.
Signed-off-by Magnus Damm <[email protected]>
---
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   64 +++++++++++++-----------------
 1 file changed, 28 insertions(+), 36 deletions(-)
drivers/pinctrl/sh-pfc/pfc-r7s72100.c +0 -0

14:19:24.000000000

Quoted 39 lines

+0900 @@ -103,48 +103,40 @@ static struct sh_pfc_pin pinmux_pins[] > _P_ALL(_P_GPIO),
};

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +8 ~~-28~~

-/* - SCIF2 ------------------------------------------------------------- */
-static const unsigned int scif2_txd_p3_0_pins[] = {
-	/* TX */
-	RZ_PORT_PIN(3, 0),
-};
-static const unsigned int scif2_txd_p3_0_mux[] = {
-	P_3_0_MARK_FN6,
-};
-static const unsigned int scif2_txd_p3_1_pins[] = {
-	/* TX */
-	RZ_PORT_PIN(3, 1),
-};
-static const unsigned int scif2_txd_p3_1_mux[] = {
-	P_3_1_MARK_FN4,
-};
-static const unsigned int scif2_rxd_p3_2_pins[] = {
-	/* RX */
-	RZ_PORT_PIN(3, 2),
-};
-static const unsigned int scif2_rxd_p3_2_mux[] = {
-	P_3_2_MARK_FN4,
-};
-static const unsigned int scif2_clk_p3_0_pins[] = {
-	/* SCK */
-	RZ_PORT_PIN(3, 0),
-};
-static const unsigned int scif2_clk_p3_0_mux[] = {
-	P_3_0_MARK_FN4,
+#define __RZ_STR(pfx, hw, bank, pin, sfx)		\
+	pfx##_##hw##_p##bank##_##pin####sfx
+
+#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)				\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {	\
+	RZ_PORT_PIN(bank, pin),						\
+};									\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {	\

drivers/pinctrl/sh-pfc/pfc-r7s72100.c static struct sh_pfc_pin pinmux_pins[] = · line 123

Quoted 10 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +8 -0

+	P_##bank##_##pin##_MARK_FN##fn,					\
 };
 
+#define RZ_PMX_GRP(pfx, hw, bank, pin, fn) \
+	SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
+
+#define __RZ_GPRS(x) #x
+
+#define RZ_GRPS(pfx, hw, bank, pin, fn) \
+	__RZ_GPRS(pfx##_##hw##_p##bank##_##pin),

I believe the code would be more readable if you didn't abbreviate GRP and GRPS. I would use GROUP and GROUPS instead.

Quoted 17 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +11 -4

+
+
+#define SCIF2(fn)			\
+	fn(scif2, txd, 3, 0, 6)		\
+	fn(scif2, txd, 3, 1, 4)		\
+	fn(scif2, rxd, 3, 2, 4)		\
+	fn(scif2, clk, 3, 0, 4)
+
+SCIF2(RZ_PIN_AND_MUX)
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(scif2_txd_p3_0),
-	SH_PFC_PIN_GROUP(scif2_txd_p3_1),
-	SH_PFC_PIN_GROUP(scif2_rxd_p3_2),
-	SH_PFC_PIN_GROUP(scif2_clk_p3_0),
+	SCIF2(RZ_PMX_GRP)
 };

drivers/pinctrl/sh-pfc/pfc-r7s72100.c static struct sh_pfc_pin pinmux_pins[] = · line 142

Quoted 10 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +1 -4

 
 static const char * const scif2_groups[] = {
-	"scif2_txd_p3_0",
-	"scif2_txd_p3_1",
-	"scif2_rxd_p3_2",
-	"scif2_clk_p3_0",
+	SCIF2(RZ_GRPS)
 };
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif2),

Once again it would help if I could access the datasheet.

Signature · 3 lines

Regards,

Laurent Pinchart

Magnus Damm

author

2013-11-27 08:06 UTC #7 lore raw

PATCH 3/3 pinctrl: sh-pfc: r7s72100 SCIF2 port4, 6 and 8 support

In reply to Magnus Damm

From: Magnus Damm <[email protected]>

Add the remaining SCIF2 pins using the recently introduced macro.

Signed-off-by Magnus Damm <[email protected]>

---

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +11 -1

@@ -127,7 +127,17 @@ static const unsigned int __RZ_STR(pfx,
 	fn(scif2, txd, 3, 0, 6)		\
 	fn(scif2, txd, 3, 1, 4)		\
 	fn(scif2, rxd, 3, 2, 4)		\
-	fn(scif2, clk, 3, 0, 4)
+	fn(scif2, clk, 3, 0, 4)		\
+	fn(scif2, clk, 4, 1, 5)		\
+	fn(scif2, txd, 4, 2, 5)		\
+	fn(scif2, rxd, 4, 3, 5)		\
+	fn(scif2, txd, 4, 14, 7)	\
+	fn(scif2, rxd, 4, 15, 7)	\
+	fn(scif2, txd, 6, 2, 7)		\
+	fn(scif2, rxd, 6, 3, 7)		\
+	fn(scif2, clk, 8, 3, 7)		\
+	fn(scif2, txd, 8, 6, 7)		\
+	fn(scif2, rxd, 8, 4, 7)
 
 SCIF2(RZ_PIN_AND_MUX)

Linus Walleij

Acked-by on v1 3/3

2013-12-03 09:36 UTC #8 lore raw

Re: [PATCH 03/03] pinctrl: sh-pfc: r7s72100 SCIF2 port4, 6 and 8 support

Quoted 5 lines · Magnus Damm

From: Magnus Damm <[email protected]>
Add the remaining SCIF2 pins using the recently introduced macro.
Signed-off-by Magnus Damm <[email protected]>

Acked-by Linus Walleij <[email protected]>

Laurent, please pick this into your stack for my tree.

I guess the pure DTS changes can go directly to Simon's tree?

Yours,
Linus Walleij

Simon Horman

2013-12-03 12:18 UTC #9 lore raw

Re: [PATCH 03/03] pinctrl: sh-pfc: r7s72100 SCIF2 port4, 6 and 8 support

Quoted 6 lines · Linus Walleij

Quoted 4 lines · Magnus Damm
From: Magnus Damm <[email protected]>
Add the remaining SCIF2 pins using the recently introduced macro.

Quoted 7 lines

Quoted 1 line
Signed-off-by Magnus Damm <[email protected]>
Acked-by Linus Walleij <[email protected]>
Laurent, please pick this into your stack for my tree.
I guess the pure DTS changes can go directly to Simon's tree?

Yes, I'll pick them up.

Laurent Pinchart

2013-12-04 01:09 UTC #10 lore raw

Re: [PATCH 03/03] pinctrl: sh-pfc: r7s72100 SCIF2 port4, 6 and 8 support

In reply to Linus Walleij

Hi Linus,

Quoted 10 lines · On Tuesday 03 December 2013 10:36:54 Linus Walleij wrote:

Quoted 5 lines · Magnus Damm
From: Magnus Damm <[email protected]>
Add the remaining SCIF2 pins using the recently introduced macro.
Signed-off-by Magnus Damm <[email protected]>
Acked-by Linus Walleij <[email protected]>
Laurent, please pick this into your stack for my tree.

I'd like to review it first, with the SoC documentation if possible. Magnus, is that something I could get access to ?

Quoted 1 line

I guess the pure DTS changes can go directly to Simon's tree?

Signature · 3 lines

Regards,

Laurent Pinchart