ARM 32-bit build with Clang IAS

Link https://github.com/ClangBuiltLinux/linux/issues/762

---
 arch/arm/vfp/Makefile |  2 --
 arch/arm/vfp/vfphw.S  | 30 ++++++++++++++++++++----------
 2 files changed, 20 insertions(+), 12 deletions(-)

arch/arm/vfp/Makefile +0 -2

index 9975b63ac3b0..749901a72d6d 100644
@@ -8,6 +8,4 @@
 # ccflags-y := -DDEBUG
 # asflags-y := -DDEBUG
 
-KBUILD_AFLAGS	:=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft)
-
 obj-y		+= vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o

arch/arm/vfp/vfphw.S +20 ~~-10~~

index b530db8f2c6c..772c6a3b1f72 100644
@@ -253,11 +253,14 @@ vfp_current_hw_state_address:
 
 ENTRY(vfp_get_float)
 	tbl_branch r0, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
+1:	vmov	r0, s\dr
 	ret	lr
 	.org	1b + 8
-1:	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
+	.endr
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	r0, s\dr
 	ret	lr
 	.org	1b + 8
 	.endr

@@ -265,11 +268,14 @@ ENDPROC(vfp_get_float)
 
 ENTRY(vfp_put_float)
 	tbl_branch r1, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
+1:	vmov	s\dr, r0
 	ret	lr
 	.org	1b + 8
-1:	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
+	.endr
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	s\dr, r0
 	ret	lr
 	.org	1b + 8
 	.endr

@@ -277,15 +283,17 @@ ENDPROC(vfp_put_float)
 
 ENTRY(vfp_get_double)
 	tbl_branch r0, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	fmrrd	r0, r1, d\dr
+1:	vmov	r0, r1, d\dr
 	ret	lr
 	.org	1b + 8
 	.endr
 #ifdef CONFIG_VFPv3
 	@ d16 - d31 registers
-	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
+	.fpu	vfpv3
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	r0, r1, d\dr
 	ret	lr
 	.org	1b + 8
 	.endr

@@ -299,15 +307,17 @@ ENDPROC(vfp_get_double)
 
 ENTRY(vfp_put_double)
 	tbl_branch r2, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	fmdrr	d\dr, r0, r1
+1:	vmov	d\dr, r0, r1
 	ret	lr
 	.org	1b + 8
 	.endr
 #ifdef CONFIG_VFPv3
+	.fpu	vfpv3
 	@ d16 - d31 registers
-	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mcrr	p11, 3, r0, r1, c\dr	@ fmdrr	r0, r1, d\dr
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	d\dr, r0, r1
 	ret	lr
 	.org	1b + 8
 	.endr

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:31 UTC #2 lore raw

Patch "ARM: 8989/1: use .fpu assembler directives instead of assembler arguments" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: 8989/1: use .fpu assembler directives instead of assembler arguments

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:17 -0700
Subject: ARM: 8989/1: use .fpu assembler directives instead of assembler arguments
To: [email protected]
Cc: Stefan Agner <[email protected]>, Russell King <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Ard Biesheuvel <[email protected]>, Nick Desaulniers <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Stefan Agner <[email protected]>

commit a6c30873ee4a5cc0549c1973668156381ab2c1c4 upstream

Explicit FPU selection has been introduced in commit 1a6be26d5b1a ("[ARM] Enable VFP to be built when non-VFP capable CPUs are selected") to make use of assembler mnemonics for VFP instructions.

However, clang currently does not support passing assembler flags like this and errors out with:
clang-10: error: the clang compiler does not support '-Wa,-mfpu=softvfp+vfp'

Make use of the .fpu assembler directives to select the floating point hardware selectively. Also use the new unified assembler language mnemonics. This allows to build these procedures with Clang.

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/vfp/Makefile |    2 --
 arch/arm/vfp/vfphw.S  |   30 ++++++++++++++++++++----------
 2 files changed, 20 insertions(+), 12 deletions(-)

arch/arm/vfp/Makefile +0 -2

@@ -8,6 +8,4 @@
 # ccflags-y := -DDEBUG
 # asflags-y := -DDEBUG
 
-KBUILD_AFLAGS	:=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft)
-
 obj-y		+= vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o

arch/arm/vfp/vfphw.S +20 ~~-10~~

@@ -253,11 +253,14 @@ vfp_current_hw_state_address:
 
 ENTRY(vfp_get_float)
 	tbl_branch r0, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
+1:	vmov	r0, s\dr
 	ret	lr
 	.org	1b + 8
-1:	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
+	.endr
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	r0, s\dr
 	ret	lr
 	.org	1b + 8
 	.endr

@@ -265,11 +268,14 @@ ENDPROC(vfp_get_float)
 
 ENTRY(vfp_put_float)
 	tbl_branch r1, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
+1:	vmov	s\dr, r0
 	ret	lr
 	.org	1b + 8
-1:	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
+	.endr
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	s\dr, r0
 	ret	lr
 	.org	1b + 8
 	.endr

@@ -277,15 +283,17 @@ ENDPROC(vfp_put_float)
 
 ENTRY(vfp_get_double)
 	tbl_branch r0, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	fmrrd	r0, r1, d\dr
+1:	vmov	r0, r1, d\dr
 	ret	lr
 	.org	1b + 8
 	.endr
 #ifdef CONFIG_VFPv3
 	@ d16 - d31 registers
-	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
+	.fpu	vfpv3
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	r0, r1, d\dr
 	ret	lr
 	.org	1b + 8
 	.endr

@@ -299,15 +307,17 @@ ENDPROC(vfp_get_double)
 
 ENTRY(vfp_put_double)
 	tbl_branch r2, r3, #3
+	.fpu	vfpv2
 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	fmdrr	d\dr, r0, r1
+1:	vmov	d\dr, r0, r1
 	ret	lr
 	.org	1b + 8
 	.endr
 #ifdef CONFIG_VFPv3
+	.fpu	vfpv3
 	@ d16 - d31 registers
-	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:	mcrr	p11, 3, r0, r1, c\dr	@ fmdrr	r0, r1, d\dr
+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:	vmov	d\dr, r0, r1
 	ret	lr
 	.org	1b + 8
 	.endr

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:02 UTC #3 lore raw

PATCH 2/11 ARM: 8990/1: use VFP assembler mnemonics in register load/store macros

Link https://github.com/ClangBuiltLinux/linux/issues/905

From: Stefan Agner <[email protected]>

commit ee440336e5ef977c397afdb72cbf9c6b8effc8ea upstream

The integrated assembler of Clang 10 and earlier do not allow to access the VFP registers through the coprocessor load/store instructions:
<instantiation>:4:6: error: invalid operand for instruction
LDC p11, cr0, [r10],#32*4 @ FLDMIAD r10!, {d0-d15}

This has been addressed with Clang 11 [0]. However, to support earlier versions of Clang and for better readability use of VFP assembler mnemonics still is preferred.

Replace the coprocessor load/store instructions with explicit assembler mnemonics to accessing the floating point coprocessor registers. Use assembler directives to select the appropriate FPU version.

This allows to build these macros with GNU assembler as well as with Clang's built-in assembler.

[0] https://reviews.llvm.org/D59733

Link https://github.com/ClangBuiltLinux/linux/issues/905

---
 arch/arm/include/asm/vfpmacros.h | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

arch/arm/include/asm/vfpmacros.h +11 -8

index 628c336e8e3b..947ee5395e1f 100644
@@ -19,23 +19,25 @@
 
 	@ read all the working registers back into the VFP
 	.macro	VFPFLDMIA, base, tmp
+	.fpu	vfpv2
 #if __LINUX_ARM_ARCH__ < 6
-	LDC	p11, cr0, [\base],#33*4		    @ FLDMIAX \base!, {d0-d15}
+	fldmiax	\base!, {d0-d15}
 #else
-	LDC	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d0-d15}
+	vldmia	\base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+	.fpu	vfpv3
 #if __LINUX_ARM_ARCH__ <= 6
 	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
 	ldr	\tmp, [\tmp, #0]
 	tst	\tmp, #HWCAP_VFPD32
-	ldclne	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
+	vldmiane \base!, {d16-d31}
 	addeq	\base, \base, #32*4		    @ step over unused register space
 #else
 	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
 	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
 	cmp	\tmp, #2			    @ 32 x 64bit registers?
-	ldcleq	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
+	vldmiaeq \base!, {d16-d31}
 	addne	\base, \base, #32*4		    @ step over unused register space
 #endif
 #endif

@@ -44,22 +46,23 @@
 	@ write all the working registers out of the VFP
 	.macro	VFPFSTMIA, base, tmp
 #if __LINUX_ARM_ARCH__ < 6
-	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}
+	fstmiax	\base!, {d0-d15}
 #else
-	STC	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d0-d15}
+	vstmia	\base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+	.fpu	vfpv3
 #if __LINUX_ARM_ARCH__ <= 6
 	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
 	ldr	\tmp, [\tmp, #0]
 	tst	\tmp, #HWCAP_VFPD32
-	stclne	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
+	vstmiane \base!, {d16-d31}
 	addeq	\base, \base, #32*4		    @ step over unused register space
 #else
 	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
 	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
 	cmp	\tmp, #2			    @ 32 x 64bit registers?
-	stcleq	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
+	vstmiaeq \base!, {d16-d31}
 	addne	\base, \base, #32*4		    @ step over unused register space
 #endif
 #endif

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:34 UTC #4 lore raw

Patch "ARM: 8990/1: use VFP assembler mnemonics in register load/store macros" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: 8990/1: use VFP assembler mnemonics in register load/store macros

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:18 -0700
Subject: ARM: 8990/1: use VFP assembler mnemonics in register load/store macros
To: [email protected]
Cc: Stefan Agner <[email protected]>, Russell King <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Ard Biesheuvel <[email protected]>, Nick Desaulniers <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Stefan Agner <[email protected]>

commit ee440336e5ef977c397afdb72cbf9c6b8effc8ea upstream

The integrated assembler of Clang 10 and earlier do not allow to access the VFP registers through the coprocessor load/store instructions:
<instantiation>:4:6: error: invalid operand for instruction
LDC p11, cr0, [r10],#32*4 @ FLDMIAD r10!, {d0-d15}

This has been addressed with Clang 11 [0]. However, to support earlier versions of Clang and for better readability use of VFP assembler mnemonics still is preferred.

Replace the coprocessor load/store instructions with explicit assembler mnemonics to accessing the floating point coprocessor registers. Use assembler directives to select the appropriate FPU version.

This allows to build these macros with GNU assembler as well as with Clang's built-in assembler.

[0] https://reviews.llvm.org/D59733

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/include/asm/vfpmacros.h |   19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

arch/arm/include/asm/vfpmacros.h +11 -8

@@ -19,23 +19,25 @@
 
 	@ read all the working registers back into the VFP
 	.macro	VFPFLDMIA, base, tmp
+	.fpu	vfpv2
 #if __LINUX_ARM_ARCH__ < 6
-	LDC	p11, cr0, [\base],#33*4		    @ FLDMIAX \base!, {d0-d15}
+	fldmiax	\base!, {d0-d15}
 #else
-	LDC	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d0-d15}
+	vldmia	\base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+	.fpu	vfpv3
 #if __LINUX_ARM_ARCH__ <= 6
 	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
 	ldr	\tmp, [\tmp, #0]
 	tst	\tmp, #HWCAP_VFPD32
-	ldclne	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
+	vldmiane \base!, {d16-d31}
 	addeq	\base, \base, #32*4		    @ step over unused register space
 #else
 	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
 	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
 	cmp	\tmp, #2			    @ 32 x 64bit registers?
-	ldcleq	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
+	vldmiaeq \base!, {d16-d31}
 	addne	\base, \base, #32*4		    @ step over unused register space
 #endif
 #endif

@@ -44,22 +46,23 @@
 	@ write all the working registers out of the VFP
 	.macro	VFPFSTMIA, base, tmp
 #if __LINUX_ARM_ARCH__ < 6
-	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}
+	fstmiax	\base!, {d0-d15}
 #else
-	STC	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d0-d15}
+	vstmia	\base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+	.fpu	vfpv3
 #if __LINUX_ARM_ARCH__ <= 6
 	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
 	ldr	\tmp, [\tmp, #0]
 	tst	\tmp, #HWCAP_VFPD32
-	stclne	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
+	vstmiane \base!, {d16-d31}
 	addeq	\base, \base, #32*4		    @ step over unused register space
 #else
 	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
 	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
 	cmp	\tmp, #2			    @ 32 x 64bit registers?
-	stcleq	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
+	vstmiaeq \base!, {d16-d31}
 	addne	\base, \base, #32*4		    @ step over unused register space
 #endif
 #endif

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #5 lore raw

PATCH 3/11 ARM: 8971/1: replace the sole use of a symbol with its definition

Link https://github.com/ClangBuiltLinux/linux/issues/920

From: Jian Cai <[email protected]>

commit a780e485b5768e78aef087502499714901b68cc4 upstream

ALT_UP_B macro sets symbol up_b_offset via .equ to an expression involving another symbol. The macro gets expanded twice when arch/arm/kernel/sleep.S is assembled, creating a scenario where up_b_offset is set to another expression involving symbols while its current value is based on symbols. LLVM integrated assembler does not allow such cases, and based on the documentation of binutils, "Values that are based on expressions involving other symbols are allowed, but some targets may restrict this to only being done once per assembly", so it may be better to avoid such cases as it is not clearly stated which targets should support or disallow them. The fix in this case is simple, as up_b_offset has only one use, so we can replace the use with the definition and get rid of up_b_offset.

Signed-off-by Jian Cai <[email protected]>

Link https://github.com/ClangBuiltLinux/linux/issues/920

---
 arch/arm/include/asm/assembler.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

arch/arm/include/asm/assembler.h +1 -2

index 6b3e64e19fb6..70e1c23feedb 100644
@@ -279,10 +279,9 @@
 	.endif							;\
 	.popsection
 #define ALT_UP_B(label)					\
-	.equ	up_b_offset, label - 9998b			;\
 	.pushsection ".alt.smp.init", "a"			;\
 	.long	9998b						;\
-	W(b)	. + up_b_offset					;\
+	W(b)	. + (label - 9998b)					;\
 	.popsection
 #else
 #define ALT_SMP(instr...)

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:31 UTC #6 lore raw

Patch "ARM: 8971/1: replace the sole use of a symbol with its definition" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: 8971/1: replace the sole use of a symbol with its definition

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch

and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:19 -0700
Subject: ARM: 8971/1: replace the sole use of a symbol with its definition
To: [email protected]
Cc: Jian Cai <[email protected]>, Nick Desaulniers <[email protected]>, Russell King <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Ard Biesheuvel <[email protected]>, Stefan Agner <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Jian Cai <[email protected]>

commit a780e485b5768e78aef087502499714901b68cc4 upstream

ALT_UP_B macro sets symbol up_b_offset via .equ to an expression involving another symbol. The macro gets expanded twice when arch/arm/kernel/sleep.S is assembled, creating a scenario where up_b_offset is set to another expression involving symbols while its current value is based on symbols. LLVM integrated assembler does not allow such cases, and based on the documentation of binutils, "Values that are based on expressions involving other symbols are allowed, but some targets may restrict this to only being done once per assembly", so it may be better to avoid such cases as it is not clearly stated which targets should support or disallow them. The fix in this case is simple, as up_b_offset has only one use, so we can replace the use with the definition and get rid of up_b_offset.

Signed-off-by Jian Cai <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/include/asm/assembler.h |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

arch/arm/include/asm/assembler.h +1 -2

@@ -279,10 +279,9 @@
 	.endif							;\
 	.popsection
 #define ALT_UP_B(label)					\
-	.equ	up_b_offset, label - 9998b			;\
 	.pushsection ".alt.smp.init", "a"			;\
 	.long	9998b						;\
-	W(b)	. + up_b_offset					;\
+	W(b)	. + (label - 9998b)					;\
 	.popsection
 #else
 #define ALT_SMP(instr...)

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #7 lore raw

PATCH 4/11 crypto: arm/sha256-neon - avoid ADRL pseudo instruction

From: Ard Biesheuvel <[email protected]>

commit 54781938ec342cadbe2d76669ef8d3294d909974 upstream

The ADRL pseudo instruction is not an architectural construct, but a convenience macro that was supported by the ARM proprietary assembler and adopted by binutils GAS as well, but only when assembling in 32-bit ARM mode. Therefore, it can only be used in assembler code that is known to assemble in ARM mode only, but as it turns out, the Clang assembler does not implement ADRL at all, and so it is better to get rid of it entirely.

So replace the ADRL instruction with a ADR instruction that refers to a nearer symbol, and apply the delta explicitly using an additional instruction.

Signed-off-by Herbert Xu <[email protected]>

---
 arch/arm/crypto/sha256-armv4.pl       | 4 ++--
 arch/arm/crypto/sha256-core.S_shipped | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/crypto/sha256-armv4.pl +2 -2

index a03cf4dfb781..d927483985c2 100644
@@ -175,7 +175,6 @@ $code=<<___;
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -471,7 +470,8 @@ sha256_block_data_order_neon:
 	stmdb	sp!,{r4-r12,lr}
 
 	sub	$H,sp,#16*4+16
-	adrl	$Ktbl,K256
+	adr	$Ktbl,.Lsha256_block_data_order
+	sub	$Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
 	bic	$H,$H,#15		@ align for 128-bit stores
 	mov	$t2,sp
 	mov	sp,$H			@ alloca

arch/arm/crypto/sha256-core.S_shipped +2 -2

index 054aae0edfce..9deb515f3c9f 100644
@@ -56,7 +56,6 @@
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon:
 	stmdb	sp!,{r4-r12,lr}
 
 	sub	r11,sp,#16*4+16
-	adrl	r14,K256
+	adr	r14,.Lsha256_block_data_order
+	sub	r14,r14,#.Lsha256_block_data_order-K256
 	bic	r11,r11,#15		@ align for 128-bit stores
 	mov	r12,sp
 	mov	sp,r11			@ alloca

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:33 UTC #8 lore raw

Patch "crypto: arm/sha256-neon - avoid ADRL pseudo instruction" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

crypto: arm/sha256-neon - avoid ADRL pseudo instruction

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:20 -0700
Subject: crypto: arm/sha256-neon - avoid ADRL pseudo instruction
To: [email protected]
Cc: Ard Biesheuvel <[email protected]>, Nick Desaulniers <[email protected]>, Herbert Xu <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Stefan Agner <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, "Russell King (Oracle)" <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Ard Biesheuvel <[email protected]>

commit 54781938ec342cadbe2d76669ef8d3294d909974 upstream

The ADRL pseudo instruction is not an architectural construct, but a convenience macro that was supported by the ARM proprietary assembler and adopted by binutils GAS as well, but only when assembling in 32-bit ARM mode. Therefore, it can only be used in assembler code that is known to assemble in ARM mode only, but as it turns out, the Clang assembler does not implement ADRL at all, and so it is better to get rid of it entirely.

So replace the ADRL instruction with a ADR instruction that refers to a nearer symbol, and apply the delta explicitly using an additional instruction.

Signed-off-by Herbert Xu <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/crypto/sha256-armv4.pl       |    4 ++--
 arch/arm/crypto/sha256-core.S_shipped |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/crypto/sha256-armv4.pl +2 -2

@@ -175,7 +175,6 @@ $code=<<___;
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -471,7 +470,8 @@ sha256_block_data_order_neon:
 	stmdb	sp!,{r4-r12,lr}
 
 	sub	$H,sp,#16*4+16
-	adrl	$Ktbl,K256
+	adr	$Ktbl,.Lsha256_block_data_order
+	sub	$Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
 	bic	$H,$H,#15		@ align for 128-bit stores
 	mov	$t2,sp
 	mov	sp,$H			@ alloca

arch/arm/crypto/sha256-core.S_shipped +2 -2

@@ -56,7 +56,6 @@
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon:
 	stmdb	sp!,{r4-r12,lr}
 
 	sub	r11,sp,#16*4+16
-	adrl	r14,K256
+	adr	r14,.Lsha256_block_data_order
+	sub	r14,r14,#.Lsha256_block_data_order-K256
 	bic	r11,r11,#15		@ align for 128-bit stores
 	mov	r12,sp
 	mov	sp,r11			@ alloca

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #9 lore raw

PATCH 5/11 crypto: arm/sha512-neon - avoid ADRL pseudo instruction

From: Ard Biesheuvel <[email protected]>

commit 0f5e8323777bfc1c1d2cba71242db6a361de03b6 upstream

The ADRL pseudo instruction is not an architectural construct, but a convenience macro that was supported by the ARM proprietary assembler and adopted by binutils GAS as well, but only when assembling in 32-bit ARM mode. Therefore, it can only be used in assembler code that is known to assemble in ARM mode only, but as it turns out, the Clang assembler does not implement ADRL at all, and so it is better to get rid of it entirely.

So replace the ADRL instruction with a ADR instruction that refers to a nearer symbol, and apply the delta explicitly using an additional instruction.

Signed-off-by Herbert Xu <[email protected]>

---
 arch/arm/crypto/sha512-armv4.pl       | 4 ++--
 arch/arm/crypto/sha512-core.S_shipped | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/crypto/sha512-armv4.pl +2 -2

index 788c17b56ecc..2a0bdf7dd87c 100644
@@ -212,7 +212,6 @@ $code=<<___;
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -602,7 +601,8 @@ sha512_block_data_order_neon:
 	dmb				@ errata #451034 on early Cortex A8
 	add	$len,$inp,$len,lsl#7	@ len to point at the end of inp
 	VFP_ABI_PUSH
-	adrl	$Ktbl,K512
+	adr	$Ktbl,.Lsha512_block_data_order
+	sub	$Ktbl,$Ktbl,.Lsha512_block_data_order-K512
 	vldmia	$ctx,{$A-$H}		@ load context
 .Loop_neon:
 ___

arch/arm/crypto/sha512-core.S_shipped +2 -2

index 710ea309769e..cf5a7a70ff00 100644
@@ -79,7 +79,6 @@
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -543,7 +542,8 @@ sha512_block_data_order_neon:
 	dmb				@ errata #451034 on early Cortex A8
 	add	r2,r1,r2,lsl#7	@ len to point at the end of inp
 	VFP_ABI_PUSH
-	adrl	r3,K512
+	adr	r3,.Lsha512_block_data_order
+	sub	r3,r3,.Lsha512_block_data_order-K512
 	vldmia	r0,{d16-d23}		@ load context
 .Loop_neon:
 	vshr.u64	d24,d20,#14	@ 0

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:33 UTC #10 lore raw

Patch "crypto: arm/sha512-neon - avoid ADRL pseudo instruction" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

crypto: arm/sha512-neon - avoid ADRL pseudo instruction

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:21 -0700
Subject: crypto: arm/sha512-neon - avoid ADRL pseudo instruction
To: [email protected]
Cc: Ard Biesheuvel <[email protected]>, Nick Desaulniers <[email protected]>, Herbert Xu <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Stefan Agner <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, "Russell King (Oracle)" <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Ard Biesheuvel <[email protected]>

commit 0f5e8323777bfc1c1d2cba71242db6a361de03b6 upstream

The ADRL pseudo instruction is not an architectural construct, but a convenience macro that was supported by the ARM proprietary assembler and adopted by binutils GAS as well, but only when assembling in 32-bit ARM mode. Therefore, it can only be used in assembler code that is known to assemble in ARM mode only, but as it turns out, the Clang assembler does not implement ADRL at all, and so it is better to get rid of it entirely.

So replace the ADRL instruction with a ADR instruction that refers to a nearer symbol, and apply the delta explicitly using an additional instruction.

Signed-off-by Herbert Xu <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/crypto/sha512-armv4.pl       |    4 ++--
 arch/arm/crypto/sha512-core.S_shipped |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/crypto/sha512-armv4.pl +2 -2

@@ -212,7 +212,6 @@ $code=<<___;
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -602,7 +601,8 @@ sha512_block_data_order_neon:
 	dmb				@ errata #451034 on early Cortex A8
 	add	$len,$inp,$len,lsl#7	@ len to point at the end of inp
 	VFP_ABI_PUSH
-	adrl	$Ktbl,K512
+	adr	$Ktbl,.Lsha512_block_data_order
+	sub	$Ktbl,$Ktbl,.Lsha512_block_data_order-K512
 	vldmia	$ctx,{$A-$H}		@ load context
 .Loop_neon:
 ___

arch/arm/crypto/sha512-core.S_shipped +2 -2

@@ -79,7 +79,6 @@
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32

@@ -543,7 +542,8 @@ sha512_block_data_order_neon:
 	dmb				@ errata #451034 on early Cortex A8
 	add	r2,r1,r2,lsl#7	@ len to point at the end of inp
 	VFP_ABI_PUSH
-	adrl	r3,K512
+	adr	r3,.Lsha512_block_data_order
+	sub	r3,r3,.Lsha512_block_data_order-K512
 	vldmia	r0,{d16-d23}		@ load context
 .Loop_neon:
 	vshr.u64	d24,d20,#14	@ 0

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #11 lore raw

PATCH 6/11 ARM: 8933/1: replace Sun/Solaris style flag on section directive

Link https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119

From: Nick Desaulniers <[email protected]>

commit 790756c7e0229dedc83bf058ac69633045b1000e upstream

It looks like a section directive was using "Solaris style" to declare the section flags. Replace this with the GNU style so that Clang's integrated assembler can assemble this directive.

The modified instances were identified via:

$ ag \.section | grep #

Link https://github.com/ClangBuiltLinux/linux/issues/744

Link https://bugs.llvm.org/show_bug.cgi?id=43759

Link https://reviews.llvm.org/D69296

Acked-by Nicolas Pitre <[email protected]>

Reviewed-by Ard Biesheuvel <[email protected]>

Signed-off-by Nick Desaulniers <[email protected]>

Suggested-by Jian Cai <[email protected]>

Link https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119

---
 arch/arm/boot/bootp/init.S            | 2 +-
 arch/arm/boot/compressed/big-endian.S | 2 +-
 arch/arm/boot/compressed/head.S       | 2 +-
 arch/arm/boot/compressed/piggy.S      | 2 +-
 arch/arm/mm/proc-arm1020.S            | 2 +-
 arch/arm/mm/proc-arm1020e.S           | 2 +-
 arch/arm/mm/proc-arm1022.S            | 2 +-
 arch/arm/mm/proc-arm1026.S            | 2 +-
 arch/arm/mm/proc-arm720.S             | 2 +-
 arch/arm/mm/proc-arm740.S             | 2 +-
 arch/arm/mm/proc-arm7tdmi.S           | 2 +-
 arch/arm/mm/proc-arm920.S             | 2 +-
 arch/arm/mm/proc-arm922.S             | 2 +-
 arch/arm/mm/proc-arm925.S             | 2 +-
 arch/arm/mm/proc-arm926.S             | 2 +-
 arch/arm/mm/proc-arm940.S             | 2 +-
 arch/arm/mm/proc-arm946.S             | 2 +-
 arch/arm/mm/proc-arm9tdmi.S           | 2 +-
 arch/arm/mm/proc-fa526.S              | 2 +-
 arch/arm/mm/proc-feroceon.S           | 2 +-
 arch/arm/mm/proc-mohawk.S             | 2 +-
 arch/arm/mm/proc-sa110.S              | 2 +-
 arch/arm/mm/proc-sa1100.S             | 2 +-
 arch/arm/mm/proc-v6.S                 | 2 +-
 arch/arm/mm/proc-v7.S                 | 2 +-
 arch/arm/mm/proc-v7m.S                | 4 ++--
 arch/arm/mm/proc-xsc3.S               | 2 +-
 arch/arm/mm/proc-xscale.S             | 2 +-
 28 files changed, 29 insertions(+), 29 deletions(-)

arch/arm/boot/bootp/init.S +1 -1

index 5c476bd2b4ce..b562da2f7040 100644
@@ -13,7 +13,7 @@
  *  size immediately following the kernel, we could build this into
  *  a binary blob, and concatenate the zImage using the cat command.
  */
-		.section .start,#alloc,#execinstr
+		.section .start, "ax"
 		.type	_start, #function
 		.globl	_start

arch/arm/boot/compressed/big-endian.S +1 -1

index 88e2a88d324b..0e092c36da2f 100644
@@ -6,7 +6,7 @@
  *  Author: Nicolas Pitre
  */
 
-	.section ".start", #alloc, #execinstr
+	.section ".start", "ax"
 
 	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
 	orr	r0, r0, #(1 << 7)	@ enable big endian mode

arch/arm/boot/compressed/head.S +1 -1

index 0a2410adc25b..cdaf94027d3b 100644
@@ -140,7 +140,7 @@
 #endif
 		.endm
 
-		.section ".start", #alloc, #execinstr
+		.section ".start", "ax"
 /*
  * sort out different calling conventions
  */

arch/arm/boot/compressed/piggy.S +1 -1

index 0284f84dcf38..27577644ee72 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-	.section .piggydata,#alloc
+	.section .piggydata, "a"
 	.globl	input_data
 input_data:
 	.incbin	"arch/arm/boot/compressed/piggy_data"

arch/arm/mm/proc-arm1020.S +1 -1

index 4fa5371bc662..2785da387c91 100644
@@ -491,7 +491,7 @@ cpu_arm1020_name:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1020_proc_info,#object
 __arm1020_proc_info:

arch/arm/mm/proc-arm1020e.S +1 -1

index 5d8a8339e09a..e9ea237ed785 100644
@@ -449,7 +449,7 @@ arm1020e_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1020e_proc_info,#object
 __arm1020e_proc_info:

arch/arm/mm/proc-arm1022.S +1 -1

index b3dd95c345e4..920c279e7879 100644
@@ -443,7 +443,7 @@ arm1022_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1022_proc_info,#object
 __arm1022_proc_info:

arch/arm/mm/proc-arm1026.S +1 -1

index ac5afde12f35..10e21012380b 100644
@@ -437,7 +437,7 @@ arm1026_crval:
 	string	cpu_arm1026_name, "ARM1026EJ-S"
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1026_proc_info,#object
 __arm1026_proc_info:

arch/arm/mm/proc-arm720.S +1 -1

index c99d24363f32..39361e196d61 100644
@@ -172,7 +172,7 @@ arm720_crval:
  * See <asm/procinfo.h> for a definition of this structure.
  */
 	
-		.section ".proc.info.init", #alloc
+		.section ".proc.info.init", "a"
 
 .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
 		.type	__\name\()_proc_info,#object

arch/arm/mm/proc-arm740.S +1 -1

index 1b4a3838393f..1a94bbf6e53f 100644
@@ -128,7 +128,7 @@ __arm740_setup:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 	.type	__arm740_proc_info,#object
 __arm740_proc_info:
 	.long	0x41807400

arch/arm/mm/proc-arm7tdmi.S +1 -1

index 17a4687065c7..52b66cf0259e 100644
@@ -72,7 +72,7 @@ __arm7tdmi_setup:
 
 		.align
 
-		.section ".proc.info.init", #alloc
+		.section ".proc.info.init", "a"
 
 .macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
 	extra_hwcaps=0

arch/arm/mm/proc-arm920.S +1 -1

index 298c76b47749..31ac8acc34dc 100644
@@ -434,7 +434,7 @@ arm920_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm920_proc_info,#object
 __arm920_proc_info:

arch/arm/mm/proc-arm922.S +1 -1

index 824be3a0bc23..ca2c7ca8af21 100644
@@ -412,7 +412,7 @@ arm922_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm922_proc_info,#object
 __arm922_proc_info:

arch/arm/mm/proc-arm925.S +1 -1

index d40cff8f102c..a381a0c9f109 100644
@@ -477,7 +477,7 @@ arm925_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-arm926.S +1 -1

index f3cd08f353f0..3188ab2bac61 100644
@@ -460,7 +460,7 @@ arm926_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm926_proc_info,#object
 __arm926_proc_info:

arch/arm/mm/proc-arm940.S +1 -1

index 1c26d991386d..4b8a00220cc9 100644
@@ -340,7 +340,7 @@ __arm940_setup:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm940_proc_info,#object
 __arm940_proc_info:

arch/arm/mm/proc-arm946.S +1 -1

index 2dc1c75a4fd4..555becf9c758 100644
@@ -395,7 +395,7 @@ __arm946_setup:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 	.type	__arm946_proc_info,#object
 __arm946_proc_info:
 	.long	0x41009460

arch/arm/mm/proc-arm9tdmi.S +1 -1

index 913c06e590af..ef517530130b 100644
@@ -66,7 +66,7 @@ __arm9tdmi_setup:
 
 		.align
 
-		.section ".proc.info.init", #alloc
+		.section ".proc.info.init", "a"
 
 .macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
 		.type	__\name\()_proc_info, #object

arch/arm/mm/proc-fa526.S +1 -1

index 8120b6f4dbb8..dddf833fe000 100644
@@ -185,7 +185,7 @@ fa526_cr1_set:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__fa526_proc_info,#object
 __fa526_proc_info:

arch/arm/mm/proc-feroceon.S +1 -1

index bb6dc34d42a3..b12b76bc8d30 100644
@@ -571,7 +571,7 @@ feroceon_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-mohawk.S +1 -1

index f08308578885..d47d6c5cee63 100644
@@ -416,7 +416,7 @@ mohawk_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__88sv331x_proc_info,#object
 __88sv331x_proc_info:

arch/arm/mm/proc-sa110.S +1 -1

index d5bc5d702563..baba503ba816 100644
@@ -196,7 +196,7 @@ sa110_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__sa110_proc_info,#object
 __sa110_proc_info:

arch/arm/mm/proc-sa1100.S +1 -1

index be7b611c76c7..75ebacc8e4e5 100644
@@ -239,7 +239,7 @@ sa1100_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-v6.S +1 -1

index c1c85eb3484f..1dd0d5ca27da 100644
@@ -261,7 +261,7 @@ v6_crval:
 	string	cpu_elf_name, "v6"
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	/*
 	 * Match any ARMv6 processor core.

arch/arm/mm/proc-v7.S +1 -1

index c4e8006a1a8c..48e0ef6f0dcc 100644
@@ -644,7 +644,7 @@ __v7_setup_stack:
 	string	cpu_elf_name, "v7"
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	/*
 	 * Standard v7 proc info content

arch/arm/mm/proc-v7m.S +2 -2

index 1a49d503eafc..84459c1d31b8 100644
@@ -93,7 +93,7 @@ ENTRY(cpu_cm7_proc_fin)
 	ret	lr
 ENDPROC(cpu_cm7_proc_fin)
 
-	.section ".init.text", #alloc, #execinstr
+	.section ".init.text", "ax"
 
 __v7m_cm7_setup:
 	mov	r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)

@@ -177,7 +177,7 @@ ENDPROC(__v7m_setup)
 	string cpu_elf_name "v7m"
 	string cpu_v7m_name "ARMv7-M"
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
 	.long	0			/* proc_info_list.__cpu_mm_mmu_flags */

arch/arm/mm/proc-xsc3.S +1 -1

index 1ac0fbbe9f12..42eaecc43cfe 100644
@@ -496,7 +496,7 @@ xsc3_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-xscale.S +1 -1

index bdb2b7749b03..18ac5a1f8922 100644
@@ -610,7 +610,7 @@ xscale_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
 	.type	__\name\()_proc_info,#object

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:31 UTC #12 lore raw

Patch "ARM: 8933/1: replace Sun/Solaris style flag on section directive" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: 8933/1: replace Sun/Solaris style flag on section directive

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:22 -0700
Subject: ARM: 8933/1: replace Sun/Solaris style flag on section directive
To: [email protected]
Cc: Nick Desaulniers <[email protected]>, Nicolas Pitre <[email protected]>, Ard Biesheuvel <[email protected]>, Stefan Agner <[email protected]>, Fangrui Song <[email protected]>, Jian Cai <[email protected]>, Peter Smith <[email protected]>, Russell King <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Andre Przywara <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin
<[email protected]>
Message-ID: <[email protected]>

From: Nick Desaulniers <[email protected]>

commit 790756c7e0229dedc83bf058ac69633045b1000e upstream

It looks like a section directive was using "Solaris style" to declare the section flags. Replace this with the GNU style so that Clang's integrated assembler can assemble this directive.

The modified instances were identified via:

$ ag \.section | grep #

Link https://github.com/ClangBuiltLinux/linux/issues/744

Link https://bugs.llvm.org/show_bug.cgi?id=43759

Link https://reviews.llvm.org/D69296

Acked-by Nicolas Pitre <[email protected]>

Reviewed-by Ard Biesheuvel <[email protected]>

Signed-off-by Nick Desaulniers <[email protected]>

Suggested-by Jian Cai <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/boot/bootp/init.S            |    2 +-
 arch/arm/boot/compressed/big-endian.S |    2 +-
 arch/arm/boot/compressed/head.S       |    2 +-
 arch/arm/boot/compressed/piggy.S      |    2 +-
 arch/arm/mm/proc-arm1020.S            |    2 +-
 arch/arm/mm/proc-arm1020e.S           |    2 +-
 arch/arm/mm/proc-arm1022.S            |    2 +-
 arch/arm/mm/proc-arm1026.S            |    2 +-
 arch/arm/mm/proc-arm720.S             |    2 +-
 arch/arm/mm/proc-arm740.S             |    2 +-
 arch/arm/mm/proc-arm7tdmi.S           |    2 +-
 arch/arm/mm/proc-arm920.S             |    2 +-
 arch/arm/mm/proc-arm922.S             |    2 +-
 arch/arm/mm/proc-arm925.S             |    2 +-
 arch/arm/mm/proc-arm926.S             |    2 +-
 arch/arm/mm/proc-arm940.S             |    2 +-
 arch/arm/mm/proc-arm946.S             |    2 +-
 arch/arm/mm/proc-arm9tdmi.S           |    2 +-
 arch/arm/mm/proc-fa526.S              |    2 +-
 arch/arm/mm/proc-feroceon.S           |    2 +-
 arch/arm/mm/proc-mohawk.S             |    2 +-
 arch/arm/mm/proc-sa110.S              |    2 +-
 arch/arm/mm/proc-sa1100.S             |    2 +-
 arch/arm/mm/proc-v6.S                 |    2 +-
 arch/arm/mm/proc-v7.S                 |    2 +-
 arch/arm/mm/proc-v7m.S                |    4 ++--
 arch/arm/mm/proc-xsc3.S               |    2 +-
 arch/arm/mm/proc-xscale.S             |    2 +-
 28 files changed, 29 insertions(+), 29 deletions(-)

arch/arm/boot/bootp/init.S +1 -1

@@ -13,7 +13,7 @@
  *  size immediately following the kernel, we could build this into
  *  a binary blob, and concatenate the zImage using the cat command.
  */
-		.section .start,#alloc,#execinstr
+		.section .start, "ax"
 		.type	_start, #function
 		.globl	_start

arch/arm/boot/compressed/big-endian.S +1 -1

@@ -6,7 +6,7 @@
  *  Author: Nicolas Pitre
  */
 
-	.section ".start", #alloc, #execinstr
+	.section ".start", "ax"
 
 	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
 	orr	r0, r0, #(1 << 7)	@ enable big endian mode

arch/arm/boot/compressed/head.S +1 -1

@@ -140,7 +140,7 @@
 #endif
 		.endm
 
-		.section ".start", #alloc, #execinstr
+		.section ".start", "ax"
 /*
  * sort out different calling conventions
  */

arch/arm/boot/compressed/piggy.S +1 -1

@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-	.section .piggydata,#alloc
+	.section .piggydata, "a"
 	.globl	input_data
 input_data:
 	.incbin	"arch/arm/boot/compressed/piggy_data"

arch/arm/mm/proc-arm1020.S +1 -1

@@ -491,7 +491,7 @@ cpu_arm1020_name:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1020_proc_info,#object
 __arm1020_proc_info:

arch/arm/mm/proc-arm1020e.S +1 -1

@@ -449,7 +449,7 @@ arm1020e_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1020e_proc_info,#object
 __arm1020e_proc_info:

arch/arm/mm/proc-arm1022.S +1 -1

@@ -443,7 +443,7 @@ arm1022_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1022_proc_info,#object
 __arm1022_proc_info:

arch/arm/mm/proc-arm1026.S +1 -1

@@ -437,7 +437,7 @@ arm1026_crval:
 	string	cpu_arm1026_name, "ARM1026EJ-S"
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm1026_proc_info,#object
 __arm1026_proc_info:

arch/arm/mm/proc-arm720.S +1 -1

@@ -172,7 +172,7 @@ arm720_crval:
  * See <asm/procinfo.h> for a definition of this structure.
  */
 	
-		.section ".proc.info.init", #alloc
+		.section ".proc.info.init", "a"
 
 .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
 		.type	__\name\()_proc_info,#object

arch/arm/mm/proc-arm740.S +1 -1

@@ -128,7 +128,7 @@ __arm740_setup:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 	.type	__arm740_proc_info,#object
 __arm740_proc_info:
 	.long	0x41807400

arch/arm/mm/proc-arm7tdmi.S +1 -1

@@ -72,7 +72,7 @@ __arm7tdmi_setup:
 
 		.align
 
-		.section ".proc.info.init", #alloc
+		.section ".proc.info.init", "a"
 
 .macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
 	extra_hwcaps=0

arch/arm/mm/proc-arm920.S +1 -1

@@ -434,7 +434,7 @@ arm920_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm920_proc_info,#object
 __arm920_proc_info:

arch/arm/mm/proc-arm922.S +1 -1

@@ -412,7 +412,7 @@ arm922_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm922_proc_info,#object
 __arm922_proc_info:

arch/arm/mm/proc-arm925.S +1 -1

@@ -477,7 +477,7 @@ arm925_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-arm926.S +1 -1

@@ -460,7 +460,7 @@ arm926_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm926_proc_info,#object
 __arm926_proc_info:

arch/arm/mm/proc-arm940.S +1 -1

@@ -340,7 +340,7 @@ __arm940_setup:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__arm940_proc_info,#object
 __arm940_proc_info:

arch/arm/mm/proc-arm946.S +1 -1

@@ -395,7 +395,7 @@ __arm946_setup:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 	.type	__arm946_proc_info,#object
 __arm946_proc_info:
 	.long	0x41009460

arch/arm/mm/proc-arm9tdmi.S +1 -1

@@ -66,7 +66,7 @@ __arm9tdmi_setup:
 
 		.align
 
-		.section ".proc.info.init", #alloc
+		.section ".proc.info.init", "a"
 
 .macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
 		.type	__\name\()_proc_info, #object

arch/arm/mm/proc-fa526.S +1 -1

@@ -185,7 +185,7 @@ fa526_cr1_set:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__fa526_proc_info,#object
 __fa526_proc_info:

arch/arm/mm/proc-feroceon.S +1 -1

@@ -571,7 +571,7 @@ feroceon_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-mohawk.S +1 -1

@@ -416,7 +416,7 @@ mohawk_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__88sv331x_proc_info,#object
 __88sv331x_proc_info:

arch/arm/mm/proc-sa110.S +1 -1

@@ -196,7 +196,7 @@ sa110_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	.type	__sa110_proc_info,#object
 __sa110_proc_info:

arch/arm/mm/proc-sa1100.S +1 -1

@@ -239,7 +239,7 @@ sa1100_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-v6.S +1 -1

@@ -261,7 +261,7 @@ v6_crval:
 	string	cpu_elf_name, "v6"
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	/*
 	 * Match any ARMv6 processor core.

arch/arm/mm/proc-v7.S +1 -1

@@ -644,7 +644,7 @@ __v7_setup_stack:
 	string	cpu_elf_name, "v7"
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 	/*
 	 * Standard v7 proc info content

arch/arm/mm/proc-v7m.S +2 -2

@@ -93,7 +93,7 @@ ENTRY(cpu_cm7_proc_fin)
 	ret	lr
 ENDPROC(cpu_cm7_proc_fin)
 
-	.section ".init.text", #alloc, #execinstr
+	.section ".init.text", "ax"
 
 __v7m_cm7_setup:
 	mov	r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)

@@ -177,7 +177,7 @@ ENDPROC(__v7m_setup)
 	string cpu_elf_name "v7m"
 	string cpu_v7m_name "ARMv7-M"
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
 	.long	0			/* proc_info_list.__cpu_mm_mmu_flags */

arch/arm/mm/proc-xsc3.S +1 -1

@@ -496,7 +496,7 @@ xsc3_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
 	.type	__\name\()_proc_info,#object

arch/arm/mm/proc-xscale.S +1 -1

@@ -610,7 +610,7 @@ xscale_crval:
 
 	.align
 
-	.section ".proc.info.init", #alloc
+	.section ".proc.info.init", "a"
 
 .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
 	.type	__\name\()_proc_info,#object

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #13 lore raw

PATCH 7/11 ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand

[0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076

From: Stefan Agner <[email protected]>

commit 9f1984c6ae30e2a379751339ce3375a21099b5d4 upstream

LLVM's integrated assembler does not accept r15 as mrc operand.
arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache

Use APSR_nzcv instead of r15. The GNU assembler supports this syntax since binutils 2.21 [0].

[0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076

---
 arch/arm/boot/compressed/head.S | 2 +-
 arch/arm/mm/proc-arm1026.S      | 4 ++--
 arch/arm/mm/proc-arm926.S       | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

arch/arm/boot/compressed/head.S +1 -1

index cdaf94027d3b..17f87f4c74f5 100644
@@ -1274,7 +1274,7 @@ iflush:
 __armv5tej_mmu_cache_flush:
 		tst	r4, #1
 		movne	pc, lr
-1:		mrc	p15, 0, r15, c7, c14, 3	@ test,clean,invalidate D cache
+1:		mrc	p15, 0, APSR_nzcv, c7, c14, 3	@ test,clean,invalidate D cache
 		bne	1b
 		mcr	p15, 0, r0, c7, c5, 0	@ flush I cache
 		mcr	p15, 0, r0, c7, c10, 4	@ drain WB

arch/arm/mm/proc-arm1026.S +2 -2

index 10e21012380b..0bdf25a95b10 100644
@@ -138,7 +138,7 @@ ENTRY(arm1026_flush_kern_cache_all)
 	mov	ip, #0
 __flush_whole_cache:
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate
 	bne	1b
 #endif
 	tst	r2, #VM_EXEC

@@ -363,7 +363,7 @@ ENTRY(cpu_arm1026_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r1, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate
 	bne	1b
 #endif
 #ifndef CONFIG_CPU_ICACHE_DISABLE

arch/arm/mm/proc-arm926.S +2 -2

index 3188ab2bac61..1ba253c2bce1 100644
@@ -131,7 +131,7 @@ __flush_whole_cache:
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
 #else
-1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
 	bne	1b
 #endif
 	tst	r2, #VM_EXEC

@@ -358,7 +358,7 @@ ENTRY(cpu_arm926_switch_mm)
 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
 #else
 @ && 'Clean & Invalidate whole DCache'
-1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
 	bne	1b
 #endif
 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:31 UTC #14 lore raw

Patch "ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch

and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:23 -0700
Subject: ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand
To: [email protected]
Cc: Stefan Agner <[email protected]>, Russell King <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Ard Biesheuvel <[email protected]>, Nick Desaulniers <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Stefan Agner <[email protected]>

commit 9f1984c6ae30e2a379751339ce3375a21099b5d4 upstream

LLVM's integrated assembler does not accept r15 as mrc operand.
arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache

Use APSR_nzcv instead of r15. The GNU assembler supports this syntax since binutils 2.21 [0].

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/boot/compressed/head.S |    2 +-
 arch/arm/mm/proc-arm1026.S      |    4 ++--
 arch/arm/mm/proc-arm926.S       |    4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

arch/arm/boot/compressed/head.S +1 -1

@@ -1274,7 +1274,7 @@ iflush:
 __armv5tej_mmu_cache_flush:
 		tst	r4, #1
 		movne	pc, lr
-1:		mrc	p15, 0, r15, c7, c14, 3	@ test,clean,invalidate D cache
+1:		mrc	p15, 0, APSR_nzcv, c7, c14, 3	@ test,clean,invalidate D cache
 		bne	1b
 		mcr	p15, 0, r0, c7, c5, 0	@ flush I cache
 		mcr	p15, 0, r0, c7, c10, 4	@ drain WB

arch/arm/mm/proc-arm1026.S +2 -2

@@ -138,7 +138,7 @@ ENTRY(arm1026_flush_kern_cache_all)
 	mov	ip, #0
 __flush_whole_cache:
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate
 	bne	1b
 #endif
 	tst	r2, #VM_EXEC

@@ -363,7 +363,7 @@ ENTRY(cpu_arm1026_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r1, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate
 	bne	1b
 #endif
 #ifndef CONFIG_CPU_ICACHE_DISABLE

arch/arm/mm/proc-arm926.S +2 -2

@@ -131,7 +131,7 @@ __flush_whole_cache:
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
 #else
-1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
 	bne	1b
 #endif
 	tst	r2, #VM_EXEC

@@ -358,7 +358,7 @@ ENTRY(cpu_arm926_switch_mm)
 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
 #else
 @ && 'Clean & Invalidate whole DCache'
-1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
 	bne	1b
 #endif
 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #15 lore raw

PATCH 8/11 ARM: OMAP2+: drop unnecessary adrl

Link https://github.com/ClangBuiltLinux/linux/issues/430

From: Stefan Agner <[email protected]>

commit d85d5247885ef2e8192287b895c2e381fa931b0b upstream

The adrl instruction has been introduced with commit dd31394779aa ("ARM:
omap3: Thumb-2 compatibility for sleep34xx.S"), back when this assembly file was considerably longer. Today adr seems to have enough reach, even when inserting about 60 instructions between the use site and the label. Replace adrl with conventional adr instruction.

This allows to build this file using Clang's integrated assembler (which does not support the adrl pseudo instruction).

Signed-off-by Tony Lindgren <[email protected]>

Link https://github.com/ClangBuiltLinux/linux/issues/430

---
 arch/arm/mach-omap2/sleep34xx.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/mach-omap2/sleep34xx.S +1 -1

index ac1324c6453b..c4e97d35c310 100644
@@ -72,7 +72,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
 	stmfd	sp!, {lr}	@ save registers on stack
 	/* Setup so that we will disable and enable l2 */
 	mov	r1, #0x1
-	adrl	r3, l2dis_3630_offset	@ may be too distant for plain adr
+	adr	r3, l2dis_3630_offset
 	ldr	r2, [r3]		@ value for offset
 	str	r1, [r2, r3]		@ write to l2dis_3630
 	ldmfd	sp!, {pc}	@ restore regs and return

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:32 UTC #16 lore raw

Patch "ARM: OMAP2+: drop unnecessary adrl" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: OMAP2+: drop unnecessary adrl

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-omap2-drop-unnecessary-adrl.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:24 -0700
Subject: ARM: OMAP2+: drop unnecessary adrl
To: [email protected]
Cc: Stefan Agner <[email protected]>, Tony Lindgren <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Hans Ulli Kroll <[email protected]>, Ard Biesheuvel <[email protected]>, Nick Desaulniers <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, "Russell King (Oracle)" <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Stefan Agner <[email protected]>

commit d85d5247885ef2e8192287b895c2e381fa931b0b upstream

The adrl instruction has been introduced with commit dd31394779aa ("ARM:
omap3: Thumb-2 compatibility for sleep34xx.S"), back when this assembly file was considerably longer. Today adr seems to have enough reach, even when inserting about 60 instructions between the use site and the label. Replace adrl with conventional adr instruction.

This allows to build this file using Clang's integrated assembler (which does not support the adrl pseudo instruction).

Signed-off-by Tony Lindgren <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/mach-omap2/sleep34xx.S |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/mach-omap2/sleep34xx.S +1 -1

@@ -72,7 +72,7 @@ ENTRY(enable_omap3630_toggle_l2_on_resto
 	stmfd	sp!, {lr}	@ save registers on stack
 	/* Setup so that we will disable and enable l2 */
 	mov	r1, #0x1
-	adrl	r3, l2dis_3630_offset	@ may be too distant for plain adr
+	adr	r3, l2dis_3630_offset
 	ldr	r2, [r3]		@ value for offset
 	str	r1, [r2, r3]		@ write to l2dis_3630
 	ldmfd	sp!, {pc}	@ restore regs and return

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #17 lore raw

PATCH 9/11 ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler

Link https://github.com/ClangBuiltLinux/linux/issues/975

From: Jian Cai <[email protected]>

commit 3c9f5708b7aed6a963e2aefccbd1854802de163e upstream

This patch replaces 6 IWMMXT instructions Clang's integrated assembler does not support in iwmmxt.S using macros, while making sure GNU assembler still emit the same instructions. This should be easier than providing full IWMMXT support in Clang. This is one of the last bits of kernel code that could be compiled but not assembled with clang. Once all of it works with IAS, we no longer need to special-case 32-bit Arm in Kbuild, or turn off CONFIG_IWMMXT when build-testing.

"Intel Wireless MMX Technology - Developer Guide - August, 2002" should be referenced for the encoding schemes of these extensions.

Signed-off-by Jian Cai <[email protected]>

Link https://github.com/ClangBuiltLinux/linux/issues/975

---
 arch/arm/kernel/iwmmxt.S | 89 ++++++++++++++++++++--------------------
 arch/arm/kernel/iwmmxt.h | 47 +++++++++++++++++++++
 2 files changed, 92 insertions(+), 44 deletions(-)
 create mode 100644 arch/arm/kernel/iwmmxt.h

arch/arm/kernel/iwmmxt.S +45 ~~-44~~

index 0dcae787b004..d2b4ac06e4ed 100644
@@ -16,6 +16,7 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 #include <asm/assembler.h>
+#include "iwmmxt.h"
 
 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 #define PJ4(code...)		code

@@ -113,33 +114,33 @@ concan_save:
 
 concan_dump:
 
-	wstrw	wCSSF, [r1, #MMX_WCSSF]
-	wstrw	wCASF, [r1, #MMX_WCASF]
-	wstrw	wCGR0, [r1, #MMX_WCGR0]
-	wstrw	wCGR1, [r1, #MMX_WCGR1]
-	wstrw	wCGR2, [r1, #MMX_WCGR2]
-	wstrw	wCGR3, [r1, #MMX_WCGR3]
+	wstrw	wCSSF, r1, MMX_WCSSF
+	wstrw	wCASF, r1, MMX_WCASF
+	wstrw	wCGR0, r1, MMX_WCGR0
+	wstrw	wCGR1, r1, MMX_WCGR1
+	wstrw	wCGR2, r1, MMX_WCGR2
+	wstrw	wCGR3, r1, MMX_WCGR3
 
 1:	@ MUP? wRn
 	tst	r2, #0x2
 	beq	2f
 
-	wstrd	wR0,  [r1, #MMX_WR0]
-	wstrd	wR1,  [r1, #MMX_WR1]
-	wstrd	wR2,  [r1, #MMX_WR2]
-	wstrd	wR3,  [r1, #MMX_WR3]
-	wstrd	wR4,  [r1, #MMX_WR4]
-	wstrd	wR5,  [r1, #MMX_WR5]
-	wstrd	wR6,  [r1, #MMX_WR6]
-	wstrd	wR7,  [r1, #MMX_WR7]
-	wstrd	wR8,  [r1, #MMX_WR8]
-	wstrd	wR9,  [r1, #MMX_WR9]
-	wstrd	wR10, [r1, #MMX_WR10]
-	wstrd	wR11, [r1, #MMX_WR11]
-	wstrd	wR12, [r1, #MMX_WR12]
-	wstrd	wR13, [r1, #MMX_WR13]
-	wstrd	wR14, [r1, #MMX_WR14]
-	wstrd	wR15, [r1, #MMX_WR15]
+	wstrd	wR0,  r1, MMX_WR0
+	wstrd	wR1,  r1, MMX_WR1
+	wstrd	wR2,  r1, MMX_WR2
+	wstrd	wR3,  r1, MMX_WR3
+	wstrd	wR4,  r1, MMX_WR4
+	wstrd	wR5,  r1, MMX_WR5
+	wstrd	wR6,  r1, MMX_WR6
+	wstrd	wR7,  r1, MMX_WR7
+	wstrd	wR8,  r1, MMX_WR8
+	wstrd	wR9,  r1, MMX_WR9
+	wstrd	wR10, r1, MMX_WR10
+	wstrd	wR11, r1, MMX_WR11
+	wstrd	wR12, r1, MMX_WR12
+	wstrd	wR13, r1, MMX_WR13
+	wstrd	wR14, r1, MMX_WR14
+	wstrd	wR15, r1, MMX_WR15
 
 2:	teq	r0, #0				@ anything to load?
 	reteq	lr				@ if not, return

@@ -147,30 +148,30 @@ concan_dump:
 concan_load:
 
 	@ Load wRn
-	wldrd	wR0,  [r0, #MMX_WR0]
-	wldrd	wR1,  [r0, #MMX_WR1]
-	wldrd	wR2,  [r0, #MMX_WR2]
-	wldrd	wR3,  [r0, #MMX_WR3]
-	wldrd	wR4,  [r0, #MMX_WR4]
-	wldrd	wR5,  [r0, #MMX_WR5]
-	wldrd	wR6,  [r0, #MMX_WR6]
-	wldrd	wR7,  [r0, #MMX_WR7]
-	wldrd	wR8,  [r0, #MMX_WR8]
-	wldrd	wR9,  [r0, #MMX_WR9]
-	wldrd	wR10, [r0, #MMX_WR10]
-	wldrd	wR11, [r0, #MMX_WR11]
-	wldrd	wR12, [r0, #MMX_WR12]
-	wldrd	wR13, [r0, #MMX_WR13]
-	wldrd	wR14, [r0, #MMX_WR14]
-	wldrd	wR15, [r0, #MMX_WR15]
+	wldrd	wR0,  r0, MMX_WR0
+	wldrd	wR1,  r0, MMX_WR1
+	wldrd	wR2,  r0, MMX_WR2
+	wldrd	wR3,  r0, MMX_WR3
+	wldrd	wR4,  r0, MMX_WR4
+	wldrd	wR5,  r0, MMX_WR5
+	wldrd	wR6,  r0, MMX_WR6
+	wldrd	wR7,  r0, MMX_WR7
+	wldrd	wR8,  r0, MMX_WR8
+	wldrd	wR9,  r0, MMX_WR9
+	wldrd	wR10, r0, MMX_WR10
+	wldrd	wR11, r0, MMX_WR11
+	wldrd	wR12, r0, MMX_WR12
+	wldrd	wR13, r0, MMX_WR13
+	wldrd	wR14, r0, MMX_WR14
+	wldrd	wR15, r0, MMX_WR15
 
 	@ Load wCx
-	wldrw	wCSSF, [r0, #MMX_WCSSF]
-	wldrw	wCASF, [r0, #MMX_WCASF]
-	wldrw	wCGR0, [r0, #MMX_WCGR0]
-	wldrw	wCGR1, [r0, #MMX_WCGR1]
-	wldrw	wCGR2, [r0, #MMX_WCGR2]
-	wldrw	wCGR3, [r0, #MMX_WCGR3]
+	wldrw	wCSSF, r0, MMX_WCSSF
+	wldrw	wCASF, r0, MMX_WCASF
+	wldrw	wCGR0, r0, MMX_WCGR0
+	wldrw	wCGR1, r0, MMX_WCGR1
+	wldrw	wCGR2, r0, MMX_WCGR2
+	wldrw	wCGR3, r0, MMX_WCGR3
 
 	@ clear CUP/MUP (only if r1 != 0)
 	teq	r1, #0

arch/arm/kernel/iwmmxt.h new file +47 -0

47 lines not on this page · raw message

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:32 UTC #18 lore raw

Patch "ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:25 -0700
Subject: ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler
To: [email protected]
Cc: Jian Cai <[email protected]>, Nick Desaulniers <[email protected]>, Ard Biesheuvel <[email protected]>, Russell King <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, Herbert Xu <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Stefan Agner <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Jian Cai <[email protected]>

commit 3c9f5708b7aed6a963e2aefccbd1854802de163e upstream

This patch replaces 6 IWMMXT instructions Clang's integrated assembler does not support in iwmmxt.S using macros, while making sure GNU assembler still emit the same instructions. This should be easier than providing full IWMMXT support in Clang. This is one of the last bits of kernel code that could be compiled but not assembled with clang. Once all of it works with IAS, we no longer need to special-case 32-bit Arm in Kbuild, or turn off CONFIG_IWMMXT when build-testing.

"Intel Wireless MMX Technology - Developer Guide - August, 2002" should be referenced for the encoding schemes of these extensions.

Signed-off-by Jian Cai <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/kernel/iwmmxt.S |   89 +++++++++++++++++++++++------------------------
 arch/arm/kernel/iwmmxt.h |   47 ++++++++++++++++++++++++
 2 files changed, 92 insertions(+), 44 deletions(-)
 create mode 100644 arch/arm/kernel/iwmmxt.h

arch/arm/kernel/iwmmxt.S +45 ~~-44~~

@@ -16,6 +16,7 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 #include <asm/assembler.h>
+#include "iwmmxt.h"
 
 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 #define PJ4(code...)		code

@@ -113,33 +114,33 @@ concan_save:
 
 concan_dump:
 
-	wstrw	wCSSF, [r1, #MMX_WCSSF]
-	wstrw	wCASF, [r1, #MMX_WCASF]
-	wstrw	wCGR0, [r1, #MMX_WCGR0]
-	wstrw	wCGR1, [r1, #MMX_WCGR1]
-	wstrw	wCGR2, [r1, #MMX_WCGR2]
-	wstrw	wCGR3, [r1, #MMX_WCGR3]
+	wstrw	wCSSF, r1, MMX_WCSSF
+	wstrw	wCASF, r1, MMX_WCASF
+	wstrw	wCGR0, r1, MMX_WCGR0
+	wstrw	wCGR1, r1, MMX_WCGR1
+	wstrw	wCGR2, r1, MMX_WCGR2
+	wstrw	wCGR3, r1, MMX_WCGR3
 
 1:	@ MUP? wRn
 	tst	r2, #0x2
 	beq	2f
 
-	wstrd	wR0,  [r1, #MMX_WR0]
-	wstrd	wR1,  [r1, #MMX_WR1]
-	wstrd	wR2,  [r1, #MMX_WR2]
-	wstrd	wR3,  [r1, #MMX_WR3]
-	wstrd	wR4,  [r1, #MMX_WR4]
-	wstrd	wR5,  [r1, #MMX_WR5]
-	wstrd	wR6,  [r1, #MMX_WR6]
-	wstrd	wR7,  [r1, #MMX_WR7]
-	wstrd	wR8,  [r1, #MMX_WR8]
-	wstrd	wR9,  [r1, #MMX_WR9]
-	wstrd	wR10, [r1, #MMX_WR10]
-	wstrd	wR11, [r1, #MMX_WR11]
-	wstrd	wR12, [r1, #MMX_WR12]
-	wstrd	wR13, [r1, #MMX_WR13]
-	wstrd	wR14, [r1, #MMX_WR14]
-	wstrd	wR15, [r1, #MMX_WR15]
+	wstrd	wR0,  r1, MMX_WR0
+	wstrd	wR1,  r1, MMX_WR1
+	wstrd	wR2,  r1, MMX_WR2
+	wstrd	wR3,  r1, MMX_WR3
+	wstrd	wR4,  r1, MMX_WR4
+	wstrd	wR5,  r1, MMX_WR5
+	wstrd	wR6,  r1, MMX_WR6
+	wstrd	wR7,  r1, MMX_WR7
+	wstrd	wR8,  r1, MMX_WR8
+	wstrd	wR9,  r1, MMX_WR9
+	wstrd	wR10, r1, MMX_WR10
+	wstrd	wR11, r1, MMX_WR11
+	wstrd	wR12, r1, MMX_WR12
+	wstrd	wR13, r1, MMX_WR13
+	wstrd	wR14, r1, MMX_WR14
+	wstrd	wR15, r1, MMX_WR15
 
 2:	teq	r0, #0				@ anything to load?
 	reteq	lr				@ if not, return

@@ -147,30 +148,30 @@ concan_dump:
 concan_load:
 
 	@ Load wRn
-	wldrd	wR0,  [r0, #MMX_WR0]
-	wldrd	wR1,  [r0, #MMX_WR1]
-	wldrd	wR2,  [r0, #MMX_WR2]
-	wldrd	wR3,  [r0, #MMX_WR3]
-	wldrd	wR4,  [r0, #MMX_WR4]
-	wldrd	wR5,  [r0, #MMX_WR5]
-	wldrd	wR6,  [r0, #MMX_WR6]
-	wldrd	wR7,  [r0, #MMX_WR7]
-	wldrd	wR8,  [r0, #MMX_WR8]
-	wldrd	wR9,  [r0, #MMX_WR9]
-	wldrd	wR10, [r0, #MMX_WR10]
-	wldrd	wR11, [r0, #MMX_WR11]
-	wldrd	wR12, [r0, #MMX_WR12]
-	wldrd	wR13, [r0, #MMX_WR13]
-	wldrd	wR14, [r0, #MMX_WR14]
-	wldrd	wR15, [r0, #MMX_WR15]
+	wldrd	wR0,  r0, MMX_WR0
+	wldrd	wR1,  r0, MMX_WR1
+	wldrd	wR2,  r0, MMX_WR2
+	wldrd	wR3,  r0, MMX_WR3
+	wldrd	wR4,  r0, MMX_WR4
+	wldrd	wR5,  r0, MMX_WR5
+	wldrd	wR6,  r0, MMX_WR6
+	wldrd	wR7,  r0, MMX_WR7
+	wldrd	wR8,  r0, MMX_WR8
+	wldrd	wR9,  r0, MMX_WR9
+	wldrd	wR10, r0, MMX_WR10
+	wldrd	wR11, r0, MMX_WR11
+	wldrd	wR12, r0, MMX_WR12
+	wldrd	wR13, r0, MMX_WR13
+	wldrd	wR14, r0, MMX_WR14
+	wldrd	wR15, r0, MMX_WR15
 
 	@ Load wCx
-	wldrw	wCSSF, [r0, #MMX_WCSSF]
-	wldrw	wCASF, [r0, #MMX_WCASF]
-	wldrw	wCGR0, [r0, #MMX_WCGR0]
-	wldrw	wCGR1, [r0, #MMX_WCGR1]
-	wldrw	wCGR2, [r0, #MMX_WCGR2]
-	wldrw	wCGR3, [r0, #MMX_WCGR3]
+	wldrw	wCSSF, r0, MMX_WCSSF
+	wldrw	wCASF, r0, MMX_WCASF
+	wldrw	wCGR0, r0, MMX_WCGR0
+	wldrw	wCGR1, r0, MMX_WCGR1
+	wldrw	wCGR2, r0, MMX_WCGR2
+	wldrw	wCGR3, r0, MMX_WCGR3
 
 	@ clear CUP/MUP (only if r1 != 0)
 	teq	r1, #0

arch/arm/kernel/iwmmxt.h new file +47 -0

47 lines not on this page · raw message

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #19 lore raw

PATCH 10/11 crypto: arm - use Kconfig based compiler checks for crypto opcodes

From: Ard Biesheuvel <[email protected]>

commit b4d0c0aad57ac3bd1b5141bac5ab1ab1d5e442b3 upstream

Instead of allowing the Crypto Extensions algorithms to be selected when using a toolchain that does not support them, and complain about it at build time, use the information we have about the compiler to prevent them from being selected in the first place. Users that are stuck with a GCC version <4.8 are unlikely to care about these routines anyway, and it cleans up the Makefile considerably.

While at it, add explicit 'armv8-a' CPU specifiers to the code that uses the 'crypto-neon-fp-armv8' FPU specifier so we don't regress Clang, which will complain about this in version 10 and later.

Signed-off-by Herbert Xu <[email protected]>

---
 arch/arm/crypto/Kconfig             | 14 +++++++------
 arch/arm/crypto/Makefile            | 32 ++++++-----------------------
 arch/arm/crypto/crct10dif-ce-core.S |  2 +-
 arch/arm/crypto/ghash-ce-core.S     |  1 +
 arch/arm/crypto/sha1-ce-core.S      |  1 +
 arch/arm/crypto/sha2-ce-core.S      |  1 +
 6 files changed, 18 insertions(+), 33 deletions(-)

arch/arm/crypto/Kconfig +8 -6

index 043b0b18bf7e..f747caea10ff 100644
@@ -30,7 +30,7 @@ config CRYPTO_SHA1_ARM_NEON
 
 config CRYPTO_SHA1_ARM_CE
 	tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_SHA1_ARM
 	select CRYPTO_HASH
 	help

@@ -39,7 +39,7 @@ config CRYPTO_SHA1_ARM_CE
 
 config CRYPTO_SHA2_ARM_CE
 	tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_SHA256_ARM
 	select CRYPTO_HASH
 	help

@@ -96,7 +96,7 @@ config CRYPTO_AES_ARM_BS
 
 config CRYPTO_AES_ARM_CE
 	tristate "Accelerated AES using ARMv8 Crypto Extensions"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_BLKCIPHER
 	select CRYPTO_LIB_AES
 	select CRYPTO_SIMD

@@ -106,7 +106,7 @@ config CRYPTO_AES_ARM_CE
 
 config CRYPTO_GHASH_ARM_CE
 	tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_HASH
 	select CRYPTO_CRYPTD
 	select CRYPTO_GF128MUL

@@ -118,12 +118,14 @@ config CRYPTO_GHASH_ARM_CE
 
 config CRYPTO_CRCT10DIF_ARM_CE
 	tristate "CRCT10DIF digest algorithm using PMULL instructions"
-	depends on KERNEL_MODE_NEON && CRC_T10DIF
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+	depends on CRC_T10DIF
 	select CRYPTO_HASH
 
 config CRYPTO_CRC32_ARM_CE
 	tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
-	depends on KERNEL_MODE_NEON && CRC32
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+	depends on CRC32
 	select CRYPTO_HASH
 
 config CRYPTO_CHACHA20_NEON

arch/arm/crypto/Makefile +6 ~~-26~~

index 4180f3a13512..c0d36771a693 100644
@@ -12,32 +12,12 @@ obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
 obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
 obj-$(CONFIG_CRYPTO_NHPOLY1305_NEON) += nhpoly1305-neon.o
 
-ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
-crc-obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
-
-ifneq ($(crc-obj-y)$(crc-obj-m),)
-ifeq ($(call as-instr,.arch armv8-a\n.arch_extension crc,y,n),y)
-ce-obj-y += $(crc-obj-y)
-ce-obj-m += $(crc-obj-m)
-else
-$(warning These CRC Extensions modules need binutils 2.23 or higher)
-$(warning $(crc-obj-y) $(crc-obj-m))
-endif
-endif
-
-ifneq ($(ce-obj-y)$(ce-obj-m),)
-ifeq ($(call as-instr,.fpu crypto-neon-fp-armv8,y,n),y)
-obj-y += $(ce-obj-y)
-obj-m += $(ce-obj-m)
-else
-$(warning These ARMv8 Crypto Extensions modules need binutils 2.23 or higher)
-$(warning $(ce-obj-y) $(ce-obj-m))
-endif
-endif
+obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
+obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
+obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
+obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
+obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
+obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
 
 aes-arm-y	:= aes-cipher-core.o aes-cipher-glue.o
 aes-arm-bs-y	:= aes-neonbs-core.o aes-neonbs-glue.o

arch/arm/crypto/crct10dif-ce-core.S +1 -1

index 86be258a803f..46c02c518a30 100644
@@ -72,7 +72,7 @@
 #endif
 
 	.text
-	.arch		armv7-a
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	init_crc	.req	r0

arch/arm/crypto/ghash-ce-core.S +1 -0

index c47fe81abcb0..534c9647726d 100644
@@ -88,6 +88,7 @@
 	T3_H		.req	d17
 
 	.text
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	.macro		__pmull_p64, rd, rn, rm, b1, b2, b3, b4

arch/arm/crypto/sha1-ce-core.S +1 -0

index 49a74a441aec..8a702e051738 100644
@@ -10,6 +10,7 @@
 #include <asm/assembler.h>
 
 	.text
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	k0		.req	q0

arch/arm/crypto/sha2-ce-core.S +1 -0

index 4ad517577e23..b6369d2440a1 100644
@@ -10,6 +10,7 @@
 #include <asm/assembler.h>
 
 	.text
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	k0		.req	q7

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:33 UTC #20 lore raw

Patch "crypto: arm - use Kconfig based compiler checks for crypto opcodes" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

crypto: arm - use Kconfig based compiler checks for crypto opcodes

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:26 -0700
Subject: crypto: arm - use Kconfig based compiler checks for crypto opcodes
To: [email protected]
Cc: Ard Biesheuvel <[email protected]>, Herbert Xu <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Ard Biesheuvel <[email protected]>, Stefan Agner <[email protected]>, Nick Desaulniers <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, "Russell King (Oracle)" <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Ard Biesheuvel <[email protected]>

commit b4d0c0aad57ac3bd1b5141bac5ab1ab1d5e442b3 upstream

Instead of allowing the Crypto Extensions algorithms to be selected when using a toolchain that does not support them, and complain about it at build time, use the information we have about the compiler to prevent them from being selected in the first place. Users that are stuck with a GCC version <4.8 are unlikely to care about these routines anyway, and it cleans up the Makefile considerably.

While at it, add explicit 'armv8-a' CPU specifiers to the code that uses the 'crypto-neon-fp-armv8' FPU specifier so we don't regress Clang, which will complain about this in version 10 and later.

Signed-off-by Herbert Xu <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/crypto/Kconfig             |   14 ++++++++------
 arch/arm/crypto/Makefile            |   32 ++++++--------------------------
 arch/arm/crypto/crct10dif-ce-core.S |    2 +-
 arch/arm/crypto/ghash-ce-core.S     |    1 +
 arch/arm/crypto/sha1-ce-core.S      |    1 +
 arch/arm/crypto/sha2-ce-core.S      |    1 +
 6 files changed, 18 insertions(+), 33 deletions(-)

arch/arm/crypto/Kconfig +8 -6

@@ -30,7 +30,7 @@ config CRYPTO_SHA1_ARM_NEON
 
 config CRYPTO_SHA1_ARM_CE
 	tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_SHA1_ARM
 	select CRYPTO_HASH
 	help

@@ -39,7 +39,7 @@ config CRYPTO_SHA1_ARM_CE
 
 config CRYPTO_SHA2_ARM_CE
 	tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_SHA256_ARM
 	select CRYPTO_HASH
 	help

@@ -96,7 +96,7 @@ config CRYPTO_AES_ARM_BS
 
 config CRYPTO_AES_ARM_CE
 	tristate "Accelerated AES using ARMv8 Crypto Extensions"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_BLKCIPHER
 	select CRYPTO_LIB_AES
 	select CRYPTO_SIMD

@@ -106,7 +106,7 @@ config CRYPTO_AES_ARM_CE
 
 config CRYPTO_GHASH_ARM_CE
 	tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions"
-	depends on KERNEL_MODE_NEON
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
 	select CRYPTO_HASH
 	select CRYPTO_CRYPTD
 	select CRYPTO_GF128MUL

@@ -118,12 +118,14 @@ config CRYPTO_GHASH_ARM_CE
 
 config CRYPTO_CRCT10DIF_ARM_CE
 	tristate "CRCT10DIF digest algorithm using PMULL instructions"
-	depends on KERNEL_MODE_NEON && CRC_T10DIF
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+	depends on CRC_T10DIF
 	select CRYPTO_HASH
 
 config CRYPTO_CRC32_ARM_CE
 	tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
-	depends on KERNEL_MODE_NEON && CRC32
+	depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+	depends on CRC32
 	select CRYPTO_HASH
 
 config CRYPTO_CHACHA20_NEON

arch/arm/crypto/Makefile +6 ~~-26~~

@@ -12,32 +12,12 @@ obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha51
 obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
 obj-$(CONFIG_CRYPTO_NHPOLY1305_NEON) += nhpoly1305-neon.o
 
-ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
-crc-obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
-
-ifneq ($(crc-obj-y)$(crc-obj-m),)
-ifeq ($(call as-instr,.arch armv8-a\n.arch_extension crc,y,n),y)
-ce-obj-y += $(crc-obj-y)
-ce-obj-m += $(crc-obj-m)
-else
-$(warning These CRC Extensions modules need binutils 2.23 or higher)
-$(warning $(crc-obj-y) $(crc-obj-m))
-endif
-endif
-
-ifneq ($(ce-obj-y)$(ce-obj-m),)
-ifeq ($(call as-instr,.fpu crypto-neon-fp-armv8,y,n),y)
-obj-y += $(ce-obj-y)
-obj-m += $(ce-obj-m)
-else
-$(warning These ARMv8 Crypto Extensions modules need binutils 2.23 or higher)
-$(warning $(ce-obj-y) $(ce-obj-m))
-endif
-endif
+obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
+obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
+obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
+obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
+obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
+obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
 
 aes-arm-y	:= aes-cipher-core.o aes-cipher-glue.o
 aes-arm-bs-y	:= aes-neonbs-core.o aes-neonbs-glue.o

arch/arm/crypto/crct10dif-ce-core.S +1 -1

@@ -72,7 +72,7 @@
 #endif
 
 	.text
-	.arch		armv7-a
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	init_crc	.req	r0

arch/arm/crypto/ghash-ce-core.S +1 -0

@@ -88,6 +88,7 @@
 	T3_H		.req	d17
 
 	.text
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	.macro		__pmull_p64, rd, rn, rm, b1, b2, b3, b4

arch/arm/crypto/sha1-ce-core.S +1 -0

@@ -10,6 +10,7 @@
 #include <asm/assembler.h>
 
 	.text
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	k0		.req	q0

arch/arm/crypto/sha2-ce-core.S +1 -0

@@ -10,6 +10,7 @@
 #include <asm/assembler.h>
 
 	.text
+	.arch		armv8-a
 	.fpu		crypto-neon-fp-armv8
 
 	k0		.req	q7

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Florian Fainelli

author

2022-06-29 18:03 UTC #21 lore raw

PATCH 11/11 crypto: arm/ghash-ce - define fpu before fpu registers are referenced

From: Stefan Agner <[email protected]>

commit 7548bf8c17d84607c106bd45d81834afd95a2edb upstream

Building ARMv7 with Clang's integrated assembler leads to errors such as:
arch/arm/crypto/ghash-ce-core.S:34:11: error: register name expected
t3l .req d16

Since no FPU has selected yet Clang considers d16 not a valid register. Moving the FPU directive on-top allows Clang to parse the registers and allows to successfully build this file with Clang's integrated assembler.

Signed-off-by Herbert Xu <[email protected]>

---
 arch/arm/crypto/ghash-ce-core.S | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/arm/crypto/ghash-ce-core.S +3 -2

index 534c9647726d..9f51e3fa4526 100644
@@ -8,6 +8,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+	.arch		armv8-a
+	.fpu		crypto-neon-fp-armv8
+
 	SHASH		.req	q0
 	T1		.req	q1
 	XL		.req	q2

@@ -88,8 +91,6 @@
 	T3_H		.req	d17
 
 	.text
-	.arch		armv8-a
-	.fpu		crypto-neon-fp-armv8
 
 	.macro		__pmull_p64, rd, rn, rm, b1, b2, b3, b4
 	vmull.p64	\rd, \rn, \rm

Signature · 1 line

2.25.1

[email protected]

maintainer Applied

2022-06-30 13:32 UTC #22 lore raw

Patch "crypto: arm/ghash-ce - define fpu before fpu registers are referenced" has been added to the 5.4-stable tree

This is a note to let you know that I've just added the patch titled

crypto: arm/ghash-ce - define fpu before fpu registers are referenced

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <[email protected]>
Date: Wed, 29 Jun 2022 11:02:27 -0700
Subject: crypto: arm/ghash-ce - define fpu before fpu registers are referenced
To: [email protected]
Cc: Stefan Agner <[email protected]>, Nick Desaulniers <[email protected]>, Ard Biesheuvel <[email protected]>, Herbert Xu <[email protected]>, Florian Fainelli <[email protected]>, Russell King <[email protected]>, "David S. Miller" <[email protected]>, Tony Lindgren <[email protected]>, Hans Ulli Kroll <[email protected]>, Nicolas Pitre <[email protected]>, Andre Przywara <[email protected]>, "Russell King (Oracle)" <[email protected]>, Greg Kroah-Hartman <[email protected]>, Catalin Marinas <[email protected]>, Jian Cai <[email protected]>, [email protected] (moderated list:ARM PORT), [email protected] (open list), [email protected] (open list:CRYPTO API), [email protected] (open list:OMAP2+ SUPPORT), [email protected] (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <[email protected]>
Message-ID: <[email protected]>

From: Stefan Agner <[email protected]>

commit 7548bf8c17d84607c106bd45d81834afd95a2edb upstream

Building ARMv7 with Clang's integrated assembler leads to errors such as:
arch/arm/crypto/ghash-ce-core.S:34:11: error: register name expected
t3l .req d16

Since no FPU has selected yet Clang considers d16 not a valid register. Moving the FPU directive on-top allows Clang to parse the registers and allows to successfully build this file with Clang's integrated assembler.

Signed-off-by Herbert Xu <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/arm/crypto/ghash-ce-core.S |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/arm/crypto/ghash-ce-core.S +3 -2

@@ -8,6 +8,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+	.arch		armv8-a
+	.fpu		crypto-neon-fp-armv8
+
 	SHASH		.req	q0
 	T1		.req	q1
 	XL		.req	q2

@@ -88,8 +91,6 @@
 	T3_H		.req	d17
 
 	.text
-	.arch		armv8-a
-	.fpu		crypto-neon-fp-armv8
 
 	.macro		__pmull_p64, rd, rn, rm, b1, b2, b3, b4
 	vmull.p64	\rd, \rn, \rm

Patches currently in stable-queue which might be from [email protected] are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch queue-5.4/arm-omap2-drop-unnecessary-adrl.patch queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Greg Kroah-Hartman

maintainer

2022-06-30 13:29 UTC #23 lore raw