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Drivers for Alibaba YCC (Yitian Cryptography Complex) cryptographic accelerator

PATCH Superseded 'Guanjun' 2 participants 12 messages Sep 28, 2022 – Oct 21, 2022 Crypto API

v2 of 3 Superseded Latest is v3 →

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'Guanjun'

author
#0 lore raw

v2 cover Drivers for Alibaba YCC (Yitian Cryptography Complex) cryptographic accelerator

From: Guanjun <[email protected]>

Hi,

This patch series aims to add drivers for Alibaba YCC (Yitian Cryptography Complex) cryptographic accelerator. Enables the on-chip cryptographic accelerator of Alibaba Yitian SoCs which is based on ARMv9 architecture.

It includes PCIe enabling, skcipher, aead, rsa, sm2 support.

Please help to review.

Thanks,
Guanjun.

Change log:
v1 RESEND -> v2:
- [01/09] Remove char device that is not used now.

v1 -> v1 RESEND:
- [01/09] Adjust the Kconfig entry in alphabetical order
- [05/09][07/09][08/09] Adjust the format of algorithm names

v1: https://lore.kernel.org/all/[email protected]/
v1 RESEND: https://lore.kernel.org/all/[email protected]/

Guanjun (3):
crypto/ycc: Add skcipher algorithm support
crypto/ycc: Add aead algorithm support
crypto/ycc: Add rsa algorithm support

Xuchun Shang (1):
crypto/ycc: Add sm2 algorithm support

Zelin Deng (5):
crypto/ycc: Add YCC (Yitian Cryptography Complex) accelerator driver crypto/ycc: Add ycc ring configuration
crypto/ycc: Add irq support for ycc kernel rings crypto/ycc: Add device error handling support for ycc hw errors
MAINTAINERS: Add Yitian Cryptography Complex (YCC) driver maintainer
entry

 MAINTAINERS                            |   8 +
 drivers/crypto/Kconfig                 |   2 +
 drivers/crypto/Makefile                |   1 +
 drivers/crypto/ycc/Kconfig             |  18 +
 drivers/crypto/ycc/Makefile            |   4 +
 drivers/crypto/ycc/sm2signature_asn1.c |  38 ++
 drivers/crypto/ycc/sm2signature_asn1.h |  13 +
 drivers/crypto/ycc/ycc_aead.c          | 646 ++++++++++++++++++++++
 drivers/crypto/ycc/ycc_algs.h          | 176 ++++++
 drivers/crypto/ycc/ycc_dev.h           | 157 ++++++
 drivers/crypto/ycc/ycc_drv.c           | 567 ++++++++++++++++++++
 drivers/crypto/ycc/ycc_isr.c           | 279 ++++++++++
 drivers/crypto/ycc/ycc_isr.h           |  12 +
 drivers/crypto/ycc/ycc_pke.c           | 944 +++++++++++++++++++++++++++++++++
 drivers/crypto/ycc/ycc_ring.c          | 652 +++++++++++++++++++++++
 drivers/crypto/ycc/ycc_ring.h          | 168 ++++++
 drivers/crypto/ycc/ycc_ske.c           | 925 ++++++++++++++++++++++++++++++++
 17 files changed, 4610 insertions(+)
 create mode 100644 drivers/crypto/ycc/Kconfig
 create mode 100644 drivers/crypto/ycc/Makefile
 create mode 100644 drivers/crypto/ycc/sm2signature_asn1.c
 create mode 100644 drivers/crypto/ycc/sm2signature_asn1.h
 create mode 100644 drivers/crypto/ycc/ycc_aead.c
 create mode 100644 drivers/crypto/ycc/ycc_algs.h
 create mode 100644 drivers/crypto/ycc/ycc_dev.h
 create mode 100644 drivers/crypto/ycc/ycc_drv.c
 create mode 100644 drivers/crypto/ycc/ycc_isr.c
 create mode 100644 drivers/crypto/ycc/ycc_isr.h
 create mode 100644 drivers/crypto/ycc/ycc_pke.c
 create mode 100644 drivers/crypto/ycc/ycc_ring.c
 create mode 100644 drivers/crypto/ycc/ycc_ring.h
 create mode 100644 drivers/crypto/ycc/ycc_ske.c
Signature · 1 line
1.8.3.1
author
#1 lore raw

PATCH v2 1/9 crypto/ycc: Add YCC (Yitian Cryptography Complex) accelerator driver

From: Zelin Deng <[email protected]>

YCC (Yitian Cryptography Complex) is designed to accelerate the process of encryption and decryption. Yitian is the name of Alibaba SoCs which is based on ARMv9 architecture.

This patch aims to add driver with basic pci settings and irq requests.

---
 drivers/crypto/Kconfig       |   2 +
 drivers/crypto/Makefile      |   1 +
 drivers/crypto/ycc/Kconfig   |   8 +
 drivers/crypto/ycc/Makefile  |   3 +
 drivers/crypto/ycc/ycc_dev.h | 148 +++++++++++++++
 drivers/crypto/ycc/ycc_drv.c | 444 +++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/ycc/ycc_isr.c | 117 ++++++++++++
 drivers/crypto/ycc/ycc_isr.h |  12 ++
 8 files changed, 735 insertions(+)
 create mode 100644 drivers/crypto/ycc/Kconfig
 create mode 100644 drivers/crypto/ycc/Makefile
 create mode 100644 drivers/crypto/ycc/ycc_dev.h
 create mode 100644 drivers/crypto/ycc/ycc_drv.c
 create mode 100644 drivers/crypto/ycc/ycc_isr.c
 create mode 100644 drivers/crypto/ycc/ycc_isr.h
drivers/crypto/Kconfig +2 -0
index 3e6aa31..2140a3f 100644
@@ -819,4 +819,6 @@ config CRYPTO_DEV_SA2UL
 
 source "drivers/crypto/keembay/Kconfig"
 
+source "drivers/crypto/ycc/Kconfig"
+
 endif # CRYPTO_HW
drivers/crypto/Makefile +1 -0
index f81703a8..0ba29dd 100644
@@ -51,4 +51,5 @@ obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
 obj-y += xilinx/
 obj-y += hisilicon/
 obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
+obj-$(CONFIG_CRYPTO_DEV_YCC) += ycc/
 obj-y += keembay/
drivers/crypto/ycc/Kconfig new file +8 -0
new file mode 100644
index 00000000..6e88ecb
@@ -0,0 +1,8 @@
+config CRYPTO_DEV_YCC
+	tristate "Support for Alibaba YCC cryptographic accelerator"
+	depends on CRYPTO && CRYPTO_HW && PCI
+	default n
+	help
+	  Enables the driver for the on-chip cryptographic accelerator of
+	  Alibaba Yitian SoCs which is based on ARMv9 architecture.
+	  If unsure say N.
drivers/crypto/ycc/Makefile new file +3 -0
new file mode 100644
index 00000000..7065273
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
+ycc-objs := ycc_drv.o ycc_isr.o
drivers/crypto/ycc/ycc_dev.h new file +148 -0

148 lines not on this page · raw message

drivers/crypto/ycc/ycc_drv.c new file +444 -0

444 lines not on this page · raw message

drivers/crypto/ycc/ycc_isr.c new file +117 -0

117 lines not on this page · raw message

drivers/crypto/ycc/ycc_isr.h new file +12 -0
new file mode 100644
index 00000000..8318a6f
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __YCC_ISR_H
+
+#include "ycc_dev.h"
+
+int ycc_enable_msix(struct ycc_dev *ydev);
+void ycc_disable_msix(struct ycc_dev *ydev);
+int ycc_alloc_irqs(struct ycc_dev *ydev);
+void ycc_free_irqs(struct ycc_dev *ydev);
+int ycc_init_global_err(struct ycc_dev *ydev);
+void ycc_deinit_global_err(struct ycc_dev *ydev);
+#endif
Signature · 1 line
1.8.3.1
maintainer
#2 lore raw

Re: [PATCH v2 1/9] crypto/ycc: Add YCC (Yitian Cryptography Complex) accelerator driver

drivers/crypto/ycc/Makefile line 3

Quoted 10 lines · Guanjun
drivers/crypto/ycc/Makefile new file +3 -0
new file mode 100644
index 00000000..7065273
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
+ycc-objs := ycc_drv.o ycc_isr.o

This doesn't even compile. When I fixed that it generates loads of warnings with sparse turned on. Please fix them all before you resubmit.

Thanks,

Signature · 3 lines
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
author
#3 lore raw

PATCH v2 2/9 crypto/ycc: Add ycc ring configuration

In reply to 'Guanjun'

From: Zelin Deng <[email protected]>

There're 2 types of functional rings, kernel ring and user ring. All kernel rings must be initialized in kernel driver while user rings are not supported now.

---
 drivers/crypto/ycc/Makefile   |   2 +-
 drivers/crypto/ycc/ycc_dev.h  |   6 +
 drivers/crypto/ycc/ycc_drv.c  |  59 ++++-
 drivers/crypto/ycc/ycc_isr.c  |   7 +
 drivers/crypto/ycc/ycc_ring.c | 562 ++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/ycc/ycc_ring.h | 111 +++++++++
 6 files changed, 745 insertions(+), 2 deletions(-)
 create mode 100644 drivers/crypto/ycc/ycc_ring.c
 create mode 100644 drivers/crypto/ycc/ycc_ring.h
drivers/crypto/ycc/Makefile +1 -1
index 7065273..61d17bd 100644
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
-ycc-objs := ycc_drv.o ycc_isr.o
+ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o
drivers/crypto/ycc/ycc_dev.h +6 -0
index e5f76af..dda82b0 100644
@@ -104,10 +104,16 @@ struct ycc_dev {
 	struct ycc_bar ycc_bars[4];
 	struct ycc_dev *assoc_dev;
 
+	int max_desc;
+	int user_rings;
 	bool is_polling;
 	unsigned long status;
 	struct workqueue_struct *dev_err_q;
 	char err_irq_name[32];
+
+	struct ycc_ring *rings;
+	unsigned long ring_bitmap;
+
 	struct work_struct work;
 	char *msi_name[48];
 	struct dentry *debug_dir;
drivers/crypto/ycc/ycc_drv.c +58 -1

128 lines not on this page · raw message

drivers/crypto/ycc/ycc_isr.c +7 -0
index f2f751c..cd2a2d7 100644
@@ -38,6 +38,13 @@ static irqreturn_t ycc_g_err_isr(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+/*
+ * TODO: will implement when ycc ring actually work.
+ */
+void ycc_resp_process(uintptr_t ring_addr)
+{
+}
+
 int ycc_enable_msix(struct ycc_dev *ydev)
 {
 	struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev;
drivers/crypto/ycc/ycc_ring.c new file +562 -0

562 lines not on this page · raw message

drivers/crypto/ycc/ycc_ring.h new file +111 -0

111 lines not on this page · raw message

Signature · 1 line
1.8.3.1
author
#4 lore raw

PATCH v2 3/9 crypto/ycc: Add irq support for ycc kernel rings

In reply to 'Guanjun'

From: Zelin Deng <[email protected]>

Each kernel ring has its own command done irq. Temporarily user rings will not enable irq.

---
 drivers/crypto/ycc/ycc_isr.c | 92 ++++++++++++++++++++++++++++++++++++++------
 1 file changed, 80 insertions(+), 12 deletions(-)
drivers/crypto/ycc/ycc_isr.c +80 -12
index cd2a2d7..a86c8d7 100644
@@ -12,6 +12,17 @@
 #include <linux/interrupt.h>
 
 #include "ycc_isr.h"
+#include "ycc_dev.h"
+#include "ycc_ring.h"
+
+
+static irqreturn_t ycc_resp_isr(int irq, void *data)
+{
+	struct ycc_ring *ring = (struct ycc_ring *)data;
+
+	tasklet_hi_schedule(&ring->resp_handler);
+	return IRQ_HANDLED;
+}
 
 /*
  * TODO: will implement when ycc ring actually work.
@@ -38,11 +49,13 @@ static irqreturn_t ycc_g_err_isr(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-/*
- * TODO: will implement when ycc ring actually work.
- */
 void ycc_resp_process(uintptr_t ring_addr)
 {
+	struct ycc_ring *ring = (struct ycc_ring *)ring_addr;
+
+	ycc_dequeue(ring);
+	if (ring->ydev->is_polling)
+		tasklet_hi_schedule(&ring->resp_handler);
 }
 
 int ycc_enable_msix(struct ycc_dev *ydev)
@@ -83,34 +96,89 @@ static void ycc_cleanup_global_err_workqueue(struct ycc_dev *ydev)
 		destroy_workqueue(ydev->dev_err_q);
 }
 
-/*
- * TODO: Just request irq for global err. Irq for each ring
- * will be requested when ring actually work.
- */
 int ycc_alloc_irqs(struct ycc_dev *ydev)
 {
 	struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev;
 	int num = ydev->is_vf ? 1 : YCC_RINGPAIR_NUM;
-	int ret;
+	int cpu, cpus = num_online_cpus();
+	int ret, i, j;
 
+	/* The 0 - (YCC_RINGPAIR_NUM-1) are rings irqs, the last one is dev error irq */
 	sprintf(ydev->err_irq_name, "ycc_dev_%d_global_err", ydev->id);
 	ret = request_irq(pci_irq_vector(rcec_pdev, num),
 			  ycc_g_err_isr, 0, ydev->err_irq_name, ydev);
-	if (ret)
+	if (ret) {
 		pr_err("Failed to alloc global irq interrupt for dev: %d\n", ydev->id);
+		goto out;
+	}
+
+	if (ydev->is_polling)
+		goto out;
+
+	for (i = 0; i < num; i++) {
+		if (ydev->rings[i].type != KERN_RING)
+			continue;
+
+		ydev->msi_name[i] = kzalloc(16, GFP_KERNEL);
+		if (!ydev->msi_name[i])
+			goto free_irq;
+		snprintf(ydev->msi_name[i], 16, "ycc_ring_%d", i);
+		ret = request_irq(pci_irq_vector(rcec_pdev, i), ycc_resp_isr,
+				  0, ydev->msi_name[i], &ydev->rings[i]);
+		if (ret) {
+			kfree(ydev->msi_name[i]);
+			goto free_irq;
+		}
+		if (!ydev->is_vf)
+			cpu = (i % YCC_RINGPAIR_NUM) % cpus;
+		else
+			cpu = smp_processor_id() % cpus;
+
+		ret = irq_set_affinity_hint(pci_irq_vector(rcec_pdev, i),
+					    get_cpu_mask(cpu));
+		if (ret) {
+			free_irq(pci_irq_vector(rcec_pdev, i), &ydev->rings[i]);
+			kfree(ydev->msi_name[i]);
+			goto free_irq;
+		}
+	}
+
+	return 0;
+
+free_irq:
+	for (j = 0; j < i; j++) {
+		if (ydev->rings[i].type != KERN_RING)
+			continue;
+
+		free_irq(pci_irq_vector(rcec_pdev, j), &ydev->rings[j]);
+		kfree(ydev->msi_name[j]);
+	}
+	free_irq(pci_irq_vector(rcec_pdev, num), ydev);
+out:
 
 	return ret;
 }
 
-/*
- * TODO: Same as the allocate action.
- */
 void ycc_free_irqs(struct ycc_dev *ydev)
 {
 	struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev;
 	int num = ydev->is_vf ? 1 : YCC_RINGPAIR_NUM;
+	int i;
 
+	/* Free device err irq */
 	free_irq(pci_irq_vector(rcec_pdev, num), ydev);
+
+	if (ydev->is_polling)
+		return;
+
+	for (i = 0; i < num; i++) {
+		if (ydev->rings[i].type != KERN_RING)
+			continue;
+
+		irq_set_affinity_hint(pci_irq_vector(rcec_pdev, i), NULL);
+		free_irq(pci_irq_vector(rcec_pdev, i), &ydev->rings[i]);
+		kfree(ydev->msi_name[i]);
+	}
 }
 
 int ycc_init_global_err(struct ycc_dev *ydev)
Signature · 1 line
1.8.3.1
author
#5 lore raw

PATCH v2 4/9 crypto/ycc: Add device error handling support for ycc hw errors

In reply to 'Guanjun'

From: Zelin Deng <[email protected]>

Due to ycc hardware limitations, in REE ycc device cannot be reset to recover from fatal error (reset register is only valid in TEE and PCIE FLR only reset queue pointers but not ycc hw), regard all hw errors except queue error as fatal error.

---
 drivers/crypto/ycc/ycc_isr.c  | 93 +++++++++++++++++++++++++++++++++++++++++--
 drivers/crypto/ycc/ycc_ring.c | 90 +++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/ycc/ycc_ring.h |  3 ++
 3 files changed, 183 insertions(+), 3 deletions(-)
drivers/crypto/ycc/ycc_isr.c +90 -3
index a86c8d7..28f8918 100644
@@ -15,6 +15,8 @@
 #include "ycc_dev.h"
 #include "ycc_ring.h"
 
+extern void ycc_clear_cmd_ring(struct ycc_ring *ring);
+extern void ycc_clear_resp_ring(struct ycc_ring *ring);
 
 static irqreturn_t ycc_resp_isr(int irq, void *data)
 {
@@ -24,11 +26,93 @@ static irqreturn_t ycc_resp_isr(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-/*
- * TODO: will implement when ycc ring actually work.
- */
+static void ycc_fatal_error(struct ycc_dev *ydev)
+{
+	struct ycc_ring *ring;
+	int i;
+
+	for (i = 0; i < YCC_RINGPAIR_NUM; i++) {
+		ring = ydev->rings + i;
+
+		if (ring->type != KERN_RING)
+			continue;
+
+		spin_lock_bh(&ring->lock);
+		ycc_clear_cmd_ring(ring);
+		spin_unlock_bh(&ring->lock);
+
+		ycc_clear_resp_ring(ring);
+	}
+}
+
 static void ycc_process_global_err(struct work_struct *work)
 {
+	struct ycc_dev *ydev = container_of(work, struct ycc_dev, work);
+	struct ycc_bar *cfg_bar = &ydev->ycc_bars[YCC_SEC_CFG_BAR];
+	struct ycc_ring *ring;
+	u32 hclk_err, xclk_err;
+	u32 xclk_ecc_uncor_err_0, xclk_ecc_uncor_err_1;
+	u32 hclk_ecc_uncor_err;
+	int i;
+
+	if (pci_wait_for_pending_transaction(ydev->pdev))
+		pr_warn("Failed to pending transaction\n");
+
+	hclk_err = YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_HCLK_INT_STATUS);
+	xclk_err = YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_XCLK_INT_STATUS);
+	xclk_ecc_uncor_err_0 = YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_XCLK_MEM_ECC_UNCOR_0);
+	xclk_ecc_uncor_err_1 = YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_XCLK_MEM_ECC_UNCOR_1);
+	hclk_ecc_uncor_err = YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_HCLK_MEM_ECC_UNCOR);
+
+	if ((hclk_err & ~(YCC_HCLK_TRNG_ERR)) || xclk_err || hclk_ecc_uncor_err) {
+		pr_err("Got uncorrected error, must be reset\n");
+		/*
+		 * Fatal error, as ycc cannot be reset in REE, clear ring data.
+		 */
+		return ycc_fatal_error(ydev);
+	}
+
+	if (xclk_ecc_uncor_err_0 || xclk_ecc_uncor_err_1) {
+		pr_err("Got algorithm ECC error: %x, %x\n",
+			xclk_ecc_uncor_err_0, xclk_ecc_uncor_err_1);
+		return ycc_fatal_error(ydev);
+	}
+
+	/* This has to be queue error. Handling command rings. */
+	for (i = 0; i < YCC_RINGPAIR_NUM; i++) {
+		ring = ydev->rings + i;
+
+		if (ring->type != KERN_RING)
+			continue;
+
+		ring->status = YCC_CSR_RD(ring->csr_vaddr, REG_RING_STATUS);
+		if (ring->status) {
+			pr_err("YCC: Dev: %d, Ring: %d got ring err: %x\n",
+				ydev->id, ring->ring_id, ring->status);
+			spin_lock_bh(&ring->lock);
+			ycc_clear_cmd_ring(ring);
+			spin_unlock_bh(&ring->lock);
+		}
+	}
+
+	/*
+	 * Give HW a chance to process all pending_cmds
+	 * through recovering transactions.
+	 */
+	pci_set_master(ydev->pdev);
+
+	for (i = 0; i < YCC_RINGPAIR_NUM; i++) {
+		ring = ydev->rings + i;
+
+		if (ring->type != KERN_RING || !ring->status)
+			continue;
+
+		ycc_clear_resp_ring(ring);
+	}
+
+	ycc_g_err_unmask(cfg_bar->vaddr);
+	clear_bit(YDEV_STATUS_ERR, &ydev->status);
+	set_bit(YDEV_STATUS_READY, &ydev->status);
 }
 
 static irqreturn_t ycc_g_err_isr(int irq, void *data)
@@ -45,6 +129,9 @@ static irqreturn_t ycc_g_err_isr(int irq, void *data)
 
 	clear_bit(YDEV_STATUS_READY, &ydev->status);
 
+	/* Disable YCC mastering, no new transactions */
+	pci_clear_master(ydev->pdev);
+
 	schedule_work(&ydev->work);
 	return IRQ_HANDLED;
 }
drivers/crypto/ycc/ycc_ring.c +90 -0

99 lines not on this page · raw message

drivers/crypto/ycc/ycc_ring.h +3 -0
index eb3e6f9..c3e7cbf 100644
@@ -20,6 +20,9 @@
 #define CMD_INVALID_CONTENT_U8		0x7f
 #define CMD_INVALID_CONTENT_U64		0x7f7f7f7f7f7f7f7fULL
 
+#define MAX_SLEEP_US_PER_CHECK		100   /* every 100us to check register */
+#define MAX_ERROR_RETRY			10000 /* 1s in total */
+
 enum ring_type {
 	FREE_RING,
 	USER_RING,
Signature · 1 line
1.8.3.1
author
#6 lore raw

PATCH v2 5/9 crypto/ycc: Add skcipher algorithm support

In reply to 'Guanjun'

From: Guanjun <[email protected]>

Support skcipher algorithm.

---
 drivers/crypto/ycc/Kconfig    |   9 +
 drivers/crypto/ycc/Makefile   |   2 +-
 drivers/crypto/ycc/ycc_algs.h | 114 ++++++
 drivers/crypto/ycc/ycc_dev.h  |   3 +
 drivers/crypto/ycc/ycc_drv.c  |  52 +++
 drivers/crypto/ycc/ycc_ring.h |  17 +-
 drivers/crypto/ycc/ycc_ske.c  | 925 ++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 1117 insertions(+), 5 deletions(-)
 create mode 100644 drivers/crypto/ycc/ycc_algs.h
 create mode 100644 drivers/crypto/ycc/ycc_ske.c
drivers/crypto/ycc/Kconfig +9 -0
index 6e88ecb..8dae75e 100644
@@ -2,6 +2,15 @@ config CRYPTO_DEV_YCC
 	tristate "Support for Alibaba YCC cryptographic accelerator"
 	depends on CRYPTO && CRYPTO_HW && PCI
 	default n
+	select CRYPTO_SKCIPHER
+	select CRYPTO_LIB_DES
+	select CRYPTO_SM3_GENERIC
+	select CRYPTO_AES
+	select CRYPTO_CBC
+	select CRYPTO_ECB
+	select CRYPTO_CTR
+	select CRYPTO_XTS
+	select CRYPTO_SM4
 	help
 	  Enables the driver for the on-chip cryptographic accelerator of
 	  Alibaba Yitian SoCs which is based on ARMv9 architecture.
drivers/crypto/ycc/Makefile +1 -1
index 61d17bd..8a23a72 100644
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
-ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o
+ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o
drivers/crypto/ycc/ycc_algs.h new file +114 -0

114 lines not on this page · raw message

drivers/crypto/ycc/ycc_dev.h +3 -0
index dda82b0..08f9a05 100644
@@ -151,4 +151,7 @@ static inline void ycc_g_err_unmask(void *vaddr)
 	YCC_CSR_WR(vaddr, REG_YCC_DEV_INT_MASK, 0);
 }
 
+int ycc_algorithm_register(void);
+void ycc_algorithm_unregister(void);
+
 #endif
drivers/crypto/ycc/ycc_drv.c +52 -0

90 lines not on this page · raw message

drivers/crypto/ycc/ycc_ring.h +13 -4
index c3e7cbf..78ba959 100644
@@ -75,11 +75,20 @@ struct ycc_resp_desc {
 	u8 reserved[6];
 };
 
+struct ycc_skcipher_cmd {
+	u8 cmd_id;
+	u8 mode;
+	u64 sptr:48;
+	u64 dptr:48;
+	u32 dlen;
+	u16 key_idx;	/* key used to decrypt kek */
+	u8 reserved[2];
+	u64 keyptr:48;
+	u8 padding;
+} __packed;
+
 union ycc_real_cmd {
-	/*
-	 * TODO: Real command will implement when
-	 * corresponding algorithm is ready
-	 */
+	struct ycc_skcipher_cmd ske_cmd;
 	u8 padding[32];
 };
 
drivers/crypto/ycc/ycc_ske.c new file +925 -0

925 lines not on this page · raw message

Signature · 1 line
1.8.3.1
author
#7 lore raw

PATCH v2 6/9 crypto/ycc: Add aead algorithm support

In reply to 'Guanjun'

From: Guanjun <[email protected]>

Support aead algorithm.

---
 drivers/crypto/ycc/Kconfig    |   1 +
 drivers/crypto/ycc/Makefile   |   2 +-
 drivers/crypto/ycc/ycc_aead.c | 646 ++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/ycc/ycc_algs.h |  20 +-
 drivers/crypto/ycc/ycc_drv.c  |   7 +
 drivers/crypto/ycc/ycc_ring.h |  14 +
 6 files changed, 687 insertions(+), 3 deletions(-)
 create mode 100644 drivers/crypto/ycc/ycc_aead.c
drivers/crypto/ycc/Kconfig +1 -0
index 8dae75e..d2808c3 100644
@@ -5,6 +5,7 @@ config CRYPTO_DEV_YCC
 	select CRYPTO_SKCIPHER
 	select CRYPTO_LIB_DES
 	select CRYPTO_SM3_GENERIC
+	select CRYPTO_AEAD
 	select CRYPTO_AES
 	select CRYPTO_CBC
 	select CRYPTO_ECB
drivers/crypto/ycc/Makefile +1 -1
index 8a23a72..279c8ca 100644
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
-ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o
+ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o
drivers/crypto/ycc/ycc_aead.c new file +646 -0

646 lines not on this page · raw message

drivers/crypto/ycc/ycc_algs.h +18 -2
index 6c7b0dc..e3be83ec 100644
@@ -3,6 +3,7 @@
 #define __YCC_ALG_H
 
 #include <crypto/skcipher.h>
+#include <crypto/aead.h>
 
 #include "ycc_ring.h"
 #include "ycc_dev.h"
@@ -70,6 +71,11 @@ enum ycc_ske_alg_mode {
 enum ycc_cmd_id {
 	YCC_CMD_SKE_ENC = 0x23,
 	YCC_CMD_SKE_DEC,
+
+	YCC_CMD_GCM_ENC = 0x25,
+	YCC_CMD_GCM_DEC,
+	YCC_CMD_CCM_ENC,
+	YCC_CMD_CCM_DEC, /* 0x28 */
 };
 
 struct ycc_crypto_ctx {
@@ -92,8 +98,10 @@ struct ycc_crypto_req {
 	dma_addr_t key_paddr;
 
 	struct ycc_cmd_desc desc;
-	struct skcipher_request *ske_req;
-	struct skcipher_request ske_subreq;
+	union {
+		struct skcipher_request *ske_req;
+		struct aead_request *aead_req;
+	};
 
 	void *src_vaddr;
 	dma_addr_t src_paddr;
@@ -105,10 +113,18 @@ struct ycc_crypto_req {
 	int aad_offset;
 	struct ycc_crypto_ctx *ctx;
 	u8 last_block[16]; /* used to store iv out when decrypt */
+
+	/* soft request for fallback, keep at the end */
+	union {
+		struct skcipher_request ske_subreq;
+		struct aead_request aead_subreq;
+	};
 };
 
 #define YCC_DEV(ctx)		(&(ctx)->ring->ydev->pdev->dev)
 
 int ycc_sym_register(void);
 void ycc_sym_unregister(void);
+int ycc_aead_register(void);
+void ycc_aead_unregister(void);
 #endif
drivers/crypto/ycc/ycc_drv.c +7 -0
index 79c1e18..cd583d7 100644
@@ -94,8 +94,14 @@ int ycc_algorithm_register(void)
 	if (ret)
 		goto err;
 
+	ret = ycc_aead_register();
+	if (ret)
+		goto unregister_sym;
+
 	return 0;
 
+unregister_sym:
+	ycc_sym_unregister();
 err:
 	atomic_dec(&ycc_algs_refcnt);
 	return ret;
@@ -109,6 +115,7 @@ void ycc_algorithm_unregister(void)
 	if (atomic_dec_return(&ycc_algs_refcnt))
 		return;
 
+	ycc_aead_unregister();
 	ycc_sym_unregister();
 }
 
drivers/crypto/ycc/ycc_ring.h +14 -0
index 78ba959..2caa9e0 100644
@@ -87,8 +87,22 @@ struct ycc_skcipher_cmd {
 	u8 padding;
 } __packed;
 
+struct ycc_aead_cmd {
+	u8 cmd_id;
+	u8 mode;
+	u64 sptr:48;	/* include aad + payload */
+	u64 dptr:48;	/* encrypted/decrypted + tag */
+	u32 dlen;	/* data size */
+	u16 key_idx;
+	u16 kek_idx;
+	u64 keyptr:48;
+	u16 aadlen;
+	u8 taglen;	/* authenc size */
+} __packed;
+
 union ycc_real_cmd {
 	struct ycc_skcipher_cmd ske_cmd;
+	struct ycc_aead_cmd aead_cmd;
 	u8 padding[32];
 };
 
Signature · 1 line
1.8.3.1
author
#8 lore raw

PATCH v2 7/9 crypto/ycc: Add rsa algorithm support

In reply to 'Guanjun'

From: Guanjun <[email protected]>

Support rsa algorithm for ycc. That includes encryption\decryption and verification\signature

---
 drivers/crypto/ycc/Makefile   |   2 +-
 drivers/crypto/ycc/ycc_algs.h |  44 +++
 drivers/crypto/ycc/ycc_drv.c  |   7 +
 drivers/crypto/ycc/ycc_pke.c  | 696 ++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/ycc/ycc_ring.h |  23 ++
 5 files changed, 771 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/ycc/ycc_pke.c
drivers/crypto/ycc/Makefile +1 -1
index 279c8ca..25f5930 100644
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
-ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o
+ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o ycc_pke.o
drivers/crypto/ycc/ycc_algs.h +44 -0

60 lines not on this page · raw message

drivers/crypto/ycc/ycc_drv.c +7 -0
index cd583d7..4a4d5cb 100644
@@ -98,8 +98,14 @@ int ycc_algorithm_register(void)
 	if (ret)
 		goto unregister_sym;
 
+	ret = ycc_pke_register();
+	if (ret)
+		goto unregister_aead;
+
 	return 0;
 
+unregister_aead:
+	ycc_aead_unregister();
 unregister_sym:
 	ycc_sym_unregister();
 err:
@@ -115,6 +121,7 @@ void ycc_algorithm_unregister(void)
 	if (atomic_dec_return(&ycc_algs_refcnt))
 		return;
 
+	ycc_pke_unregister();
 	ycc_aead_unregister();
 	ycc_sym_unregister();
 }
drivers/crypto/ycc/ycc_pke.c new file +696 -0

696 lines not on this page · raw message

drivers/crypto/ycc/ycc_ring.h +23 -0
index 2caa9e0..c47fc18 100644
@@ -100,9 +100,32 @@ struct ycc_aead_cmd {
 	u8 taglen;	/* authenc size */
 } __packed;
 
+struct ycc_rsa_enc_cmd {
+	u8 cmd_id;
+	u64 sptr:48;
+	u16 key_id;
+	u64 keyptr:48;	/* public key e+n Bytes */
+	u16 elen;	/* bits not byte */
+	u16 nlen;
+	u64 dptr:48;
+} __packed;
+
+struct ycc_rsa_dec_cmd {
+	u8 cmd_id;
+	u64 sptr:48;
+	u16 key_id;
+	u16 kek_id;
+	u64 keyptr:48;	/* private key e + pin + d + n */
+	u16 elen;	/* bits not byte */
+	u16 nlen;
+	u64 dptr:48;
+} __packed;
+
 union ycc_real_cmd {
 	struct ycc_skcipher_cmd ske_cmd;
 	struct ycc_aead_cmd aead_cmd;
+	struct ycc_rsa_enc_cmd rsa_enc_cmd;
+	struct ycc_rsa_dec_cmd rsa_dec_cmd;
 	u8 padding[32];
 };
 
Signature · 1 line
1.8.3.1
author
#9 lore raw

PATCH v2 8/9 crypto/ycc: Add sm2 algorithm support

In reply to 'Guanjun'

From: Xuchun Shang <[email protected]>

Only support verification through sm2 at present.

---
 drivers/crypto/ycc/Makefile            |   3 +-
 drivers/crypto/ycc/sm2signature_asn1.c |  38 +++++
 drivers/crypto/ycc/sm2signature_asn1.h |  13 ++
 drivers/crypto/ycc/ycc_algs.h          |   2 +
 drivers/crypto/ycc/ycc_pke.c           | 250 ++++++++++++++++++++++++++++++++-
 drivers/crypto/ycc/ycc_ring.h          |   8 ++
 6 files changed, 312 insertions(+), 2 deletions(-)
 create mode 100644 drivers/crypto/ycc/sm2signature_asn1.c
 create mode 100644 drivers/crypto/ycc/sm2signature_asn1.h
drivers/crypto/ycc/Makefile +2 -1
index 25f5930..3c86371 100644
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-(CONFIG_CRYPTO_DEV_YCC) += ycc.o
-ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o ycc_pke.o
+ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o ycc_pke.o \
+	sm2signature_asn1.o
drivers/crypto/ycc/sm2signature_asn1.c new file +38 -0
new file mode 100644
index 00000000..1fd15c1
@@ -0,0 +1,38 @@
+/*
+ * Automatically generated by asn1_compiler.  Do not edit
+ *
+ * ASN.1 parser for sm2signature
+ */
+#include <linux/asn1_ber_bytecode.h>
+#include "sm2signature_asn1.h"
+
+enum sm2signature_actions {
+	ACT_sm2_get_signature_r = 0,
+	ACT_sm2_get_signature_s = 1,
+	NR__sm2signature_actions = 2
+};
+
+static const asn1_action_t sm2signature_action_table[NR__sm2signature_actions] = {
+	[0] = sm2_get_signature_r,
+	[1] = sm2_get_signature_s,
+};
+
+static const unsigned char sm2signature_machine[] = {
+	// Sm2Signature
+	[0] = ASN1_OP_MATCH,
+	[1] = _tag(UNIV, CONS, SEQ),
+	[2] =  ASN1_OP_MATCH_ACT,		// sig_r
+	[3] =  _tag(UNIV, PRIM, INT),
+	[4] =  _action(ACT_sm2_get_signature_r),
+	[5] =  ASN1_OP_MATCH_ACT,		// sig_s
+	[6] =  _tag(UNIV, PRIM, INT),
+	[7] =  _action(ACT_sm2_get_signature_s),
+	[8] = ASN1_OP_END_SEQ,
+	[9] = ASN1_OP_COMPLETE,
+};
+
+const struct asn1_decoder sm2signature_decoder = {
+	.machine = sm2signature_machine,
+	.machlen = sizeof(sm2signature_machine),
+	.actions = sm2signature_action_table,
+};
drivers/crypto/ycc/sm2signature_asn1.h new file +13 -0
new file mode 100644
index 00000000..192c9e1
@@ -0,0 +1,13 @@
+/*
+ * Automatically generated by asn1_compiler.  Do not edit
+ *
+ * ASN.1 parser for sm2signature
+ */
+#include <linux/asn1_decoder.h>
+
+extern const struct asn1_decoder sm2signature_decoder;
+
+extern int sm2_get_signature_r(void *context, size_t hdrlen,
+		unsigned char tag, const void *value, size_t vlen);
+extern int sm2_get_signature_s(void *context, size_t hdrlen,
+		unsigned char tag, const void *value, size_t vlen);
drivers/crypto/ycc/ycc_algs.h +2 -0
index 6a13230a..26323a8 100644
@@ -77,6 +77,8 @@ enum ycc_cmd_id {
 	YCC_CMD_CCM_ENC,
 	YCC_CMD_CCM_DEC, /* 0x28 */
 
+	YCC_CMD_SM2_VERIFY = 0x47,
+
 	YCC_CMD_RSA_ENC = 0x83,
 	YCC_CMD_RSA_DEC,
 	YCC_CMD_RSA_CRT_DEC,
drivers/crypto/ycc/ycc_pke.c +249 -1

273 lines not on this page · raw message

drivers/crypto/ycc/ycc_ring.h +8 -0
index c47fc18..6dafdc7 100644
@@ -121,11 +121,19 @@ struct ycc_rsa_dec_cmd {
 	u64 dptr:48;
 } __packed;
 
+struct ycc_sm2_verify_cmd {
+	u8 cmd_id;
+	u64 sptr:48;
+	u16 key_id;
+	u64 keyptr:48;
+} __packed;
+
 union ycc_real_cmd {
 	struct ycc_skcipher_cmd ske_cmd;
 	struct ycc_aead_cmd aead_cmd;
 	struct ycc_rsa_enc_cmd rsa_enc_cmd;
 	struct ycc_rsa_dec_cmd rsa_dec_cmd;
+	struct ycc_sm2_verify_cmd sm2_verify_cmd;
 	u8 padding[32];
 };
 
Signature · 1 line
1.8.3.1
author
#10 lore raw

PATCH v2 9/9 MAINTAINERS: Add Yitian Cryptography Complex (YCC) driver maintainer entry

In reply to 'Guanjun'

From: Zelin Deng <[email protected]>

I will continue to add new feature, optimize the performance, and handle the issues of Yitian Cryptography Complex (YCC) driver.

Guanjun and Xuchun Shang focus on various algorithms support, add them as co-maintainers.

---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)
MAINTAINERS +8 -0
index 56ff555..ffededc 100644
@@ -943,6 +943,14 @@ S:	Supported
 F:	drivers/crypto/ccp/sev*
 F:	include/uapi/linux/psp-sev.h
 
+ALIBABA YITIAN CRYPTOGRAPHY COMPLEX (YCC) ACCELERATOR DRIVER
+M:	Zelin Deng <[email protected]>
+M:	Guanjun <[email protected]>
+M:	Xuchun Shang <[email protected]>
+L:	[email protected]
+S:	Supported
+F:	drivers/crypto/ycc/
+
 AMD DISPLAY CORE
 M:	Harry Wentland <[email protected]>
 M:	Leo Li <[email protected]>
Signature · 1 line
1.8.3.1
author
#11 lore raw
In reply to 'Guanjun'
Quoted 8 lines

2022年9月28日 下午3:37,Guanjun <[email protected]> 写道:

From: Guanjun <[email protected]>

Hi,

Hi Herbert, Elliott,

Quoted 6 lines

This patch series aims to add drivers for Alibaba YCC (Yitian Cryptography Complex) cryptographic accelerator. Enables the on-chip cryptographic accelerator of Alibaba Yitian SoCs which is based on ARMv9 architecture.

It includes PCIe enabling, skcipher, aead, rsa, sm2 support.

Quoted 8 lines

Please help to review.

Thanks,
Guanjun.

Change log:
v1 RESEND -> v2:
- [01/09] Remove char device that is not used now.

Do you have any comments about this v2 patchset?

Thank you very much for code review!

BR,
Guanjun

Quoted 59 lines

v1 -> v1 RESEND:
- [01/09] Adjust the Kconfig entry in alphabetical order
- [05/09][07/09][08/09] Adjust the format of algorithm names

v1: https://lore.kernel.org/all/[email protected]/
v1 RESEND: https://lore.kernel.org/all/[email protected]/

Guanjun (3):
crypto/ycc: Add skcipher algorithm support
crypto/ycc: Add aead algorithm support
crypto/ycc: Add rsa algorithm support

Xuchun Shang (1):
crypto/ycc: Add sm2 algorithm support

Zelin Deng (5):
crypto/ycc: Add YCC (Yitian Cryptography Complex) accelerator driver crypto/ycc: Add ycc ring configuration
crypto/ycc: Add irq support for ycc kernel rings crypto/ycc: Add device error handling support for ycc hw errors
MAINTAINERS: Add Yitian Cryptography Complex (YCC) driver maintainer
entry

MAINTAINERS                            |   8 +
drivers/crypto/Kconfig                 |   2 +
drivers/crypto/Makefile                |   1 +
drivers/crypto/ycc/Kconfig             |  18 +
drivers/crypto/ycc/Makefile            |   4 +
drivers/crypto/ycc/sm2signature_asn1.c |  38 ++
drivers/crypto/ycc/sm2signature_asn1.h |  13 +
drivers/crypto/ycc/ycc_aead.c          | 646 ++++++++++++++++++++++
drivers/crypto/ycc/ycc_algs.h          | 176 ++++++
drivers/crypto/ycc/ycc_dev.h           | 157 ++++++
drivers/crypto/ycc/ycc_drv.c           | 567 ++++++++++++++++++++
drivers/crypto/ycc/ycc_isr.c           | 279 ++++++++++
drivers/crypto/ycc/ycc_isr.h           |  12 +
drivers/crypto/ycc/ycc_pke.c           | 944 +++++++++++++++++++++++++++++++++
drivers/crypto/ycc/ycc_ring.c          | 652 +++++++++++++++++++++++
drivers/crypto/ycc/ycc_ring.h          | 168 ++++++
drivers/crypto/ycc/ycc_ske.c           | 925 ++++++++++++++++++++++++++++++++
17 files changed, 4610 insertions(+)

create mode 100644 drivers/crypto/ycc/Kconfig create mode 100644 drivers/crypto/ycc/Makefile create mode 100644 drivers/crypto/ycc/sm2signature_asn1.c create mode 100644 drivers/crypto/ycc/sm2signature_asn1.h create mode 100644 drivers/crypto/ycc/ycc_aead.c create mode 100644 drivers/crypto/ycc/ycc_algs.h create mode 100644 drivers/crypto/ycc/ycc_dev.h create mode 100644 drivers/crypto/ycc/ycc_drv.c create mode 100644 drivers/crypto/ycc/ycc_isr.c create mode 100644 drivers/crypto/ycc/ycc_isr.h create mode 100644 drivers/crypto/ycc/ycc_pke.c create mode 100644 drivers/crypto/ycc/ycc_ring.c create mode 100644 drivers/crypto/ycc/ycc_ring.h create mode 100644 drivers/crypto/ycc/ycc_ske.c

Signature · 1 line
1.8.3.1