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FAILED: patch "[PATCH] drm/i915/tgl+: Add locking around DKL PHY register accesses" failed to apply to 5.15-stable tree

PATCH [email protected] 1 participant 1 message Jan 4, 2023

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Stable branch DRM drivers Intel i915 Intel DRM display for xe and i915 drivers
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The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

Possible dependencies:

89cb0ba4ceee ("drm/i915/tgl+: Add locking around DKL PHY register accesses") b7d1559038b6 ("drm/i915: move dbuf under display sub-struct") 90b87cf24304 ("drm/i915: move mipi_mmio_base to display.dsi") d51309b4e9aa ("drm/i915: move and group cdclk under display.cdclk") f0acaf9d6912 ("drm/i915: move and group max_bw and bw_obj under display.bw") eb11eabc5f26 ("drm/i915: move and group hdcp under display.hdcp") b3d81dafdc48 ("drm/i915: move and group fbdev under display.fbdev") 36d225f365e7 ("drm/i915: move dpll under display.dpll")
4be1c12c880e ("drm/i915: move and split audio under display.audio and display.funcs") 6c77055aa674 ("drm/i915: move dmc to display.dmc")
12dc50823845 ("drm/i915: move and group pps members under display.pps") 203eb5a98edb ("drm/i915: move and group gmbus members under display.gmbus") 34dc3cc5017f ("drm/i915: move color_funcs to display.funcs") 06a50913d96e ("drm/i915: move fdi_funcs to display.funcs")
103472c13f0a ("drm/i915: move wm_disp funcs to display.funcs") 5a04eb5be8e4 ("drm/i915: move hotplug_funcs to display.funcs") ae611d171ec0 ("drm/i915: move dpll_funcs to display.funcs") 986531bd0e72 ("drm/i915: move cdclk_funcs to display.funcs") 3b10f8517648 ("drm/i915: add display sub-struct to drm_i915_private") c247cd03898c ("drm/i915: fix null pointer dereference")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 89cb0ba4ceee6bed1059904859c5723b3f39da68 Mon Sep 17 00:00:00 2001
From: Imre Deak <[email protected]>
Date: Tue, 25 Oct 2022 14:44:55 +0300
Subject: [PATCH] drm/i915/tgl+: Add locking around DKL PHY register accesses
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Accessing the TypeC DKL PHY registers during modeset-commit, -verification, DP link-retraining and AUX power well toggling is racy due to these code paths being concurrent and the PHY register bank selection register (HIP_INDEX_REG) being shared between PHY instances (aka TC ports) and the bank selection being not atomic wrt. the actual PHY register access.

Add the required locking around each PHY register bank selection-> register access sequence.

Kudos to Ville for noticing the race conditions.

v2:
- Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani)
- Make the DKL_REG_TC_PORT macro independent of PHY internals.
- Move initing the DKL PHY lock to a more logical place.

v3:
- Fix parameter reuse in the DKL_REG_TC_PORT definition.
- Document the usage of phy_lock.

v4:
- Fix adding TC_PORT_1 offset in the DKL_REG_TC_PORT definition.

Cc Ville Syrjälä <[email protected]>
Cc Jani Nikula <[email protected]>
Cc <[email protected]> # v5.5+
Acked-by Jani Nikula <[email protected]>
Signed-off-by Imre Deak <[email protected]>
Link https://patchwork.freedesktop.org/patch/msgid/[email protected]
drivers/gpu/drm/i915/Makefile +1 -0
index 8f35be02b80e..b9da872ba8c0 100644
@@ -281,6 +281,7 @@ i915-y += \
 	display/intel_ddi.o \
 	display/intel_ddi_buf_trans.o \
 	display/intel_display_trace.o \
+	display/intel_dkl_phy.o \
 	display/intel_dp.o \
 	display/intel_dp_aux.o \
 	display/intel_dp_aux_backlight.o \
drivers/gpu/drm/i915/display/intel_ddi.c +28 -40

111 lines not on this page · raw message

drivers/gpu/drm/i915/display/intel_display_core.h +8 -0
index b4b9c4cef78e..337d8e08ba43 100644
@@ -320,6 +320,14 @@ struct intel_display {
 		struct intel_global_obj obj;
 	} dbuf;
 
+	struct {
+		/*
+		 * dkl.phy_lock protects against concurrent access of the
+		 * Dekel TypeC PHYs.
+		 */
+		spinlock_t phy_lock;
+	} dkl;
+
 	struct {
 		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
 		u32 mmio_base;
drivers/gpu/drm/i915/display/intel_display_power_well.c +3 -4
index df7ee4969ef1..1d18eee56253 100644
@@ -12,6 +12,7 @@
 #include "intel_de.h"
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
+#include "intel_dkl_phy.h"
 #include "intel_dmc.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"

@@ -529,11 +530,9 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 		enum tc_port tc_port;
 
 		tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
-		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
-			       HIP_INDEX_VAL(tc_port, 0x2));
 
-		if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
-					  DKL_CMN_UC_DW27_UC_HEALTH, 1))
+		if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) &
+			     DKL_CMN_UC_DW27_UC_HEALTH, 1))
 			drm_warn(&dev_priv->drm,
 				 "Timeout waiting TC uC health\n");
 	}
drivers/gpu/drm/i915/display/intel_dkl_phy.c new file +109 -0

109 lines not on this page · raw message

drivers/gpu/drm/i915/display/intel_dkl_phy.h new file +24 -0
new file mode 100644
index 000000000000..260ad121a0b1
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DKL_PHY_H__
+#define __INTEL_DKL_PHY_H__
+
+#include <linux/types.h>
+
+#include "i915_reg_defs.h"
+
+struct drm_i915_private;
+
+u32
+intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln);
+void
+intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val);
+void
+intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set);
+void
+intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln);
+
+#endif /* __INTEL_DKL_PHY_H__ */
drivers/gpu/drm/i915/display/intel_dpll_mgr.c +27 -32

141 lines not on this page · raw message

drivers/gpu/drm/i915/i915_driver.c +1 -0
index e7b2ebc6b88d..5802be24a22f 100644
@@ -341,6 +341,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 	mutex_init(&dev_priv->display.wm.wm_mutex);
 	mutex_init(&dev_priv->display.pps.mutex);
 	mutex_init(&dev_priv->display.hdcp.comp_mutex);
+	spin_lock_init(&dev_priv->display.dkl.phy_lock);
 
 	i915_memcpy_init_early(dev_priv);
 	intel_runtime_pm_init_early(&dev_priv->runtime_pm);
drivers/gpu/drm/i915/i915_reg.h +3 -0
index 975ce5e0a890..959c2bd6707c 100644
@@ -7425,6 +7425,9 @@ enum skl_power_gate {
 #define _DKL_PHY5_BASE			0x16C000
 #define _DKL_PHY6_BASE			0x16D000
 
+#define DKL_REG_TC_PORT(__reg) \
+	(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
+
 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
 #define _DKL_PCS_DW5			0x14
 #define DKL_PCS_DW5(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \