PolarFire SoC Auto Update Support

From: Conor Dooley <[email protected]>

Hey all,

This patchset adds support for the "Auto Update" feature on PolarFire SoC that allows for writing an FPGA bistream to the SPI flash connected to the system controller.
On powercycle (or reboot depending on how the firmware implements the openSBI SRST extension) "Auto Update" will take place, and program the FPGA with the contents of the SPI flash - provided that that image is valid and an actual upgrade from that already programmed.

Previously this driver was added to the FPGA subsystem, but as there is no capability for dynamic reconfiguration due to the device reset requirement, the FPGA manager framework is not actually used by the driver. As a result, the FPGA maintainers did not think it belonged in that directory, and after speaking to Arnd, I have put it in drivers/firmware/microchip instead. Otherwise, very little has changed here, compared to the previous submission.

If this is acceptable, I can add this to my eventual SoC drivers pull request for v6.8.

Cheers,
Conor.

Changes in v3:
- Move the driver to drivers/firmware
- Rename the firmware upload device: s/mpfs_bitstream/mpfs-auto-update/
- Fix the clock parentage for the qspi node added in this series
- https://lore.kernel.org/linux-fpga/ZDlJxrybiWy3Mk4Y@yilunxu-OptiPlex-7050/

Changes in v2:
- per Russ' suggestion, the driver has been switched to using the firmware-upload API rather than the fpga one
- as a result of that change, the structure of the driver has changed significantly, although most of that is reshuffling existing code around
- check if the upgrade is possible in probe and fail if it isn't
- only write the image index if it is not already set
- delete the now unneeded debugfs bits

Conor Dooley (6):
dt-bindings: soc: microchip: add a property for system controller
flash
soc: microchip: mpfs: enable access to the system controller's flash
soc: microchip: mpfs: print service status in warning message
soc: microchip: mpfs: add auto-update subdev to system controller
firmware: microchip: add PolarFire SoC Auto Update support
riscv: dts: microchip: add the mpfs' system controller qspi &
associated flash

 .../microchip,mpfs-sys-controller.yaml        |  10 +
 .../boot/dts/microchip/mpfs-icicle-kit.dts    |  21 +
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  17 +
 drivers/firmware/Kconfig                      |   1 +
 drivers/firmware/Makefile                     |   1 +
 drivers/firmware/microchip/Kconfig            |  12 +
 drivers/firmware/microchip/Makefile           |   3 +
 drivers/firmware/microchip/mpfs-auto-update.c | 494 ++++++++++++++++++
 drivers/soc/microchip/Kconfig                 |   1 +
 drivers/soc/microchip/mpfs-sys-controller.c   |  33 +-
 include/soc/microchip/mpfs.h                  |   2 +
 11 files changed, 592 insertions(+), 3 deletions(-)
 create mode 100644 drivers/firmware/microchip/Kconfig
 create mode 100644 drivers/firmware/microchip/Makefile
 create mode 100644 drivers/firmware/microchip/mpfs-auto-update.c

2.39.2

From: Conor Dooley <[email protected]>

The system controller "shares" a SPI flash device with a QSPI controller in the MSS. This flash is used to store FPGA bitstreams & other metadata. IAP and Auto Upgrade both write images to this flash that the System Controller will use to re-program the FPGA.

Add a phandle property signifying which flash device is connected to the system controller.

---
 .../soc/microchip/microchip,mpfs-sys-controller.yaml   | 10 ++++++++++
 1 file changed, 10 insertions(+)

index 365a9fed5914..a3fa04f3a1bd 100644
@@ -26,6 +26,16 @@ properties:
   compatible:
     const: microchip,mpfs-sys-controller
 
+  microchip,bitstream-flash:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      The SPI flash connected to the system controller's QSPI controller.
+      The system controller may retrieve FPGA bitstreams from this flash to
+      perform In-Application Programming (IAP) or during device initialisation
+      for Auto Update. The MSS and system controller have separate QSPI
+      controllers and this flash is connected to both. Software running in the
+      MSS can write bitstreams to the flash.
+
 required:
   - compatible
   - mboxes

2.39.2

From: Conor Dooley <[email protected]>

The system controller has a flash that contains images used to reprogram the FPGA using IAP (In-Application Programming).
Introduce a function that allows a driver with a reference to the system controller to get one to a flash device attached to it.

---
 drivers/soc/microchip/Kconfig               |  1 +
 drivers/soc/microchip/mpfs-sys-controller.c | 20 ++++++++++++++++++++
 include/soc/microchip/mpfs.h                |  2 ++
 3 files changed, 23 insertions(+)

index eb656b33156b..9b0fdd95276e 100644
@@ -1,6 +1,7 @@
 config POLARFIRE_SOC_SYS_CTRL
 	tristate "POLARFIRE_SOC_SYS_CTRL"
 	depends on POLARFIRE_SOC_MAILBOX
+	depends on MTD
 	help
 	  This driver adds support for the PolarFire SoC (MPFS) system controller.
 

index fbcd5fd24d7c..829d6c511efc 100644
@@ -12,6 +12,8 @@
 #include <linux/kref.h>
 #include <linux/module.h>
 #include <linux/jiffies.h>
+#include <linux/mtd/mtd.h>
+#include <linux/spi/spi.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/mailbox_client.h>

@@ -30,6 +32,7 @@ struct mpfs_sys_controller {
 	struct mbox_client client;
 	struct mbox_chan *chan;
 	struct completion c;
+	struct mtd_info *flash;
 	struct kref consumers;
 };
 

@@ -99,6 +102,12 @@ static void mpfs_sys_controller_put(void *data)
 	kref_put(&sys_controller->consumers, mpfs_sys_controller_delete);
 }
 
+struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client)
+{
+	return mpfs_client->flash;
+}
+EXPORT_SYMBOL(mpfs_sys_controller_get_flash);
+
 static struct platform_device subdevs[] = {
 	{
 		.name		= "mpfs-rng",

@@ -114,12 +123,23 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct mpfs_sys_controller *sys_controller;
+	struct device_node *np;
 	int i, ret;
 
 	sys_controller = kzalloc(sizeof(*sys_controller), GFP_KERNEL);
 	if (!sys_controller)
 		return -ENOMEM;
 
+	np = of_parse_phandle(dev->of_node, "microchip,bitstream-flash", 0);
+	if (!np)
+		goto no_flash;
+
+	sys_controller->flash = of_get_mtd_device_by_node(np);
+	of_node_put(np);
+	if (IS_ERR(sys_controller->flash))
+		return dev_err_probe(dev, PTR_ERR(sys_controller->flash), "Failed to get flash\n");
+
+no_flash:
 	sys_controller->client.dev = dev;
 	sys_controller->client.rx_callback = mpfs_sys_controller_rx_callback;
 	sys_controller->client.tx_block = 1U;

index f916dcde457f..09722f83b0ca 100644
@@ -38,6 +38,8 @@ int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mp
 
 struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
 
+struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client);
+
 #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
 
 #if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)

2.39.2

From: Conor Dooley <[email protected]>

Now that resp_status is set for failed services, print the status in the error path's warning.

---
 drivers/soc/microchip/mpfs-sys-controller.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

index 829d6c511efc..f363f13567f0 100644
@@ -66,7 +66,9 @@ int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct
 	 */
 	if (!wait_for_completion_timeout(&sys_controller->c, timeout)) {
 		ret = -EBADMSG;
-		dev_warn(sys_controller->client.dev, "MPFS sys controller service failed\n");
+		dev_warn(sys_controller->client.dev,
+			 "MPFS sys controller service failed with status: %d\n",
+			 msg->response->resp_status);
 	} else {
 		ret = 0;
 	}

2.39.2

From: Conor Dooley <[email protected]>

The PolarFire SoC's system controller offers the ability to re-program the FPGA from a user application via two, related, mechanisms. In-Application Programming (IAP) is not ideal for use in Linux, as it will immediately take down the system when requested. Auto Update is preferred, as it will only take affect at device power up*, allowing the OS (and potential applications in AMP) to be shut down gracefully.

* Auto Update occurs at device initialisation, which can also be triggered by device reset - possible with the v2023.02 version of the Hart Software Services (HSS) and reference design.

---
 drivers/soc/microchip/mpfs-sys-controller.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

index f363f13567f0..35c03ded8501 100644
@@ -118,7 +118,11 @@ static struct platform_device subdevs[] = {
 	{
 		.name		= "mpfs-generic-service",
 		.id		= -1,
-	}
+	},
+	{
+		.name		= "mpfs-auto-update",
+		.id		= -1,
+	},
 };
 
 static int mpfs_sys_controller_probe(struct platform_device *pdev)

@@ -160,7 +164,6 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, sys_controller);
 
-	dev_info(&pdev->dev, "Registered MPFS system controller\n");
 
 	for (i = 0; i < ARRAY_SIZE(subdevs); i++) {
 		subdevs[i].dev.parent = dev;

@@ -168,6 +171,8 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev)
 			dev_warn(dev, "Error registering sub device %s\n", subdevs[i].name);
 	}
 
+	dev_info(&pdev->dev, "Registered MPFS system controller\n");
+
 	return 0;
 }
 

2.39.2

From: Conor Dooley <[email protected]>

Add support for Auto Update reprogramming of the FPGA fabric on PolarFire SoC, using the fw_upload mechanism a la the intel-m10-bmc-sec-update driver.

This driver only writes the image to the spi flash & performs validation on it, as the entire FPGA becomes unusable during the actual reprogramming of a bitstream. To initiate the reprogramming itself, a device reset is required. The SBI SRST extension's "cold reboot" can trigger such a device reset, provided corresponding support has been enabled in the HSS (Hart Software Services), the provider of SBI runtime services on PolarFire SoC.

While this is a driver responsible for the reprogramming of an FPGA, there is no dynamic discovery of devices involved, as runtime reconfiguration is not possible due to the device reset requirements. Therefore FPGA manager subsystem is not used by this driver and the FPGA subsystem maintainers were unwilling to accept it there.

---
 drivers/firmware/Kconfig                      |   1 +
 drivers/firmware/Makefile                     |   1 +
 drivers/firmware/microchip/Kconfig            |  12 +
 drivers/firmware/microchip/Makefile           |   3 +
 drivers/firmware/microchip/mpfs-auto-update.c | 494 ++++++++++++++++++
 5 files changed, 511 insertions(+)
 create mode 100644 drivers/firmware/microchip/Kconfig
 create mode 100644 drivers/firmware/microchip/Makefile
 create mode 100644 drivers/firmware/microchip/mpfs-auto-update.c

index b59e3041fd62..f247ac33c75b 100644
@@ -310,6 +310,7 @@ source "drivers/firmware/google/Kconfig"
 source "drivers/firmware/efi/Kconfig"
 source "drivers/firmware/imx/Kconfig"
 source "drivers/firmware/meson/Kconfig"
+source "drivers/firmware/microchip/Kconfig"
 source "drivers/firmware/psci/Kconfig"
 source "drivers/firmware/smccc/Kconfig"
 source "drivers/firmware/tegra/Kconfig"

index 28fcddcd688f..901771d2bd47 100644
@@ -31,6 +31,7 @@ obj-y				+= arm_scmi/
 obj-y				+= broadcom/
 obj-y				+= cirrus/
 obj-y				+= meson/
+obj-y				+= microchip/
 obj-$(CONFIG_GOOGLE_FIRMWARE)	+= google/
 obj-y				+= efi/
 obj-y				+= imx/

new file mode 100644
index 000000000000..434b923e08c2
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config POLARFIRE_SOC_AUTO_UPDATE
+	tristate "Microchip PolarFire SoC AUTO UPDATE"
+	depends on POLARFIRE_SOC_SYS_CTRL
+	select FW_LOADER
+	select FW_UPLOAD
+	help
+	  Support for reprogramming PolarFire SoC from within Linux, using the
+	  Auto Upgrade feature of the system controller.
+
+	  If built as a module, it will be called mpfs-auto-update.

new file mode 100644
index 000000000000..38796fd82893
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_POLARFIRE_SOC_AUTO_UPDATE) += mpfs-auto-update.o

2.39.2

From: Conor Dooley <[email protected]>

The system controller's flash can be accessed via an MSS-exposed QSPI controller sitting, which sits between the mailbox's control & data registers. On Icicle, it has an MT25QL01GBBB8ESF connected to it.

The system controller and MSS both have separate QSPI controllers, both of which can access the flash, although the system controller takes priority.
Unfortunately, on engineering sample silicon, such as that on Icicle kits, the MSS' QSPI controller cannot write to the flash due to a bug. As a workaround, a QSPI controller can be implemented in the FPGA fabric and the IO routing modified to connect it to the flash in place of the "hard" controller in the MSS.

---
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 21 +++++++++++++++++++
 arch/riscv/boot/dts/microchip/mpfs.dtsi       | 17 +++++++++++++++
 2 files changed, 38 insertions(+)

index 90b261114763..2dae3f8f33f6 100644
@@ -199,6 +199,27 @@ &syscontroller {
 	status = "okay";
 };
 
+&syscontroller_qspi {
+	/*
+	 * The flash *is* there, but Icicle kits that have engineering sample
+	 * silicon (write?) access to this flash to non-functional. The system
+	 * controller itself can actually access it, but the MSS cannot write
+	 * an image there. Instantiating a coreQSPI in the fabric & connecting
+	 * it to the flash instead should work though. Pre-production or later
+	 * silicon does not have this issue.
+	 */
+	status = "disabled";
+
+	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+	};
+};
+
 &usb {
 	status = "okay";
 	dr_mode = "host";

index 104504352e99..8f66e2c839ef 100644
@@ -178,6 +178,12 @@ syscontroller: syscontroller {
 		mboxes = <&mbox 0>;
 	};
 
+	scbclk: mssclkclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <80000000>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -508,5 +514,16 @@ mbox: mailbox@37020000 {
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
+
+		syscontroller_qspi: spi@37020100 {
+			compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x37020100 0x0 0x100>;
+			interrupt-parent = <&plic>;
+			interrupts = <110>;
+			clocks = <&scbclk>;
+			status = "disabled";
+		};
 	};
 };

2.39.2

From: Conor Dooley <[email protected]>

Arnd, I've gone and applied this stuff since things have been dead since I sent it & will send it to you for the upcoming mw in a few weeks.

[1/6] dt-bindings: soc: microchip: add a property for system controller flash

      https://git.kernel.org/conor/c/98d62e97c39f
[2/6] soc: microchip: mpfs: enable access to the system controller's flash
      https://git.kernel.org/conor/c/742aa6c563d2
[3/6] soc: microchip: mpfs: print service status in warning message
      https://git.kernel.org/conor/c/a8f00589be7b
[4/6] soc: microchip: mpfs: add auto-update subdev to system controller
      https://git.kernel.org/conor/c/fad13b5b73e0
[5/6] firmware: microchip: add PolarFire SoC Auto Update support
      https://git.kernel.org/conor/c/ec5b0f1193ad

Thanks,
Conor.