ARM: rockchip: provide the watchdog with a clock

The snps,dw-wdt needs to read the clock-rate of its supplying clock for some operations. The clock itself is based on pclk_pd_alive and is indeed gateable. The caveat is that the gate is living in the so-called secure-GRF, which isn't even writeable in some boot-modes.

But to have an actual clock reference to the correct clock, implement a fixed-factor clock, to be substituted when we can control the actual gate safely.

Heiko Stuebner (3):
clk: rockchip: add id for watchdog pclk on rk3288
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
ARM: dts: rockchip: add rk3288 watchdog clock

 arch/arm/boot/dts/rk3288.dtsi          | 1 +
 drivers/clk/rockchip/clk-rk3288.c      | 8 ++++++++
 include/dt-bindings/clock/rk3288-cru.h | 1 +
 3 files changed, 10 insertions(+)

2.1.1

Adds a new id for the pclk supplying the watchdog on rk3288 socs.

---
 include/dt-bindings/clock/rk3288-cru.h | 1 +
 1 file changed, 1 insertion(+)

index 1c34c24..ba0d724 100644
@@ -157,6 +157,7 @@
 #define PCLK_PUBL0		365
 #define PCLK_DDRUPCTL1		366
 #define PCLK_PUBL1		367
+#define PCLK_WDT		368
 
 /* hclk gates */
 #define HCLK_GPS		448

2.1.1

Heiko,

The pclk supplying the watchdog is controlled via the SGRF register area. Currently we don't have any clock-type handling external clock bits like this one. Additionally the SGRF isn't even writable in every boot mode.

But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate.

---
 drivers/clk/rockchip/clk-rk3288.c | 8 ++++++++
 1 file changed, 8 insertions(+)

index cbcddcc..6cc3e0d 100644
@@ -866,6 +866,14 @@ static void __init rk3288_clk_init(struct device_node *np)
 		pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 			__func__, PTR_ERR(clk));
 
+	/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
+	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
+	if (IS_ERR(clk))
+		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
+			__func__, PTR_ERR(clk));
+	else
+		rockchip_clk_add_lookup(clk, PCLK_WDT);
+
 	rockchip_clk_register_plls(rk3288_pll_clks,
 				   ARRAY_SIZE(rk3288_pll_clks),
 				   RK3288_GRF_SOC_STATUS1);

2.1.1

Heiko,

On rk3288 on a 3.14 kernel with backports, I tested this and confirmed that the clock rate was right (when programmed to ~43 seconds, the watchdog caused a reboot when not patted for ~43 seconds).

Add the clock property for the watchdog on rk3288 socs.

---
 arch/arm/boot/dts/rk3288.dtsi | 1 +
 1 file changed, 1 insertion(+)

index 910dcad..6fcf74b9 100644
@@ -554,6 +554,7 @@
 	wdt: watchdog at ff800000 {
 		compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 		reg = <0xff800000 0x100>;
+		clocks = <&cru PCLK_WDT>;
 		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};

2.1.1

Heiko,

On rk3288 on a 3.14 kernel with backports:

Am Mittwoch, 21. Januar 2015, 20:54:50 schrieb Heiko St?bner:

with the clock changes (patches 1+2) being accepted into the clock tree, I've now also added the third patch to my dts branch.

Heiko