Add Renesas R8A7794 audio PFC support
Subsystems (4)
cover Add Renesas R8A7794 audio PFC support
Hello.
Here's the set of 2 patches against the 'devel' branch of Linus Walleij's
'linux-pinctrl.git' repo. Here we add the PFC support for the Renesas R8A7794 SSI devices and audio clocks.
[1/2] pinctrl: sh-pfc: r8a7794: add SSI pin groups [2/2] pinctrl: sh-pfc: r8a7794: add audio clock pin groups
WBR, Sergei
PATCH 1/2 pinctrl: sh-pfc: r8a7794: add SSI pin groups
From: Ryo Kataoka <[email protected]>
Add the SSI pin groups to the R8A7794 PFC driver.
[Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control ones, moved SSI7 data B group to its proper place, fixed pin names in the comments to *_pins[], extended Cogent Embedded's copyright, added the changelog, renamed the patch.]
--- drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 315 ++++++++++++++++++++++++++++++++++- 1 file changed, 313 insertions(+), 2 deletions(-)
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +313 -2
@@ -1,9 +1,9 @@/* * r8a7794 processor support - PFC hardware block. * -* Copyright (C) 2014 Renesas Electronics Corporation +* Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Solutions Corp. -* Copyright (C) 2015 Cogent Embedded, Inc., <[email protected]> +* Copyright (C) 2015-2016 Cogent Embedded, Inc., <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2
@@ -2751,6 +2751,245 @@ static const unsigned int sdhi2_wp_pins[static const unsigned int sdhi2_wp_mux[] = {SD2_WP_MARK , }; +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { +/* SDATA0 */ +RCAR_GP_PIN (5 ,3 ), +}; +static const unsigned int ssi0_data_mux[] = { +SSI_SDATA0_MARK , +}; +static const unsigned int ssi0129_ctrl_pins[] = { +/* SCK0129, WS0129 */ +RCAR_GP_PIN (5 ,1 ),RCAR_GP_PIN (5 ,2 ), +}; +static const unsigned int ssi0129_ctrl_mux[] = { +SSI_SCK0129_MARK ,SSI_WS0129_MARK , +}; +static const unsigned int ssi1_data_pins[] = { +/* SDATA1 */ +RCAR_GP_PIN (5 ,13 ), +}; +static const unsigned int ssi1_data_mux[] = { +SSI_SDATA1_MARK , +}; +static const unsigned int ssi1_ctrl_pins[] = { +/* SCK1, WS1 */ +RCAR_GP_PIN (5 ,11 ),RCAR_GP_PIN (5 ,12 ), +}; +static const unsigned int ssi1_ctrl_mux[] = { +SSI_SCK1_MARK ,SSI_WS1_MARK , +}; +static const unsigned int ssi1_data_b_pins[] = { +/* SDATA1 */ +RCAR_GP_PIN (4 ,13 ), +}; +static const unsigned int ssi1_data_b_mux[] = { +SSI_SDATA1_B_MARK , +}; +static const unsigned int ssi1_ctrl_b_pins[] = { +/* SCK1, WS1 */ +RCAR_GP_PIN (4 ,11 ),RCAR_GP_PIN (4 ,12 ), +}; +static const unsigned int ssi1_ctrl_b_mux[] = { +SSI_SCK1_B_MARK ,SSI_WS1_B_MARK , +}; +static const unsigned int ssi2_data_pins[] = { +/* SDATA2 */ +RCAR_GP_PIN (5 ,16 ), +}; +static const unsigned int ssi2_data_mux[] = { +SSI_SDATA2_MARK , +}; +static const unsigned int ssi2_ctrl_pins[] = { +/* SCK2, WS2 */ +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +}; +static const unsigned int ssi2_ctrl_mux[] = { +SSI_SCK2_MARK ,SSI_WS2_MARK , +}; +static const unsigned int ssi2_data_b_pins[] = { +/* SDATA2 */ +RCAR_GP_PIN (4 ,16 ), +}; +static const unsigned int ssi2_data_b_mux[] = { +SSI_SDATA2_B_MARK , +}; +static const unsigned int ssi2_ctrl_b_pins[] = { +/* SCK2, WS2 */ +RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,15 ), +}; +static const unsigned int ssi2_ctrl_b_mux[] = { +SSI_SCK2_B_MARK ,SSI_WS2_B_MARK , +}; +static const unsigned int ssi3_data_pins[] = { +/* SDATA3 */ +RCAR_GP_PIN (5 ,6 ), +}; +static const unsigned int ssi3_data_mux[] = { +SSI_SDATA3_MARK +}; +static const unsigned int ssi34_ctrl_pins[] = { +/* SCK34, WS34 */ +RCAR_GP_PIN (5 ,4 ),RCAR_GP_PIN (5 ,5 ), +}; +static const unsigned int ssi34_ctrl_mux[] = { +SSI_SCK34_MARK ,SSI_WS34_MARK , +}; +static const unsigned int ssi4_data_pins[] = { +/* SDATA4 */ +RCAR_GP_PIN (5 ,9 ), +}; +static const unsigned int ssi4_data_mux[] = { +SSI_SDATA4_MARK , +}; +static const unsigned int ssi4_ctrl_pins[] = { +/* SCK4, WS4 */ +RCAR_GP_PIN (5 ,7 ),RCAR_GP_PIN (5 ,8 ), +}; +static const unsigned int ssi4_ctrl_mux[] = { +SSI_SCK4_MARK ,SSI_WS4_MARK , +}; +static const unsigned int ssi4_data_b_pins[] = { +/* SDATA4 */ +RCAR_GP_PIN (4 ,22 ), +}; +static const unsigned int ssi4_data_b_mux[] = { +SSI_SDATA4_B_MARK , +}; +static const unsigned int ssi4_ctrl_b_pins[] = { +/* SCK4, WS4 */ +RCAR_GP_PIN (4 ,20 ),RCAR_GP_PIN (4 ,21 ), +}; +static const unsigned int ssi4_ctrl_b_mux[] = { +SSI_SCK4_B_MARK ,SSI_WS4_B_MARK , +}; +static const unsigned int ssi5_data_pins[] = { +/* SDATA5 */ +RCAR_GP_PIN (4 ,26 ), +}; +static const unsigned int ssi5_data_mux[] = { +SSI_SDATA5_MARK , +}; +static const unsigned int ssi5_ctrl_pins[] = { +/* SCK5, WS5 */ +RCAR_GP_PIN (4 ,24 ),RCAR_GP_PIN (4 ,25 ), +}; +static const unsigned int ssi5_ctrl_mux[] = { +SSI_SCK5_MARK ,SSI_WS5_MARK , +}; +static const unsigned int ssi5_data_b_pins[] = { +/* SDATA5 */ +RCAR_GP_PIN (3 ,21 ), +}; +static const unsigned int ssi5_data_b_mux[] = { +SSI_SDATA5_B_MARK , +}; +static const unsigned int ssi5_ctrl_b_pins[] = { +/* SCK5, WS5 */ +RCAR_GP_PIN (3 ,19 ),RCAR_GP_PIN (3 ,20 ), +}; +static const unsigned int ssi5_ctrl_b_mux[] = { +SSI_SCK5_B_MARK ,SSI_WS5_B_MARK , +}; +static const unsigned int ssi6_data_pins[] = { +/* SDATA6 */ +RCAR_GP_PIN (4 ,29 ), +}; +static const unsigned int ssi6_data_mux[] = { +SSI_SDATA6_MARK , +}; +static const unsigned int ssi6_ctrl_pins[] = { +/* SCK6, WS6 */ +RCAR_GP_PIN (4 ,27 ),RCAR_GP_PIN (4 ,28 ), +}; +static const unsigned int ssi6_ctrl_mux[] = { +SSI_SCK6_MARK ,SSI_WS6_MARK , +}; +static const unsigned int ssi6_data_b_pins[] = { +/* SDATA6 */ +RCAR_GP_PIN (3 ,24 ), +}; +static const unsigned int ssi6_data_b_mux[] = { +SSI_SDATA6_B_MARK , +}; +static const unsigned int ssi6_ctrl_b_pins[] = { +/* SCK6, WS6 */ +RCAR_GP_PIN (3 ,22 ),RCAR_GP_PIN (3 ,23 ), +}; +static const unsigned int ssi6_ctrl_b_mux[] = { +SSI_SCK6_B_MARK ,SSI_WS6_B_MARK , +}; +static const unsigned int ssi7_data_pins[] = { +/* SDATA7 */ +RCAR_GP_PIN (5 ,0 ), +}; +static const unsigned int ssi7_data_mux[] = { +SSI_SDATA7_MARK , +}; +static const unsigned int ssi78_ctrl_pins[] = { +/* SCK78, WS78 */ +RCAR_GP_PIN (4 ,30 ),RCAR_GP_PIN (4 ,31 ), +}; +static const unsigned int ssi78_ctrl_mux[] = { +SSI_SCK78_MARK ,SSI_WS78_MARK , +}; +static const unsigned int ssi7_data_b_pins[] = { +/* SDATA7 */ +RCAR_GP_PIN (3 ,27 ), +}; +static const unsigned int ssi7_data_b_mux[] = { +SSI_SDATA7_B_MARK , +}; +static const unsigned int ssi78_ctrl_b_pins[] = { +/* SCK78, WS78 */ +RCAR_GP_PIN (3 ,25 ),RCAR_GP_PIN (3 ,26 ), +}; +static const unsigned int ssi78_ctrl_b_mux[] = { +SSI_SCK78_B_MARK ,SSI_WS78_B_MARK , +}; +static const unsigned int ssi8_data_pins[] = { +/* SDATA8 */ +RCAR_GP_PIN (5 ,10 ), +}; +static const unsigned int ssi8_data_mux[] = { +SSI_SDATA8_MARK , +}; +static const unsigned int ssi8_data_b_pins[] = { +/* SDATA8 */ +RCAR_GP_PIN (3 ,28 ), +}; +static const unsigned int ssi8_data_b_mux[] = { +SSI_SDATA8_B_MARK , +}; +static const unsigned int ssi9_data_pins[] = { +/* SDATA9 */ +RCAR_GP_PIN (5 ,19 ), +}; +static const unsigned int ssi9_data_mux[] = { +SSI_SDATA9_MARK , +}; +static const unsigned int ssi9_ctrl_pins[] = { +/* SCK9, WS9 */ +RCAR_GP_PIN (5 ,17 ),RCAR_GP_PIN (5 ,18 ), +}; +static const unsigned int ssi9_ctrl_mux[] = { +SSI_SCK9_MARK ,SSI_WS9_MARK , +}; +static const unsigned int ssi9_data_b_pins[] = { +/* SDATA9 */ +RCAR_GP_PIN (4 ,19 ), +}; +static const unsigned int ssi9_data_b_mux[] = { +SSI_SDATA9_B_MARK , +}; +static const unsigned int ssi9_ctrl_b_pins[] = { +/* SCK9, WS9 */ +RCAR_GP_PIN (4 ,17 ),RCAR_GP_PIN (4 ,18 ), +}; +static const unsigned int ssi9_ctrl_b_mux[] = { +SSI_SCK9_B_MARK ,SSI_WS9_B_MARK , +};/* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = {RCAR_GP_PIN (5 ,24 ),/* PWEN */
@@ -3084,6 +3323,40 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (sdhi2_ctrl),SH_PFC_PIN_GROUP (sdhi2_cd),SH_PFC_PIN_GROUP (sdhi2_wp), +SH_PFC_PIN_GROUP (ssi0_data), +SH_PFC_PIN_GROUP (ssi0129_ctrl), +SH_PFC_PIN_GROUP (ssi1_data), +SH_PFC_PIN_GROUP (ssi1_ctrl), +SH_PFC_PIN_GROUP (ssi1_data_b), +SH_PFC_PIN_GROUP (ssi1_ctrl_b), +SH_PFC_PIN_GROUP (ssi2_data), +SH_PFC_PIN_GROUP (ssi2_ctrl), +SH_PFC_PIN_GROUP (ssi2_data_b), +SH_PFC_PIN_GROUP (ssi2_ctrl_b), +SH_PFC_PIN_GROUP (ssi3_data), +SH_PFC_PIN_GROUP (ssi34_ctrl), +SH_PFC_PIN_GROUP (ssi4_data), +SH_PFC_PIN_GROUP (ssi4_ctrl), +SH_PFC_PIN_GROUP (ssi4_data_b), +SH_PFC_PIN_GROUP (ssi4_ctrl_b), +SH_PFC_PIN_GROUP (ssi5_data), +SH_PFC_PIN_GROUP (ssi5_ctrl), +SH_PFC_PIN_GROUP (ssi5_data_b), +SH_PFC_PIN_GROUP (ssi5_ctrl_b), +SH_PFC_PIN_GROUP (ssi6_data), +SH_PFC_PIN_GROUP (ssi6_ctrl), +SH_PFC_PIN_GROUP (ssi6_data_b), +SH_PFC_PIN_GROUP (ssi6_ctrl_b), +SH_PFC_PIN_GROUP (ssi7_data), +SH_PFC_PIN_GROUP (ssi78_ctrl), +SH_PFC_PIN_GROUP (ssi7_data_b), +SH_PFC_PIN_GROUP (ssi78_ctrl_b), +SH_PFC_PIN_GROUP (ssi8_data), +SH_PFC_PIN_GROUP (ssi8_data_b), +SH_PFC_PIN_GROUP (ssi9_data), +SH_PFC_PIN_GROUP (ssi9_ctrl), +SH_PFC_PIN_GROUP (ssi9_data_b), +SH_PFC_PIN_GROUP (ssi9_ctrl_b),SH_PFC_PIN_GROUP (usb0),SH_PFC_PIN_GROUP (usb1), VIN_DATA_PIN_GROUP(vin0_data, 24),
@@ -3381,6 +3654,43 @@ static const char * const sdhi2_groups[] "sdhi2_wp", }; +static const char *const ssi_groups[] = { +"ssi0_data" , +"ssi0129_ctrl" , +"ssi1_data" , +"ssi1_ctrl" , +"ssi1_data_b" , +"ssi1_ctrl_b" , +"ssi2_data" , +"ssi2_ctrl" , +"ssi2_data_b" , +"ssi2_ctrl_b" , +"ssi3_data" , +"ssi34_ctrl" , +"ssi4_data" , +"ssi4_ctrl" , +"ssi4_data_b" , +"ssi4_ctrl_b" , +"ssi5_data" , +"ssi5_ctrl" , +"ssi5_data_b" , +"ssi5_ctrl_b" , +"ssi6_data" , +"ssi6_ctrl" , +"ssi6_data_b" , +"ssi6_ctrl_b" , +"ssi7_data" , +"ssi78_ctrl" , +"ssi7_data_b" , +"ssi78_ctrl_b" , +"ssi8_data" , +"ssi8_data_b" , +"ssi9_data" , +"ssi9_ctrl" , +"ssi9_data_b" , +"ssi9_ctrl_b" , +}; +static const char *const usb0_groups[] = {"usb0" , };
@@ -3448,6 +3758,7 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (sdhi0),SH_PFC_FUNCTION (sdhi1),SH_PFC_FUNCTION (sdhi2), +SH_PFC_FUNCTION (ssi),SH_PFC_FUNCTION (usb0),SH_PFC_FUNCTION (usb1), SH_PFC_FUNCTION(vin0),
Re: [PATCH 1/2] pinctrl: sh-pfc: r8a7794: add SSI pin groups
Quoted 11 lines · Sergei Shtylyov
From: Ryo Kataoka <[email protected]>
Add the SSI pin groups to the R8A7794 PFC driver.
[Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control ones, moved SSI7 data B group to its proper place, fixed pin names in the comments to *_pins[], extended Cogent Embedded's copyright, added the changelog, renamed the patch.]
Signed-off-by Ryo Kataoka <[email protected]>Signed-off-by Sergei Shtylyov <[email protected]>
These look fine to me, Acked-by for both.
Geert, will you & Laurent review and queue this please.
Yours,
Linus Walleij
Re: [PATCH 1/2] pinctrl: sh-pfc: r8a7794: add SSI pin groups
In reply to Sergei ShtylyovQuoted 21 lines · Sergei Shtylyov
From: Ryo Kataoka <[email protected]>
Add the SSI pin groups to the R8A7794 PFC driver.
[Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control ones, moved SSI7 data B group to its proper place, fixed pin names in the comments to *_pins[], extended Cogent Embedded's copyright, added the changelog, renamed the patch.]
Signed-off-by Ryo Kataoka <[email protected]>Signed-off-by Sergei Shtylyov <[email protected]>--- drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 315 ++++++++++++++++++++++++++++++++++- 1 file changed, 313 insertions(+), 2 deletions(-)Index:
linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
===================================================================
drivers/pinctrl/sh-pfc/pfc-r8a7794.c line 6
Quoted 8 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +2
-2@@ -1,9 +1,9 @@/* * r8a7794 processor support - PFC hardware block. * -* Copyright (C) 2014 Renesas Electronics Corporation +* Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Solutions Corp. -* Copyright (C) 2015 Cogent Embedded, Inc., <[email protected]> +* Copyright (C) 2015-2016 Cogent Embedded, Inc., <[email protected]>
Geert, could you turn the double space into single?
MBR, Sergei
Re: [PATCH 1/2] pinctrl: sh-pfc: r8a7794: add SSI pin groups
Hi Sergei,
Quoted 7 lines · Sergei Shtylyov
Quoted 7 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +0
-1@@ -1,9 +1,9 @@/* * r8a7794 processor support - PFC hardware block. * -* Copyright (C) 2014 Renesas Electronics Corporation
Quoted 8 lines
Quoted 5 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +2
-1+* Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Solutions Corp. -* Copyright (C) 2015 Cogent Embedded, Inc., <[email protected]> +* Copyright (C) 2015-2016 Cogent Embedded, Inc., Geert, could you turn the double space into single?
Sure, done.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/2] pinctrl: sh-pfc: r8a7794: add SSI pin groups
Hello.
Quoted 15 lines · Geert Uytterhoeven
Quoted 6 lines
Quoted 6 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +0
-0@@ -1,9 +1,9 @@/* * r8a7794 processor support - PFC hardware block. * Quoted 8 lines
Quoted 6 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +2
-2-* Copyright (C) 2014 Renesas Electronics Corporation +* Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Solutions Corp. -* Copyright (C) 2015 Cogent Embedded, Inc., <[email protected]> +* Copyright (C) 2015-2016 Cogent Embedded, Inc., Geert, could you turn the double space into single?
Quoted 1 line
Sure, done.
Thank you! Overlooked it. :-/
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
PATCH 2/2 pinctrl: sh-pfc: r8a7794: add audio clock pin groups
In reply to Sergei ShtylyovFrom: Ryo Kataoka <[email protected]>
Add the audio clock pin groups to the R8A7794 PFC driver.
[Sergei: fixed pin group names to reflect the reality, fixed pin names in the comments to *_pins[], lowercased the separator comment, resolved rejects, added the changelog, renamed the patch.]
--- drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 122 +++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +122 -0
@@ -1491,6 +1491,98 @@ static const struct sh_pfc_pin pinmux_pi PINMUX_GPIO_GP_ALL(), }; +/* - Audio Clock ------------------------------------------------------------ */ +static const unsigned int audio_clka_pins[] = { +/* CLKA */ +RCAR_GP_PIN (5 ,20 ), +}; +static const unsigned int audio_clka_mux[] = { +AUDIO_CLKA_MARK , +}; +static const unsigned int audio_clka_b_pins[] = { +/* CLKA */ +RCAR_GP_PIN (3 ,25 ), +}; +static const unsigned int audio_clka_b_mux[] = { +AUDIO_CLKA_B_MARK , +}; +static const unsigned int audio_clka_c_pins[] = { +/* CLKA */ +RCAR_GP_PIN (4 ,20 ), +}; +static const unsigned int audio_clka_c_mux[] = { +AUDIO_CLKA_C_MARK , +}; +static const unsigned int audio_clka_d_pins[] = { +/* CLKA */ +RCAR_GP_PIN (5 ,0 ), +}; +static const unsigned int audio_clka_d_mux[] = { +AUDIO_CLKA_D_MARK , +}; +static const unsigned int audio_clkb_pins[] = { +/* CLKB */ +RCAR_GP_PIN (5 ,21 ), +}; +static const unsigned int audio_clkb_mux[] = { +AUDIO_CLKB_MARK , +}; +static const unsigned int audio_clkb_b_pins[] = { +/* CLKB */ +RCAR_GP_PIN (3 ,26 ), +}; +static const unsigned int audio_clkb_b_mux[] = { +AUDIO_CLKB_B_MARK , +}; +static const unsigned int audio_clkb_c_pins[] = { +/* CLKB */ +RCAR_GP_PIN (4 ,21 ), +}; +static const unsigned int audio_clkb_c_mux[] = { +AUDIO_CLKB_C_MARK , +}; +static const unsigned int audio_clkc_pins[] = { +/* CLKC */ +RCAR_GP_PIN (5 ,22 ), +}; +static const unsigned int audio_clkc_mux[] = { +AUDIO_CLKC_MARK , +}; +static const unsigned int audio_clkc_b_pins[] = { +/* CLKC */ +RCAR_GP_PIN (3 ,29 ), +}; +static const unsigned int audio_clkc_b_mux[] = { +AUDIO_CLKC_B_MARK , +}; +static const unsigned int audio_clkc_c_pins[] = { +/* CLKC */ +RCAR_GP_PIN (4 ,22 ), +}; +static const unsigned int audio_clkc_c_mux[] = { +AUDIO_CLKC_C_MARK , +}; +static const unsigned int audio_clkout_pins[] = { +/* CLKOUT */ +RCAR_GP_PIN (5 ,23 ), +}; +static const unsigned int audio_clkout_mux[] = { +AUDIO_CLKOUT_MARK , +}; +static const unsigned int audio_clkout_b_pins[] = { +/* CLKOUT */ +RCAR_GP_PIN (3 ,12 ), +}; +static const unsigned int audio_clkout_b_mux[] = { +AUDIO_CLKOUT_B_MARK , +}; +static const unsigned int audio_clkout_c_pins[] = { +/* CLKOUT */ +RCAR_GP_PIN (4 ,23 ), +}; +static const unsigned int audio_clkout_c_mux[] = { +AUDIO_CLKOUT_C_MARK , +};/* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = {/* LINK */
@@ -3150,6 +3242,19 @@ static const unsigned int vin1_clk_mux[] };static const struct sh_pfc_pin_group pinmux_groups[] = { +SH_PFC_PIN_GROUP (audio_clka), +SH_PFC_PIN_GROUP (audio_clka_b), +SH_PFC_PIN_GROUP (audio_clka_c), +SH_PFC_PIN_GROUP (audio_clka_d), +SH_PFC_PIN_GROUP (audio_clkb), +SH_PFC_PIN_GROUP (audio_clkb_b), +SH_PFC_PIN_GROUP (audio_clkb_c), +SH_PFC_PIN_GROUP (audio_clkc), +SH_PFC_PIN_GROUP (audio_clkc_b), +SH_PFC_PIN_GROUP (audio_clkc_c), +SH_PFC_PIN_GROUP (audio_clkout), +SH_PFC_PIN_GROUP (audio_clkout_b), +SH_PFC_PIN_GROUP (audio_clkout_c),SH_PFC_PIN_GROUP (eth_link),SH_PFC_PIN_GROUP (eth_magic),SH_PFC_PIN_GROUP (eth_mdio),
@@ -3379,6 +3484,22 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(vin1_clk), }; +static const char *const audio_clk_groups[] = { +"audio_clka" , +"audio_clka_b" , +"audio_clka_c" , +"audio_clka_d" , +"audio_clkb" , +"audio_clkb_b" , +"audio_clkb_c" , +"audio_clkc" , +"audio_clkc_b" , +"audio_clkc_c" , +"audio_clkout" , +"audio_clkout_b" , +"audio_clkout_c" , +}; +static const char *const eth_groups[] = {"eth_link" ,"eth_magic" ,
@@ -3724,6 +3845,7 @@ static const char * const vin1_groups[] };static const struct sh_pfc_function pinmux_functions[] = { +SH_PFC_FUNCTION (audio_clk),SH_PFC_FUNCTION (eth),SH_PFC_FUNCTION (hscif0),SH_PFC_FUNCTION (hscif1),
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Here's the set of 2 patches against the 'devel' branch of Linus Walleij's
'linux-pinctrl.git' repo. Here we add the PFC support for the Renesas R8A7794 SSI devices and audio clocks.
Thanks!
Quoted 2 lines
[1/2] pinctrl: sh-pfc: r8a7794: add SSI pin groups [2/2] pinctrl: sh-pfc: r8a7794: add audio clock pin groups
Both
Will queue for renesas-drivers, and sh-pfc-for-v4.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7794: add EtherAVB pin groups
In reply to Sergei ShtylyovAdd the EtherAVB pin groups to the R8A7794 PFC driver.
Based on the patches by Mitsuhiro Kimura <[email protected]>.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus the SSI/audio clock patches posted last week.
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 123 +++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +123 -0
@@ -1583,6 +1583,105 @@ static const unsigned int audio_clkout_cstatic const unsigned int audio_clkout_c_mux[] = {AUDIO_CLKOUT_C_MARK , }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { +RCAR_GP_PIN (3 ,26 ), +}; +static const unsigned int avb_link_mux[] = { +AVB_LINK_MARK , +}; +static const unsigned int avb_magic_pins[] = { +RCAR_GP_PIN (3 ,27 ), +}; +static const unsigned int avb_magic_mux[] = { +AVB_MAGIC_MARK , +}; +static const unsigned int avb_phy_int_pins[] = { +RCAR_GP_PIN (3 ,28 ), +}; +static const unsigned int avb_phy_int_mux[] = { +AVB_PHY_INT_MARK , +}; +static const unsigned int avb_mdio_pins[] = { +RCAR_GP_PIN (3 ,24 ),RCAR_GP_PIN (3 ,25 ), +}; +static const unsigned int avb_mdio_mux[] = { +AVB_MDC_MARK ,AVB_MDIO_MARK , +}; +static const unsigned int avb_mii_pins[] = { +RCAR_GP_PIN (3 ,14 ),RCAR_GP_PIN (3 ,15 ),RCAR_GP_PIN (3 ,16 ), +RCAR_GP_PIN (3 ,17 ), + +RCAR_GP_PIN (3 ,2 ),RCAR_GP_PIN (3 ,3 ),RCAR_GP_PIN (3 ,4 ), +RCAR_GP_PIN (3 ,5 ), + +RCAR_GP_PIN (3 ,10 ),RCAR_GP_PIN (3 ,0 ),RCAR_GP_PIN (3 ,1 ), +RCAR_GP_PIN (3 ,29 ),RCAR_GP_PIN (3 ,12 ),RCAR_GP_PIN (3 ,22 ), +RCAR_GP_PIN (3 ,13 ),RCAR_GP_PIN (3 ,11 ), +}; +static const unsigned int avb_mii_mux[] = { +AVB_TXD0_MARK ,AVB_TXD1_MARK ,AVB_TXD2_MARK , +AVB_TXD3_MARK , + +AVB_RXD0_MARK ,AVB_RXD1_MARK ,AVB_RXD2_MARK , +AVB_RXD3_MARK , + +AVB_RX_ER_MARK ,AVB_RX_CLK_MARK ,AVB_RX_DV_MARK , +AVB_CRS_MARK ,AVB_TX_EN_MARK ,AVB_TX_ER_MARK , +AVB_TX_CLK_MARK ,AVB_COL_MARK , +}; +static const unsigned int avb_gmii_pins[] = { +RCAR_GP_PIN (3 ,14 ),RCAR_GP_PIN (3 ,15 ),RCAR_GP_PIN (3 ,16 ), +RCAR_GP_PIN (3 ,17 ),RCAR_GP_PIN (3 ,18 ),RCAR_GP_PIN (3 ,19 ), +RCAR_GP_PIN (3 ,20 ),RCAR_GP_PIN (3 ,21 ), + +RCAR_GP_PIN (3 ,2 ),RCAR_GP_PIN (3 ,3 ),RCAR_GP_PIN (3 ,4 ), +RCAR_GP_PIN (3 ,5 ),RCAR_GP_PIN (3 ,6 ),RCAR_GP_PIN (3 ,7 ), +RCAR_GP_PIN (3 ,8 ),RCAR_GP_PIN (3 ,9 ), + +RCAR_GP_PIN (3 ,10 ),RCAR_GP_PIN (3 ,0 ),RCAR_GP_PIN (3 ,1 ), +RCAR_GP_PIN (3 ,29 ),RCAR_GP_PIN (3 ,23 ),RCAR_GP_PIN (3 ,30 ), +RCAR_GP_PIN (3 ,12 ),RCAR_GP_PIN (3 ,22 ),RCAR_GP_PIN (3 ,13 ), +RCAR_GP_PIN (3 ,11 ), +}; +static const unsigned int avb_gmii_mux[] = { +AVB_TXD0_MARK ,AVB_TXD1_MARK ,AVB_TXD2_MARK , +AVB_TXD3_MARK ,AVB_TXD4_MARK ,AVB_TXD5_MARK , +AVB_TXD6_MARK ,AVB_TXD7_MARK , + +AVB_RXD0_MARK ,AVB_RXD1_MARK ,AVB_RXD2_MARK , +AVB_RXD3_MARK ,AVB_RXD4_MARK ,AVB_RXD5_MARK , +AVB_RXD6_MARK ,AVB_RXD7_MARK , + +AVB_RX_ER_MARK ,AVB_RX_CLK_MARK ,AVB_RX_DV_MARK , +AVB_CRS_MARK ,AVB_GTX_CLK_MARK ,AVB_GTXREFCLK_MARK , +AVB_TX_EN_MARK ,AVB_TX_ER_MARK ,AVB_TX_CLK_MARK , +AVB_COL_MARK , +}; +static const unsigned int avb_avtp_capture_pins[] = { +RCAR_GP_PIN (5 ,11 ), +}; +static const unsigned int avb_avtp_capture_mux[] = { +AVB_AVTP_CAPTURE_MARK , +}; +static const unsigned int avb_avtp_match_pins[] = { +RCAR_GP_PIN (5 ,12 ), +}; +static const unsigned int avb_avtp_match_mux[] = { +AVB_AVTP_MATCH_MARK , +}; +static const unsigned int avb_avtp_capture_b_pins[] = { +RCAR_GP_PIN (1 ,1 ), +}; +static const unsigned int avb_avtp_capture_b_mux[] = { +AVB_AVTP_CAPTURE_B_MARK , +}; +static const unsigned int avb_avtp_match_b_pins[] = { +RCAR_GP_PIN (1 ,2 ), +}; +static const unsigned int avb_avtp_match_b_mux[] = { +AVB_AVTP_MATCH_B_MARK , +};/* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = {/* LINK */
@@ -3255,6 +3354,16 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (audio_clkout),SH_PFC_PIN_GROUP (audio_clkout_b),SH_PFC_PIN_GROUP (audio_clkout_c), +SH_PFC_PIN_GROUP (avb_link), +SH_PFC_PIN_GROUP (avb_magic), +SH_PFC_PIN_GROUP (avb_phy_int), +SH_PFC_PIN_GROUP (avb_mdio), +SH_PFC_PIN_GROUP (avb_mii), +SH_PFC_PIN_GROUP (avb_gmii), +SH_PFC_PIN_GROUP (avb_avtp_capture), +SH_PFC_PIN_GROUP (avb_avtp_match), +SH_PFC_PIN_GROUP (avb_avtp_capture_b), +SH_PFC_PIN_GROUP (avb_avtp_match_b),SH_PFC_PIN_GROUP (eth_link),SH_PFC_PIN_GROUP (eth_magic), SH_PFC_PIN_GROUP(eth_mdio),
@@ -3500,6 +3609,19 @@ static const char * const audio_clk_grou "audio_clkout_c", }; +static const char *const avb_groups[] = { +"avb_link" , +"avb_magic" , +"avb_phy_int" , +"avb_mdio" , +"avb_mii" , +"avb_gmii" , +"avb_avtp_capture" , +"avb_avtp_match" , +"avb_avtp_capture_b" , +"avb_avtp_match_b" , +}; +static const char *const eth_groups[] = {"eth_link" ,"eth_magic" ,
@@ -3846,6 +3968,7 @@ static const char * const vin1_groups[]static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (audio_clk), +SH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (eth),SH_PFC_FUNCTION (hscif0),SH_PFC_FUNCTION (hscif1),
Re: [PATCH] pinctrl: sh-pfc: r8a7794: add EtherAVB pin groups
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7794 PFC driver.
Based on the patches by Mitsuhiro Kimura <[email protected]>.
Thank you for your patch!
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>
Quoted 14 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +14
-0+static const unsigned int avb_avtp_capture_pins[] = { +RCAR_GP_PIN (5 ,11 ), +}; +static const unsigned int avb_avtp_capture_mux[] = { +AVB_AVTP_CAPTURE_MARK , +}; +static const unsigned int avb_avtp_match_pins[] = { +RCAR_GP_PIN (5 ,12 ), +}; +static const unsigned int avb_avtp_match_mux[] = { +AVB_AVTP_MATCH_MARK , +}; +static const unsigned int avb_avtp_capture_b_pins[] = { +RCAR_GP_PIN (1 ,1 ),
drivers/pinctrl/sh-pfc/pfc-r8a7794.c static const unsigned int audio_clkout_c · line 1684
Quoted 10 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +10
-0+}; +static const unsigned int avb_avtp_capture_b_mux[] = { +AVB_AVTP_CAPTURE_B_MARK , +}; +static const unsigned int avb_avtp_match_b_pins[] = { +RCAR_GP_PIN (1 ,2 ), +}; +static const unsigned int avb_avtp_match_b_mux[] = { +AVB_AVTP_MATCH_B_MARK , +};
BTW, the capture pin seems to be available on R-Car E2 only. The match pin seems to be available on R-Car E2 and V2H only. The EtherAVB section in the datasheet doesn't clarify this. Do you know more?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] pinctrl: sh-pfc: r8a7794: add EtherAVB pin groups
Hello.
Quoted 28 lines · Geert Uytterhoeven
Quoted 3 lines
Add the EtherAVB pin groups to the R8A7794 PFC driver.
Based on the patches by Mitsuhiro Kimura <[email protected]>.
Thank you for your patch!
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Quoted 18 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +18
-0+static const unsigned int avb_avtp_capture_pins[] = { +RCAR_GP_PIN (5 ,11 ), +}; +static const unsigned int avb_avtp_capture_mux[] = { +AVB_AVTP_CAPTURE_MARK , +}; +static const unsigned int avb_avtp_match_pins[] = { +RCAR_GP_PIN (5 ,12 ), +}; +static const unsigned int avb_avtp_match_mux[] = { +AVB_AVTP_MATCH_MARK , +}; +static const unsigned int avb_avtp_capture_b_pins[] = { +RCAR_GP_PIN (1 ,1 ), +}; +static const unsigned int avb_avtp_capture_b_mux[] = { +AVB_AVTP_CAPTURE_B_MARK , +};
Quoted 8 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c static const unsigned int audio_clkout_c · line 1684
Quoted 6 lines
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +6
-0+static const unsigned int avb_avtp_match_b_pins[] = { +RCAR_GP_PIN (1 ,2 ), +}; +static const unsigned int avb_avtp_match_b_mux[] = { +AVB_AVTP_MATCH_B_MARK , +};BTW, the capture pin seems to be available on R-Car E2 only.
Yes, I've noticed.
Quoted 1 line
The match pin seems to be available on R-Car E2 and V2H only.
Don't have V2H manual, have to trust you. :-)
Quoted 2 lines
The EtherAVB section in the datasheet doesn't clarify this. Do you know more?
Unfortunately, no. I only know what AVTP in the pin name probably stands
for: Audio/Video Transport Protocol.
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
Re: [PATCH] pinctrl: sh-pfc: r8a7794: add EtherAVB pin groups
In reply to Geert UytterhoevenQuoted 11 lines · Geert Uytterhoeven
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7794 PFC driver.
Based on the patches by Mitsuhiro Kimura <[email protected]>.
Thank you for your patch!
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
I guess this means you're queueing it too?
Yours,
Linus Walleij
Re: [PATCH] pinctrl: sh-pfc: r8a7794: add EtherAVB pin groups
Quoted 9 lines · Linus Walleij
Quoted 6 lines · Geert Uytterhoeven
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7794 PFC driver.
Based on the patches by Mitsuhiro Kimura <[email protected]>.
Quoted 7 lines
Quoted 5 lines
Thank you for your patch!
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>I guess this means you're queueing it too?
Indeed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7794: fix GP2[29] muxing
In reply to Sergei ShtylyovFrom: Andrey Gusakov <[email protected]>
GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values are listed instead of 4...
[Sergei: fixed up the formatting, renamed, added the changelog.]
---
The patch is against the 'fixes' branch of Linus W.'s 'linux-pinctrl.git' repo.
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 1 + 1 file changed, 1 insertion(+)
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +1 -0
@@ -3974,6 +3974,7 @@ static const struct pinmux_cfg_reg pinmu FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,/* IP6_3_2 [2] */ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE ,FN_QCPV_QDE ,FN_CC50_STATE29 , + 0,/* IP6_1_0 [2] */ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } },
Re: [PATCH] pinctrl: sh-pfc: r8a7794: fix GP2[29] muxing
Quoted 9 lines · Sergei Shtylyov
From: Andrey Gusakov <[email protected]>
GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values are listed instead of 4...
[Sergei: fixed up the formatting, renamed, added the changelog.]
Signed-off-by Andrey Gusakov <[email protected]>Signed-off-by Sergei Shtylyov <[email protected]>
Thanks, nice catch!
I guess I have found a reason to queue up more stuff on sh-pfc-for-v4.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: core: only call pinctrl_provide_dummies() on SuperH
In reply to Sergei ShtylyovThe 'ravb' Ethernet driver couldn't connect to the PHY as the MDIO bus appeared empty on the Renesas R-Car boards. The bug hunt finally pointed at the commit adding the "init" pintcrl state: it tries to switch to non- default state before the driver probe which should fail but doesn't as the PFC pinctrl driver happens to call pinctrl_provide_dummies() which makes all state lookups succeed, even though the state doesn't really exist. That feature is only relevant to non-DT systems and all the ARM boards that use the PFC driver have been converted to the DT boot, so limiting it to the SuperH architecture seems The Right Thing...
---
The patch is against the 'fixes' branch of Linus W.'s 'linux-pinctrl.git' repo. As the bug only seems to happen to the hardware that's not pre-configured by U-Boot, this patch can wait till 4.6 in principle...
drivers/pinctrl/sh-pfc/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/pinctrl/sh-pfc/core.c +2 -1
@@ -545,7 +545,8 @@ static int sh_pfc_probe(struct platform_return ret; } -pinctrl_provide_dummies (); +if (IS_ENABLED (CONFIG_SUPERH )) +pinctrl_provide_dummies (); ret =sh_pfc_init_ranges (pfc);if (ret <0 )
Re: [PATCH] pinctrl: sh-pfc: core: only call pinctrl_provide_dummies() on SuperH
Quoted 10 lines · Sergei Shtylyov
The 'ravb' Ethernet driver couldn't connect to the PHY as the MDIO bus appeared empty on the Renesas R-Car boards. The bug hunt finally pointed at the commit adding the "init" pintcrl state: it tries to switch to non- default state before the driver probe which should fail but doesn't as the PFC pinctrl driver happens to call
pinctrl_provide_dummies()which makes all state lookups succeed, even though the state doesn't really exist. That feature is only relevant to non-DT systems and all the ARM boards that use the PFC driver have been converted to the DT boot, so limiting it to the SuperH architecture seems The Right Thing...
Quoted 3 lines
Fixes ef0eebc05130 ("drivers/pinctrl: Add the concept of an "init" state")Signed-off-by Sergei Shtylyov <[email protected]>
Putting this on hold because another patch is being discussed as a more proper fix.
Yours,
Linus Walleij
Re: [PATCH] pinctrl: sh-pfc: core: only call pinctrl_provide_dummies() on SuperH
Hello.
Quoted 10 lines · Linus Walleij
Quoted 10 lines
The 'ravb' Ethernet driver couldn't connect to the PHY as the MDIO bus appeared empty on the Renesas R-Car boards. The bug hunt finally pointed at the commit adding the "init" pintcrl state: it tries to switch to non- default state before the driver probe which should fail but doesn't as the PFC pinctrl driver happens to call
pinctrl_provide_dummies()which makes all state lookups succeed, even though the state doesn't really exist. That feature is only relevant to non-DT systems and all the ARM boards that use the PFC driver have been converted to the DT boot, so limiting it to the SuperH architecture seems The Right Thing...
Quoted 6 lines
Quoted 3 lines
Fixes ef0eebc05130 ("drivers/pinctrl: Add the concept of an "init" state")Signed-off-by Sergei Shtylyov <[email protected]>Putting this on hold because another patch is being discussed as a more proper fix.
Sigh, I had that variant of the fix too but erroneously thought thatof_have_populated_dt() could only be used with CONFIG_OF=y, so didn't publish that variant... Had no idea someone else's working on the same issue.
Quoted 2 lines
Yours,
Linus Walleij
MBR, Sergei
PATCH v2 1/1 pinctrl: sh-pfc: r8a7794: Add DU pin groups
In reply to Sergei ShtylyovFrom: Koji Matsuoka <[email protected]>
r8a7794 PFC DU support from the R-Car Gen2 v1.9.4 BSP
[Magnus: added the description, added missing dot clock output signals, separated CDE and DISP signals, broke out the ODDF signal from the sync group.]
[Sergei: resolved rejects, folded in Magnus' patches, killed empty lines, reordered pin/mux arrays and pin groups, fixed up some comments to the pin arrays, removed the "du" function splitting its groups between the "du0" and "du1" functions.]
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'.
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 217 +++++++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7794.c +217 -0
@@ -1682,6 +1682,179 @@ static const unsigned int avb_avtp_matchstatic const unsigned int avb_avtp_match_b_mux[] = {AVB_AVTP_MATCH_B_MARK , }; +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { +/* R[7:2], G[7:2], B[7:2] */ +RCAR_GP_PIN (2 ,7 ),RCAR_GP_PIN (2 ,6 ),RCAR_GP_PIN (2 ,5 ), +RCAR_GP_PIN (2 ,4 ),RCAR_GP_PIN (2 ,3 ),RCAR_GP_PIN (2 ,2 ), +RCAR_GP_PIN (2 ,15 ),RCAR_GP_PIN (2 ,14 ),RCAR_GP_PIN (2 ,13 ), +RCAR_GP_PIN (2 ,12 ),RCAR_GP_PIN (2 ,11 ),RCAR_GP_PIN (2 ,10 ), +RCAR_GP_PIN (2 ,23 ),RCAR_GP_PIN (2 ,22 ),RCAR_GP_PIN (2 ,21 ), +RCAR_GP_PIN (2 ,20 ),RCAR_GP_PIN (2 ,19 ),RCAR_GP_PIN (2 ,18 ), +}; +static const unsigned int du0_rgb666_mux[] = { +DU0_DR7_MARK ,DU0_DR6_MARK ,DU0_DR5_MARK ,DU0_DR4_MARK , +DU0_DR3_MARK ,DU0_DR2_MARK , +DU0_DG7_MARK ,DU0_DG6_MARK ,DU0_DG5_MARK ,DU0_DG4_MARK , +DU0_DG3_MARK ,DU0_DG2_MARK , +DU0_DB7_MARK ,DU0_DB6_MARK ,DU0_DB5_MARK ,DU0_DB4_MARK , +DU0_DB3_MARK ,DU0_DB2_MARK , +}; +static const unsigned int du0_rgb888_pins[] = { +/* R[7:0], G[7:0], B[7:0] */ +RCAR_GP_PIN (2 ,7 ),RCAR_GP_PIN (2 ,6 ),RCAR_GP_PIN (2 ,5 ), +RCAR_GP_PIN (2 ,4 ),RCAR_GP_PIN (2 ,3 ),RCAR_GP_PIN (2 ,2 ), +RCAR_GP_PIN (2 ,1 ),RCAR_GP_PIN (2 ,0 ), +RCAR_GP_PIN (2 ,15 ),RCAR_GP_PIN (2 ,14 ),RCAR_GP_PIN (2 ,13 ), +RCAR_GP_PIN (2 ,12 ),RCAR_GP_PIN (2 ,11 ),RCAR_GP_PIN (2 ,10 ), +RCAR_GP_PIN (2 ,9 ),RCAR_GP_PIN (2 ,8 ), +RCAR_GP_PIN (2 ,23 ),RCAR_GP_PIN (2 ,22 ),RCAR_GP_PIN (2 ,21 ), +RCAR_GP_PIN (2 ,20 ),RCAR_GP_PIN (2 ,19 ),RCAR_GP_PIN (2 ,18 ), +RCAR_GP_PIN (2 ,17 ),RCAR_GP_PIN (2 ,16 ), +}; +static const unsigned int du0_rgb888_mux[] = { +DU0_DR7_MARK ,DU0_DR6_MARK ,DU0_DR5_MARK ,DU0_DR4_MARK , +DU0_DR3_MARK ,DU0_DR2_MARK ,DU0_DR1_MARK ,DU0_DR0_MARK , +DU0_DG7_MARK ,DU0_DG6_MARK ,DU0_DG5_MARK ,DU0_DG4_MARK , +DU0_DG3_MARK ,DU0_DG2_MARK ,DU0_DG1_MARK ,DU0_DG0_MARK , +DU0_DB7_MARK ,DU0_DB6_MARK ,DU0_DB5_MARK ,DU0_DB4_MARK , +DU0_DB3_MARK ,DU0_DB2_MARK ,DU0_DB1_MARK ,DU0_DB0_MARK , +}; +static const unsigned int du0_clk0_out_pins[] = { +/* DOTCLKOUT0 */ +RCAR_GP_PIN (2 ,25 ), +}; +static const unsigned int du0_clk0_out_mux[] = { +DU0_DOTCLKOUT0_MARK +}; +static const unsigned int du0_clk1_out_pins[] = { +/* DOTCLKOUT1 */ +RCAR_GP_PIN (2 ,26 ), +}; +static const unsigned int du0_clk1_out_mux[] = { +DU0_DOTCLKOUT1_MARK +}; +static const unsigned int du0_clk_in_pins[] = { +/* CLKIN */ +RCAR_GP_PIN (2 ,24 ), +}; +static const unsigned int du0_clk_in_mux[] = { +DU0_DOTCLKIN_MARK +}; +static const unsigned int du0_sync_pins[] = { +/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ +RCAR_GP_PIN (2 ,28 ),RCAR_GP_PIN (2 ,27 ), +}; +static const unsigned int du0_sync_mux[] = { +DU0_EXVSYNC_DU0_VSYNC_MARK ,DU0_EXHSYNC_DU0_HSYNC_MARK +}; +static const unsigned int du0_oddf_pins[] = { +/* EXODDF/ODDF/DISP/CDE */ +RCAR_GP_PIN (2 ,29 ), +}; +static const unsigned int du0_oddf_mux[] = { +DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK , +}; +static const unsigned int du0_cde_pins[] = { +/* CDE */ +RCAR_GP_PIN (2 ,31 ), +}; +static const unsigned int du0_cde_mux[] = { +DU0_CDE_MARK , +}; +static const unsigned int du0_disp_pins[] = { +/* DISP */ +RCAR_GP_PIN (2 ,30 ), +}; +static const unsigned int du0_disp_mux[] = { +DU0_DISP_MARK +}; +static const unsigned int du1_rgb666_pins[] = { +/* R[7:2], G[7:2], B[7:2] */ +RCAR_GP_PIN (4 ,7 ),RCAR_GP_PIN (4 ,6 ),RCAR_GP_PIN (4 ,5 ), +RCAR_GP_PIN (4 ,4 ),RCAR_GP_PIN (4 ,3 ),RCAR_GP_PIN (4 ,2 ), +RCAR_GP_PIN (4 ,15 ),RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,13 ), +RCAR_GP_PIN (4 ,12 ),RCAR_GP_PIN (4 ,11 ),RCAR_GP_PIN (4 ,10 ), +RCAR_GP_PIN (4 ,23 ),RCAR_GP_PIN (4 ,22 ),RCAR_GP_PIN (4 ,21 ), +RCAR_GP_PIN (4 ,20 ),RCAR_GP_PIN (4 ,19 ),RCAR_GP_PIN (4 ,18 ), +}; +static const unsigned int du1_rgb666_mux[] = { +DU1_DR7_MARK ,DU1_DR6_MARK ,DU1_DR5_MARK ,DU1_DR4_MARK , +DU1_DR3_MARK ,DU1_DR2_MARK , +DU1_DG7_MARK ,DU1_DG6_MARK ,DU1_DG5_MARK ,DU1_DG4_MARK , +DU1_DG3_MARK ,DU1_DG2_MARK , +DU1_DB7_MARK ,DU1_DB6_MARK ,DU1_DB5_MARK ,DU1_DB4_MARK , +DU1_DB3_MARK ,DU1_DB2_MARK , +}; +static const unsigned int du1_rgb888_pins[] = { +/* R[7:0], G[7:0], B[7:0] */ +RCAR_GP_PIN (4 ,7 ),RCAR_GP_PIN (4 ,6 ),RCAR_GP_PIN (4 ,5 ), +RCAR_GP_PIN (4 ,4 ),RCAR_GP_PIN (4 ,3 ),RCAR_GP_PIN (4 ,2 ), +RCAR_GP_PIN (4 ,1 ),RCAR_GP_PIN (4 ,0 ), +RCAR_GP_PIN (4 ,15 ),RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,13 ), +RCAR_GP_PIN (4 ,12 ),RCAR_GP_PIN (4 ,11 ),RCAR_GP_PIN (4 ,10 ), +RCAR_GP_PIN (4 ,9 ),RCAR_GP_PIN (4 ,8 ), +RCAR_GP_PIN (4 ,23 ),RCAR_GP_PIN (4 ,22 ),RCAR_GP_PIN (4 ,21 ), +RCAR_GP_PIN (4 ,20 ),RCAR_GP_PIN (4 ,19 ),RCAR_GP_PIN (4 ,18 ), +RCAR_GP_PIN (4 ,17 ),RCAR_GP_PIN (4 ,16 ), +}; +static const unsigned int du1_rgb888_mux[] = { +DU1_DR7_MARK ,DU1_DR6_MARK ,DU1_DR5_MARK ,DU1_DR4_MARK , +DU1_DR3_MARK ,DU1_DR2_MARK ,DU1_DR1_MARK ,DU1_DR0_MARK , +DU1_DG7_MARK ,DU1_DG6_MARK ,DU1_DG5_MARK ,DU1_DG4_MARK , +DU1_DG3_MARK ,DU1_DG2_MARK ,DU1_DG1_MARK ,DU1_DG0_MARK , +DU1_DB7_MARK ,DU1_DB6_MARK ,DU1_DB5_MARK ,DU1_DB4_MARK , +DU1_DB3_MARK ,DU1_DB2_MARK ,DU1_DB1_MARK ,DU1_DB0_MARK , +}; +static const unsigned int du1_clk0_out_pins[] = { +/* DOTCLKOUT0 */ +RCAR_GP_PIN (4 ,25 ), +}; +static const unsigned int du1_clk0_out_mux[] = { +DU1_DOTCLKOUT0_MARK +}; +static const unsigned int du1_clk1_out_pins[] = { +/* DOTCLKOUT1 */ +RCAR_GP_PIN (4 ,26 ), +}; +static const unsigned int du1_clk1_out_mux[] = { +DU1_DOTCLKOUT1_MARK +}; +static const unsigned int du1_clk_in_pins[] = { +/* DOTCLKIN */ +RCAR_GP_PIN (4 ,24 ), +}; +static const unsigned int du1_clk_in_mux[] = { +DU1_DOTCLKIN_MARK +}; +static const unsigned int du1_sync_pins[] = { +/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ +RCAR_GP_PIN (4 ,28 ),RCAR_GP_PIN (4 ,27 ), +}; +static const unsigned int du1_sync_mux[] = { +DU1_EXVSYNC_DU1_VSYNC_MARK ,DU1_EXHSYNC_DU1_HSYNC_MARK +}; +static const unsigned int du1_oddf_pins[] = { +/* EXODDF/ODDF/DISP/CDE */ +RCAR_GP_PIN (4 ,29 ), +}; +static const unsigned int du1_oddf_mux[] = { +DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK , +}; +static const unsigned int du1_cde_pins[] = { +/* CDE */ +RCAR_GP_PIN (4 ,31 ), +}; +static const unsigned int du1_cde_mux[] = { +DU1_CDE_MARK +}; +static const unsigned int du1_disp_pins[] = { +/* DISP */ +RCAR_GP_PIN (4 ,30 ), +}; +static const unsigned int du1_disp_mux[] = { +DU1_DISP_MARK +};/* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = {/* LINK */
@@ -3364,6 +3537,24 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (avb_avtp_match),SH_PFC_PIN_GROUP (avb_avtp_capture_b),SH_PFC_PIN_GROUP (avb_avtp_match_b), +SH_PFC_PIN_GROUP (du0_rgb666), +SH_PFC_PIN_GROUP (du0_rgb888), +SH_PFC_PIN_GROUP (du0_clk0_out), +SH_PFC_PIN_GROUP (du0_clk1_out), +SH_PFC_PIN_GROUP (du0_clk_in), +SH_PFC_PIN_GROUP (du0_sync), +SH_PFC_PIN_GROUP (du0_oddf), +SH_PFC_PIN_GROUP (du0_cde), +SH_PFC_PIN_GROUP (du0_disp), +SH_PFC_PIN_GROUP (du1_rgb666), +SH_PFC_PIN_GROUP (du1_rgb888), +SH_PFC_PIN_GROUP (du1_clk0_out), +SH_PFC_PIN_GROUP (du1_clk1_out), +SH_PFC_PIN_GROUP (du1_clk_in), +SH_PFC_PIN_GROUP (du1_sync), +SH_PFC_PIN_GROUP (du1_oddf), +SH_PFC_PIN_GROUP (du1_cde), +SH_PFC_PIN_GROUP (du1_disp),SH_PFC_PIN_GROUP (eth_link),SH_PFC_PIN_GROUP (eth_magic), SH_PFC_PIN_GROUP(eth_mdio),
@@ -3622,6 +3813,30 @@ static const char * const avb_groups[] = "avb_avtp_match_b", }; +static const char *const du0_groups[] = { +"du0_rgb666" , +"du0_rgb888" , +"du0_clk0_out" , +"du0_clk1_out" , +"du0_clk_in" , +"du0_sync" , +"du0_oddf" , +"du0_cde" , +"du0_disp" , +}; + +static const char *const du1_groups[] = { +"du1_rgb666" , +"du1_rgb888" , +"du1_clk0_out" , +"du1_clk1_out" , +"du1_clk_in" , +"du1_sync" , +"du1_oddf" , +"du1_cde" , +"du1_disp" , +}; +static const char *const eth_groups[] = {"eth_link" ,"eth_magic" ,
@@ -3969,6 +4184,8 @@ static const char * const vin1_groups[]static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (audio_clk),SH_PFC_FUNCTION (avb), +SH_PFC_FUNCTION (du0), +SH_PFC_FUNCTION (du1),SH_PFC_FUNCTION (eth),SH_PFC_FUNCTION (hscif0),SH_PFC_FUNCTION (hscif1),
Re: [PATCH v2] pinctrl: sh-pfc: r8a7794: Add DU pin groups
Quoted 8 lines · Sergei Shtylyov
From: Koji Matsuoka <[email protected]>
r8a7794 PFC DU support from the R-Car Gen2 v1.9.4 BSP
[Magnus: added the description, added missing dot clock output signals, separated CDE and DISP signals, broke out the ODDF signal from the sync group.]
Quoted 8 lines
[Sergei: resolved rejects, folded in Magnus' patches, killed empty lines, reordered pin/mux arrays and pin groups, fixed up some comments to the pin arrays, removed the "du" function splitting its groups between the "du0" and "du1" functions.]
Signed-off-by Koji Matsuoka <[email protected]>Signed-off-by Magnus Damm <[email protected]>Signed-off-by Sergei Shtylyov <[email protected]>
Looks fine to me, Geert do you want to stack more stuff or should I apply it directly?
Quoted 2 lines
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'.
I just pulled a first set of new stuff from Geert. Will it apply on top?
Yours,
Linus Walleij
Re: [PATCH v2] pinctrl: sh-pfc: r8a7794: Add DU pin groups
In reply to Sergei ShtylyovHi Sergei,
Quoted 8 lines · Sergei Shtylyov
From: Koji Matsuoka <[email protected]>
r8a7794 PFC DU support from the R-Car Gen2 v1.9.4 BSP
[Magnus: added the description, added missing dot clock output signals, separated CDE and DISP signals, broke out the ODDF signal from the sync group.]
Quoted 8 lines
[Sergei: resolved rejects, folded in Magnus' patches, killed empty lines, reordered pin/mux arrays and pin groups, fixed up some comments to the pin arrays, removed the "du" function splitting its groups between the "du0" and "du1" functions.]
Signed-off-by Koji Matsuoka <[email protected]>Signed-off-by Magnus Damm <[email protected]>Signed-off-by Sergei Shtylyov <[email protected]>
Thanks, will queue in sh-pfc-for-v4.7 for a second pull request.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
In reply to Sergei ShtylyovAdd the EtherAVB pin groups to the R8A7792 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 2 PFC patches posted last week...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 91 +++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +91 -0
@@ -728,6 +728,81 @@ static const struct sh_pfc_pin pinmux_pi PINMUX_GPIO_GP_ALL(), }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { +RCAR_GP_PIN (7 ,9 ), +}; +static const unsigned int avb_link_mux[] = { +AVB_LINK_MARK , +}; +static const unsigned int avb_magic_pins[] = { +RCAR_GP_PIN (7 ,10 ), +}; +static const unsigned int avb_magic_mux[] = { +AVB_MAGIC_MARK , +}; +static const unsigned int avb_phy_int_pins[] = { +RCAR_GP_PIN (7 ,11 ), +}; +static const unsigned int avb_phy_int_mux[] = { +AVB_PHY_INT_MARK , +}; +static const unsigned int avb_mdio_pins[] = { +RCAR_GP_PIN (7 ,7 ),RCAR_GP_PIN (7 ,8 ), +}; +static const unsigned int avb_mdio_mux[] = { +AVB_MDC_MARK ,AVB_MDIO_MARK , +}; +static const unsigned int avb_mii_pins[] = { +RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ),RCAR_GP_PIN (6 ,16 ), +RCAR_GP_PIN (6 ,12 ), + +RCAR_GP_PIN (6 ,2 ),RCAR_GP_PIN (6 ,3 ),RCAR_GP_PIN (6 ,4 ), +RCAR_GP_PIN (6 ,5 ), + +RCAR_GP_PIN (6 ,10 ),RCAR_GP_PIN (6 ,0 ),RCAR_GP_PIN (6 ,1 ), +RCAR_GP_PIN (7 ,12 ),RCAR_GP_PIN (6 ,13 ),RCAR_GP_PIN (7 ,5 ), +RCAR_GP_PIN (7 ,0 ),RCAR_GP_PIN (6 ,11 ), +}; +static const unsigned int avb_mii_mux[] = { +AVB_TXD0_MARK ,AVB_TXD1_MARK ,AVB_TXD2_MARK , +AVB_TXD3_MARK , + +AVB_RXD0_MARK ,AVB_RXD1_MARK ,AVB_RXD2_MARK , +AVB_RXD3_MARK , + +AVB_RX_ER_MARK ,AVB_RX_CLK_MARK ,AVB_RX_DV_MARK , +AVB_CRS_MARK ,AVB_TX_EN_MARK ,AVB_TX_ER_MARK , +AVB_TX_CLK_MARK ,AVB_COL_MARK , +}; +static const unsigned int avb_gmii_pins[] = { +RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ),RCAR_GP_PIN (6 ,16 ), +RCAR_GP_PIN (6 ,12 ),RCAR_GP_PIN (7 ,1 ),RCAR_GP_PIN (7 ,2 ), +RCAR_GP_PIN (7 ,3 ),RCAR_GP_PIN (7 ,4 ), + +RCAR_GP_PIN (6 ,2 ),RCAR_GP_PIN (6 ,3 ),RCAR_GP_PIN (6 ,4 ), +RCAR_GP_PIN (6 ,5 ),RCAR_GP_PIN (6 ,6 ),RCAR_GP_PIN (6 ,7 ), +RCAR_GP_PIN (6 ,8 ),RCAR_GP_PIN (6 ,9 ), + +RCAR_GP_PIN (6 ,10 ),RCAR_GP_PIN (6 ,0 ),RCAR_GP_PIN (6 ,1 ), +RCAR_GP_PIN (7 ,12 ),RCAR_GP_PIN (7 ,6 ),RCAR_GP_PIN (7 ,13 ), +RCAR_GP_PIN (6 ,13 ),RCAR_GP_PIN (7 ,5 ),RCAR_GP_PIN (7 ,0 ), +RCAR_GP_PIN (6 ,11 ), +}; +static const unsigned int avb_gmii_mux[] = { +AVB_TXD0_MARK ,AVB_TXD1_MARK ,AVB_TXD2_MARK , +AVB_TXD3_MARK ,AVB_TXD4_MARK ,AVB_TXD5_MARK , +AVB_TXD6_MARK ,AVB_TXD7_MARK , + +AVB_RXD0_MARK ,AVB_RXD1_MARK ,AVB_RXD2_MARK , +AVB_RXD3_MARK ,AVB_RXD4_MARK ,AVB_RXD5_MARK , +AVB_RXD6_MARK ,AVB_RXD7_MARK , + +AVB_RX_ER_MARK ,AVB_RX_CLK_MARK ,AVB_RX_DV_MARK , +AVB_CRS_MARK ,AVB_GTX_CLK_MARK ,AVB_GTXREFCLK_MARK , +AVB_TX_EN_MARK ,AVB_TX_ER_MARK ,AVB_TX_CLK_MARK , +AVB_COL_MARK , +};/* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = {/* IRQ0 */
@@ -853,6 +928,12 @@ static const unsigned int scif3_clk_mux[ };static const struct sh_pfc_pin_group pinmux_groups[] = { +SH_PFC_PIN_GROUP (avb_link), +SH_PFC_PIN_GROUP (avb_magic), +SH_PFC_PIN_GROUP (avb_phy_int), +SH_PFC_PIN_GROUP (avb_mdio), +SH_PFC_PIN_GROUP (avb_mii), +SH_PFC_PIN_GROUP (avb_gmii),SH_PFC_PIN_GROUP (intc_irq0),SH_PFC_PIN_GROUP (intc_irq1),SH_PFC_PIN_GROUP (intc_irq2),
@@ -872,6 +953,15 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(scif3_clk), }; +static const char *const avb_groups[] = { +"avb_link" , +"avb_magic" , +"avb_phy_int" , +"avb_mdio" , +"avb_mii" , +"avb_gmii" , +}; +static const char *const intc_groups[] = {"intc_irq0" ,"intc_irq1" ,
@@ -902,6 +992,7 @@ static const char * const scif3_groups[] };static const struct sh_pfc_function pinmux_functions[] = { +SH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc),SH_PFC_FUNCTION (scif0),
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>
However, you forgot to add the avb_avtp_match group. Is that intentional?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Hello.
Quoted 8 lines · Geert Uytterhoeven
Quoted 3 lines
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>However, you forgot to add the
avb_avtp_matchgroup. Is that intentional?
No, it didn't get created in the original Renesas patch and I forgot about it.
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
In reply to Geert UytterhoevenQuoted 9 lines · Geert Uytterhoeven
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Should I just apply it?
It's late in the kernel cycle but I do not mind stuff like this so much.
Yours,
Linus Walleij
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Hi Linus,
Quoted 7 lines · Linus Walleij
Quoted 6 lines · Geert Uytterhoeven
Hi Sergei,
Quoted 2 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Should I just apply it?
It's late in the kernel cycle but I do not mind stuff like this so much.
You can't, as I haven't send a pull request for the initial r8a7792 support yet, so this patch won't apply ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Quoted 12 lines · Geert Uytterhoeven
Quoted 11 lines · Linus Walleij
Quoted 9 lines · Geert Uytterhoeven
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Quoted 7 lines
Quoted 4 lines
Should I just apply it?
It's late in the kernel cycle but I do not mind stuff like this so much.
You can't, as I haven't send a pull request for the initial r8a7792 support yet, so this patch won't apply ;-)
Bring it on. None of your stuff has ever bit me so I'm still happy to pull in some more Renesas stuff.
Yours,
Linus Walleij
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Quoted 8 lines · Linus Walleij
Quoted 8 lines
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Should I just apply it?
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
It's late in the kernel cycle but I do not mind stuff like this so much.
You can't, as I haven't send a pull request for the initial r8a7792 support yet, so this patch won't apply ;-)
Bring it on. None of your stuff has ever bit me so I'm still happy to pull in some more Renesas stuff.
Geert was going to take the rest of week off. This patch needs a bit more
work but you can merge the 2-patch series that this one's based on. I would be really thankful if so. :-)
Quoted 2 lines
Yours,
Linus Walleij
MBR, Sergei
PATCH 1/1 gpio: rcar: document R8A7792 support
In reply to Sergei ShtylyovRenesas R8A7792 SoC is a member of the R-Car gen2 family that is supported by the Renesas R-Car GPIO driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-gpio.git' repo.
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +1 -0
@@ -7,6 +7,7 @@ Required Properties: - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. + - "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller. - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
Re: [PATCH] gpio: rcar: document R8A7792 support
Quoted 4 lines · Sergei Shtylyov
Renesas R8A7792 SoC is a member of the R-Car gen2 family that is supported by the Renesas R-Car GPIO driver.
Signed-off-by Sergei Shtylyov <[email protected]>
[...]
Scratch this, the driver needs modification too... :-/
MBR, Sergei
PATCH 1/1 gpio: rcar: add R8A7792 support
In reply to Sergei ShtylyovRenesas R8A7792 SoC is a member of the R-Car gen2 family, add support for its GPIO controllers.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-gpio.git' repo. It replaces previously posted patch "gpio: rcar: document R8A7792 support."
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + drivers/gpio/gpio-rcar.c | 3 +++ 2 files changed, 4 insertions(+)
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +1 -0
@@ -7,6 +7,7 @@ Required Properties: - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. + - "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller. - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
drivers/gpio/gpio-rcar.c +3 -0
@@ -335,6 +335,9 @@ static const struct of_device_id gpio_rc .compatible = "renesas,gpio-r8a7791", .data = &gpio_rcar_info_gen2, }, { + .compatible = "renesas,gpio-r8a7792", + .data = &gpio_rcar_info_gen2, + }, { .compatible = "renesas,gpio-r8a7793", .data = &gpio_rcar_info_gen2, }, {
Re: [PATCH] gpio: rcar: add R8A7792 support
Quoted 4 lines · Sergei Shtylyov
Renesas R8A7792 SoC is a member of the R-Car gen2 family, add support for its GPIO controllers.
Signed-off-by Sergei Shtylyov <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH v2 1/1 pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
In reply to Sergei ShtylyovAdd the EtherAVB pin groups to the R8A7792 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 2 R8A7792 PFC patches posted before...
Changes in version 2:
- added AVB_AVTP_MATCH pin group.
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 99 +++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +99 -0
@@ -728,6 +728,87 @@ static const struct sh_pfc_pin pinmux_pi PINMUX_GPIO_GP_ALL(), }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { +RCAR_GP_PIN (7 ,9 ), +}; +static const unsigned int avb_link_mux[] = { +AVB_LINK_MARK , +}; +static const unsigned int avb_magic_pins[] = { +RCAR_GP_PIN (7 ,10 ), +}; +static const unsigned int avb_magic_mux[] = { +AVB_MAGIC_MARK , +}; +static const unsigned int avb_phy_int_pins[] = { +RCAR_GP_PIN (7 ,11 ), +}; +static const unsigned int avb_phy_int_mux[] = { +AVB_PHY_INT_MARK , +}; +static const unsigned int avb_mdio_pins[] = { +RCAR_GP_PIN (7 ,7 ),RCAR_GP_PIN (7 ,8 ), +}; +static const unsigned int avb_mdio_mux[] = { +AVB_MDC_MARK ,AVB_MDIO_MARK , +}; +static const unsigned int avb_mii_pins[] = { +RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ),RCAR_GP_PIN (6 ,16 ), +RCAR_GP_PIN (6 ,12 ), + +RCAR_GP_PIN (6 ,2 ),RCAR_GP_PIN (6 ,3 ),RCAR_GP_PIN (6 ,4 ), +RCAR_GP_PIN (6 ,5 ), + +RCAR_GP_PIN (6 ,10 ),RCAR_GP_PIN (6 ,0 ),RCAR_GP_PIN (6 ,1 ), +RCAR_GP_PIN (7 ,12 ),RCAR_GP_PIN (6 ,13 ),RCAR_GP_PIN (7 ,5 ), +RCAR_GP_PIN (7 ,0 ),RCAR_GP_PIN (6 ,11 ), +}; +static const unsigned int avb_mii_mux[] = { +AVB_TXD0_MARK ,AVB_TXD1_MARK ,AVB_TXD2_MARK , +AVB_TXD3_MARK , + +AVB_RXD0_MARK ,AVB_RXD1_MARK ,AVB_RXD2_MARK , +AVB_RXD3_MARK , + +AVB_RX_ER_MARK ,AVB_RX_CLK_MARK ,AVB_RX_DV_MARK , +AVB_CRS_MARK ,AVB_TX_EN_MARK ,AVB_TX_ER_MARK , +AVB_TX_CLK_MARK ,AVB_COL_MARK , +}; +static const unsigned int avb_gmii_pins[] = { +RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ),RCAR_GP_PIN (6 ,16 ), +RCAR_GP_PIN (6 ,12 ),RCAR_GP_PIN (7 ,1 ),RCAR_GP_PIN (7 ,2 ), +RCAR_GP_PIN (7 ,3 ),RCAR_GP_PIN (7 ,4 ), + +RCAR_GP_PIN (6 ,2 ),RCAR_GP_PIN (6 ,3 ),RCAR_GP_PIN (6 ,4 ), +RCAR_GP_PIN (6 ,5 ),RCAR_GP_PIN (6 ,6 ),RCAR_GP_PIN (6 ,7 ), +RCAR_GP_PIN (6 ,8 ),RCAR_GP_PIN (6 ,9 ), + +RCAR_GP_PIN (6 ,10 ),RCAR_GP_PIN (6 ,0 ),RCAR_GP_PIN (6 ,1 ), +RCAR_GP_PIN (7 ,12 ),RCAR_GP_PIN (7 ,6 ),RCAR_GP_PIN (7 ,13 ), +RCAR_GP_PIN (6 ,13 ),RCAR_GP_PIN (7 ,5 ),RCAR_GP_PIN (7 ,0 ), +RCAR_GP_PIN (6 ,11 ), +}; +static const unsigned int avb_gmii_mux[] = { +AVB_TXD0_MARK ,AVB_TXD1_MARK ,AVB_TXD2_MARK , +AVB_TXD3_MARK ,AVB_TXD4_MARK ,AVB_TXD5_MARK , +AVB_TXD6_MARK ,AVB_TXD7_MARK , + +AVB_RXD0_MARK ,AVB_RXD1_MARK ,AVB_RXD2_MARK , +AVB_RXD3_MARK ,AVB_RXD4_MARK ,AVB_RXD5_MARK , +AVB_RXD6_MARK ,AVB_RXD7_MARK , + +AVB_RX_ER_MARK ,AVB_RX_CLK_MARK ,AVB_RX_DV_MARK , +AVB_CRS_MARK ,AVB_GTX_CLK_MARK ,AVB_GTXREFCLK_MARK , +AVB_TX_EN_MARK ,AVB_TX_ER_MARK ,AVB_TX_CLK_MARK , +AVB_COL_MARK , +}; +static const unsigned int avb_avtp_match_pins[] = { +RCAR_GP_PIN (7 ,15 ), +}; +static const unsigned int avb_avtp_match_mux[] = { +AVB_AVTP_MATCH_MARK , +};/* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = {/* IRQ0 */
@@ -853,6 +934,13 @@ static const unsigned int scif3_clk_mux[ };static const struct sh_pfc_pin_group pinmux_groups[] = { +SH_PFC_PIN_GROUP (avb_link), +SH_PFC_PIN_GROUP (avb_magic), +SH_PFC_PIN_GROUP (avb_phy_int), +SH_PFC_PIN_GROUP (avb_mdio), +SH_PFC_PIN_GROUP (avb_mii), +SH_PFC_PIN_GROUP (avb_gmii), +SH_PFC_PIN_GROUP (avb_avtp_match),SH_PFC_PIN_GROUP (intc_irq0),SH_PFC_PIN_GROUP (intc_irq1),SH_PFC_PIN_GROUP (intc_irq2),
@@ -872,6 +960,16 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(scif3_clk), }; +static const char *const avb_groups[] = { +"avb_link" , +"avb_magic" , +"avb_phy_int" , +"avb_mdio" , +"avb_mii" , +"avb_gmii" , +"avb_avtp_match" , +}; +static const char *const intc_groups[] = {"intc_irq0" ,"intc_irq1" ,
@@ -902,6 +1000,7 @@ static const char * const scif3_groups[] };static const struct sh_pfc_function pinmux_functions[] = { +SH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc),SH_PFC_FUNCTION (scif0),
Re: [PATCH v2] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Quoted 3 lines · Sergei Shtylyov
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>
Quoted 6 lines
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 2 R8A7792 PFC patches posted before...Changes in version 2:
- addedAVB_AVTP_MATCHpin group.
Thanks for the update!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups
Hello.
Quoted 6 lines · Geert Uytterhoeven
Quoted 3 lines
Add the EtherAVB pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Quoted 8 lines
Quoted 6 lines
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 2 R8A7792 PFC patches posted before...Changes in version 2:
- addedAVB_AVTP_MATCHpin group.Thanks for the update!
Not at all. How about queuing the PFC patches? :-)
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add SDHI pin groups
In reply to Sergei ShtylyovAdd SDHI0 pin groups to the R8A7792 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 2 R8A7792 PFC patches posted before and the EtherAVB patch just reposted...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +51 -0
@@ -932,6 +932,43 @@ static const unsigned int scif3_clk_pinsstatic const unsigned int scif3_clk_mux[] = {SCK3_MARK , }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { +/* DAT0 */ +RCAR_GP_PIN (11 ,7 ), +}; +static const unsigned int sdhi0_data1_mux[] = { +SD0_DAT0_MARK , +}; +static const unsigned int sdhi0_data4_pins[] = { +/* DAT[0-3] */ +RCAR_GP_PIN (11 ,7 ),RCAR_GP_PIN (11 ,8 ), +RCAR_GP_PIN (11 ,9 ),RCAR_GP_PIN (11 ,10 ), +}; +static const unsigned int sdhi0_data4_mux[] = { +SD0_DAT0_MARK ,SD0_DAT1_MARK ,SD0_DAT2_MARK ,SD0_DAT3_MARK , +}; +static const unsigned int sdhi0_ctrl_pins[] = { +/* CLK, CMD */ +RCAR_GP_PIN (11 ,5 ),RCAR_GP_PIN (11 ,6 ), +}; +static const unsigned int sdhi0_ctrl_mux[] = { +SD0_CLK_MARK ,SD0_CMD_MARK , +}; +static const unsigned int sdhi0_cd_pins[] = { +/* CD */ +RCAR_GP_PIN (11 ,11 ), +}; +static const unsigned int sdhi0_cd_mux[] = { +SD0_CD_MARK , +}; +static const unsigned int sdhi0_wp_pins[] = { +/* WP */ +RCAR_GP_PIN (11 ,12 ), +}; +static const unsigned int sdhi0_wp_mux[] = { +SD0_WP_MARK , +};static const struct sh_pfc_pin_group pinmux_groups[] = {SH_PFC_PIN_GROUP (avb_link),
@@ -958,6 +995,11 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (scif0_ctrl),SH_PFC_PIN_GROUP (scif3_data ),SH_PFC_PIN_GROUP (scif3_clk ), +SH_PFC_PIN_GROUP (sdhi0_data1 ), +SH_PFC_PIN_GROUP (sdhi0_data4 ), +SH_PFC_PIN_GROUP (sdhi0_ctrl ), +SH_PFC_PIN_GROUP (sdhi0_cd ), + SH_PFC_PIN_GROUP(sdhi0_wp), };static const char *const avb_groups[] = {
@@ -999,12 +1041,21 @@ static const char * const scif3_groups[] "scif3_clk", }; +static const char *const sdhi0_groups[] = { +"sdhi0_data1" , +"sdhi0_data4" , +"sdhi0_ctrl" , +"sdhi0_cd" , +"sdhi0_wp" , +}; +static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc),SH_PFC_FUNCTION (scif0),SH_PFC_FUNCTION (scif3), +SH_PFC_FUNCTION (sdhi0), };static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add SDHI pin groups
Quoted 3 lines · Sergei Shtylyov
Add SDHI0 pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add SDHI pin groups
In reply to Sergei ShtylyovQuoted 3 lines · Sergei Shtylyov
Add SDHI0 pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>
I expect Geert to queue this and send it with the first pull request for the v4.9 development cycle.
Yours,
Linus Walleij
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add CAN pin groups
In reply to Sergei ShtylyovAdd CAN0/1 data/clock pin groups to R8A7792 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 4 R8A7792 PFC patches posted before...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +37 -0
@@ -809,6 +809,28 @@ static const unsigned int avb_avtp_matchstatic const unsigned int avb_avtp_match_mux[] = {AVB_AVTP_MATCH_MARK , }; +/* - CAN -------------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = { +/* TX, RX */ +RCAR_GP_PIN (10 ,27 ),RCAR_GP_PIN (10 ,28 ), +}; +static const unsigned int can0_data_mux[] = { +CAN0_TX_MARK ,CAN0_RX_MARK , +}; +static const unsigned int can1_data_pins[] = { +/* TX, RX */ +RCAR_GP_PIN (10 ,30 ),RCAR_GP_PIN (10 ,31 ), +}; +static const unsigned int can1_data_mux[] = { +CAN1_TX_MARK ,CAN1_RX_MARK , +}; +static const unsigned int can_clk_pins[] = { +/* CAN_CLK */ +RCAR_GP_PIN (10 ,29 ), +}; +static const unsigned int can_clk_mux[] = { +CAN_CLK_MARK , +};/* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = {/* IRQ0 */
@@ -978,6 +1000,9 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (avb_mii),SH_PFC_PIN_GROUP (avb_gmii),SH_PFC_PIN_GROUP (avb_avtp_match), +SH_PFC_PIN_GROUP (can0_data), +SH_PFC_PIN_GROUP (can1_data), +SH_PFC_PIN_GROUP (can_clk),SH_PFC_PIN_GROUP (intc_irq0),SH_PFC_PIN_GROUP (intc_irq1), SH_PFC_PIN_GROUP(intc_irq2),
@@ -1012,6 +1037,16 @@ static const char * const avb_groups[] = "avb_avtp_match", }; +static const char *const can0_groups[] = { +"can0_data" , +"can_clk" , +}; + +static const char *const can1_groups[] = { +"can1_data" , +"can_clk" , +}; +static const char *const intc_groups[] = {"intc_irq0" ,"intc_irq1" ,
@@ -1051,6 +1086,8 @@ static const char * const sdhi0_groups[]static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (avb), +SH_PFC_FUNCTION (can0), +SH_PFC_FUNCTION (can1),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc),SH_PFC_FUNCTION (scif0),
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add CAN pin groups
Hi Sergei,
Quoted 1 line · Sergei Shtylyov
Add CAN0/1 data/clock pin groups to R8A7792 PFC driver.
Thanks!
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>
Queued for v4.9, together with your other r8a7792 PFC patches.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add missing pinmux data
In reply to Sergei ShtylyovThe patch I've based my R8A7792 PFC work on had some VIN pinmux data missing and I just noticed that while adding the VIN pin groups...
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 5 R8A7792 PFC patches posted before...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +3 -0
@@ -622,6 +622,7 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP4_10_9 ,VI0_D18_R2 ),PINMUX_IPSR_MSEL (IP4_10_9 ,VI1_D14_G6_Y6 ,SEL_VI1_0 ),PINMUX_IPSR_GPSR (IP4_12_11 ,VI4_D4_C4 ), +PINMUX_IPSR_GPSR (IP4_12_11 ,VI0_D19_R3 ),PINMUX_IPSR_MSEL (IP4_12_11 ,VI1_D15_G7_Y7 ,SEL_VI1_0 ),PINMUX_IPSR_GPSR (IP4_14_13 ,VI4_D5_C5 ), PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
@@ -633,6 +634,8 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP4_18_17 ,VI0_D22_R6 ),PINMUX_IPSR_GPSR (IP4_18_17 ,VI2_D14_Y6 ),PINMUX_IPSR_GPSR (IP4_20_19 ,VI4_D8_Y0 ), +PINMUX_IPSR_GPSR (IP4_20_19 ,VI0_D23_R7 ), +PINMUX_IPSR_GPSR (IP4_20_19 ,VI2_D15_Y7 ),PINMUX_IPSR_GPSR (IP4_21 ,VI4_D9_Y1 ),PINMUX_IPSR_GPSR (IP4_21 ,VI3_D12_Y4 ), PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add missing pinmux data
Quoted 4 lines · Sergei Shtylyov
The patch I've based my R8A7792 PFC work on had some VIN pinmux data missing and I just noticed that while adding the VIN pin groups...
Signed-off-by Sergei Shtylyov <[email protected]>
This looks like a fix that should go in ASAP?
Geert, do you want me to apply this directly for fixes with your ACK?
Yours,
Linus Walleij
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add missing pinmux data
Quoted 6 lines · Linus Walleij
Quoted 4 lines
The patch I've based my R8A7792 PFC work on had some VIN pinmux data missing and I just noticed that while adding the VIN pin groups...
Signed-off-by Sergei Shtylyov <[email protected]>This looks like a fix that should go in ASAP?
It would be enough if it gets queued before the patch adding VIN pin groups.
[...]
Quoted 2 lines
Yours,
Linus Walleij
MBR, Sergei
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add missing pinmux data
Hi Sergei,
Quoted 7 lines · Sergei Shtylyov
Quoted 5 lines · Linus Walleij
Quoted 5 lines
The patch I've based my R8A7792 PFC work on had some VIN pinmux data missing
and I just noticed that while adding the VIN pin groups...Signed-off-by Sergei Shtylyov <[email protected]>
Thank you!
Quoted 4 lines
Quoted 1 line
This looks like a fix that should go in ASAP?
It would be enough if it gets queued before the patch adding VIN pin
groups.
As the original "pinctrl: sh-pfc: Add R8A7792 PFC support" isn't in the pinctrl tree yet, I'll fold your fix into that one.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add VIN pin groups
In reply to Sergei ShtylyovAdd VIN[0-5] pin groups to the R8A7794 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 5 R8A7792 PFC patches posted before (those should be collected by Geert) and the fix sent earlier today...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 577 +++++++++++++++++++++++++++++++++++ 1 file changed, 577 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +577 -0
@@ -994,6 +994,448 @@ static const unsigned int sdhi0_wp_pins[static const unsigned int sdhi0_wp_mux[] = {SD0_WP_MARK , }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { +/* B */ +RCAR_GP_PIN (4 ,4 ),RCAR_GP_PIN (4 ,5 ), +RCAR_GP_PIN (4 ,6 ),RCAR_GP_PIN (4 ,7 ), +RCAR_GP_PIN (4 ,8 ),RCAR_GP_PIN (4 ,9 ), +RCAR_GP_PIN (4 ,10 ),RCAR_GP_PIN (4 ,11 ), +/* G */ +RCAR_GP_PIN (4 ,12 ),RCAR_GP_PIN (4 ,13 ), +RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,15 ), +RCAR_GP_PIN (8 ,1 ),RCAR_GP_PIN (8 ,2 ), +RCAR_GP_PIN (8 ,3 ),RCAR_GP_PIN (8 ,4 ), +/* R */ +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,7 ),RCAR_GP_PIN (8 ,8 ), +RCAR_GP_PIN (8 ,9 ),RCAR_GP_PIN (8 ,10 ), +RCAR_GP_PIN (8 ,11 ),RCAR_GP_PIN (8 ,12 ), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { +/* B */ +VI0_D0_B0_C0_MARK ,VI0_D1_B1_C1_MARK , +VI0_D2_B2_C2_MARK ,VI0_D3_B3_C3_MARK , +VI0_D4_B4_C4_MARK ,VI0_D5_B5_C5_MARK , +VI0_D6_B6_C6_MARK ,VI0_D7_B7_C7_MARK , +/* G */ +VI0_D8_G0_Y0_MARK ,VI0_D9_G1_Y1_MARK , +VI0_D10_G2_Y2_MARK ,VI0_D11_G3_Y3_MARK , +VI0_D12_G4_Y4_MARK ,VI0_D13_G5_Y5_MARK , +VI0_D14_G6_Y6_MARK ,VI0_D15_G7_Y7_MARK , +/* R */ +VI0_D16_R0_MARK ,VI0_D17_R1_MARK , +VI0_D18_R2_MARK ,VI0_D19_R3_MARK , +VI0_D20_R4_MARK ,VI0_D21_R5_MARK , +VI0_D22_R6_MARK ,VI0_D23_R7_MARK , + }, +}; +static const unsigned int vin0_data18_pins[] = { +/* B */ +RCAR_GP_PIN (4 ,6 ),RCAR_GP_PIN (4 ,7 ), +RCAR_GP_PIN (4 ,8 ),RCAR_GP_PIN (4 ,9 ), +RCAR_GP_PIN (4 ,10 ),RCAR_GP_PIN (4 ,11 ), +/* G */ +RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,15 ), +RCAR_GP_PIN (8 ,1 ),RCAR_GP_PIN (8 ,2 ), +RCAR_GP_PIN (8 ,3 ),RCAR_GP_PIN (8 ,4 ), +/* R */ +RCAR_GP_PIN (8 ,7 ),RCAR_GP_PIN (8 ,8 ), +RCAR_GP_PIN (8 ,9 ),RCAR_GP_PIN (8 ,10 ), +RCAR_GP_PIN (8 ,11 ),RCAR_GP_PIN (8 ,12 ), +}; +static const unsigned int vin0_data18_mux[] = { +/* B */ +VI0_D2_B2_C2_MARK ,VI0_D3_B3_C3_MARK , +VI0_D4_B4_C4_MARK ,VI0_D5_B5_C5_MARK , +VI0_D6_B6_C6_MARK ,VI0_D7_B7_C7_MARK , +/* G */ +VI0_D10_G2_Y2_MARK ,VI0_D11_G3_Y3_MARK , +VI0_D12_G4_Y4_MARK ,VI0_D13_G5_Y5_MARK , +VI0_D14_G6_Y6_MARK ,VI0_D15_G7_Y7_MARK , +/* R */ +VI0_D18_R2_MARK ,VI0_D19_R3_MARK , +VI0_D20_R4_MARK ,VI0_D21_R5_MARK , +VI0_D22_R6_MARK ,VI0_D23_R7_MARK , +}; +static const unsigned int vin0_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (4 ,2 ),RCAR_GP_PIN (4 ,3 ), +}; +static const unsigned int vin0_sync_mux[] = { +VI0_HSYNC_N_MARK ,VI0_VSYNC_N_MARK , +}; +static const unsigned int vin0_field_pins[] = { +RCAR_GP_PIN (4 ,16 ), +}; +static const unsigned int vin0_field_mux[] = { +VI0_FIELD_MARK , +}; +static const unsigned int vin0_clkenb_pins[] = { +RCAR_GP_PIN (4 ,1 ), +}; +static const unsigned int vin0_clkenb_mux[] = { +VI0_CLKENB_MARK , +}; +static const unsigned int vin0_clk_pins[] = { +RCAR_GP_PIN (4 ,0 ), +}; +static const unsigned int vin0_clk_mux[] = { +VI0_CLK_MARK , +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data24 = { +/* B */ +RCAR_GP_PIN (5 ,4 ),RCAR_GP_PIN (5 ,5 ), +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,12 ),RCAR_GP_PIN (5 ,13 ), +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ), +/* R */ +RCAR_GP_PIN (9 ,5 ),RCAR_GP_PIN (9 ,6 ), +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), + }, +}; +static const union vin_data vin1_data_mux = { + .data24 = { +/* B */ +VI1_D0_B0_C0_MARK ,VI1_D1_B1_C1_MARK , +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D8_G0_Y0_MARK ,VI1_D9_G1_Y1_MARK , +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_MARK ,VI1_D13_G5_Y5_MARK , +VI1_D14_G6_Y6_MARK ,VI1_D15_G7_Y7_MARK , +/* R */ +VI1_D16_R0_MARK ,VI1_D17_R1_MARK , +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , + }, +}; +static const unsigned int vin1_data18_pins[] = { +/* B */ +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ), +/* R */ +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), +}; +static const unsigned int vin1_data18_mux[] = { +/* B */ +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_MARK ,VI1_D13_G5_Y5_MARK , +VI1_D14_G6_Y6_MARK ,VI1_D15_G7_Y7_MARK , +/* R */ +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , +}; +static const union vin_data vin1_data_b_pins = { + .data24 = { +/* B */ +RCAR_GP_PIN (5 ,4 ),RCAR_GP_PIN (5 ,5 ), +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,12 ),RCAR_GP_PIN (5 ,13 ), +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (9 ,1 ),RCAR_GP_PIN (9 ,2 ), +RCAR_GP_PIN (9 ,3 ),RCAR_GP_PIN (9 ,4 ), +/* R */ +RCAR_GP_PIN (9 ,5 ),RCAR_GP_PIN (9 ,6 ), +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), + }, +}; +static const union vin_data vin1_data_b_mux = { + .data24 = { +/* B */ +VI1_D0_B0_C0_MARK ,VI1_D1_B1_C1_MARK , +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D8_G0_Y0_MARK ,VI1_D9_G1_Y1_MARK , +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_B_MARK ,VI1_D13_G5_Y5_B_MARK , +VI1_D14_G6_Y6_B_MARK ,VI1_D15_G7_Y7_B_MARK , +/* R */ +VI1_D16_R0_MARK ,VI1_D17_R1_MARK , +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , + }, +}; +static const unsigned int vin1_data18_b_pins[] = { +/* B */ +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (9 ,1 ),RCAR_GP_PIN (9 ,2 ), +RCAR_GP_PIN (9 ,3 ),RCAR_GP_PIN (9 ,4 ), +/* R */ +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), +}; +static const unsigned int vin1_data18_b_mux[] = { +/* B */ +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_B_MARK ,VI1_D13_G5_Y5_B_MARK , +VI1_D14_G6_Y6_B_MARK ,VI1_D15_G7_Y7_B_MARK , +/* R */ +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , +}; +static const unsigned int vin1_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (5 ,2 ),RCAR_GP_PIN (5 ,3 ), +}; +static const unsigned int vin1_sync_mux[] = { +VI1_HSYNC_N_MARK ,VI1_VSYNC_N_MARK , +}; +static const unsigned int vin1_field_pins[] = { +RCAR_GP_PIN (5 ,16 ), +}; +static const unsigned int vin1_field_mux[] = { +VI1_FIELD_MARK , +}; +static const unsigned int vin1_clkenb_pins[] = { +RCAR_GP_PIN (5 ,1 ), +}; +static const unsigned int vin1_clkenb_mux[] = { +VI1_CLKENB_MARK , +}; +static const unsigned int vin1_clk_pins[] = { +RCAR_GP_PIN (5 ,0 ), +}; +static const unsigned int vin1_clk_mux[] = { +VI1_CLK_MARK , +}; +/* - VIN2 ------------------------------------------------------------------- */ +static const union vin_data vin2_data_pins = { + .data16 = { +RCAR_GP_PIN (6 ,4 ),RCAR_GP_PIN (6 ,5 ), +RCAR_GP_PIN (6 ,6 ),RCAR_GP_PIN (6 ,7 ), +RCAR_GP_PIN (6 ,8 ),RCAR_GP_PIN (6 ,9 ), +RCAR_GP_PIN (6 ,10 ),RCAR_GP_PIN (6 ,11 ), +RCAR_GP_PIN (6 ,12 ),RCAR_GP_PIN (6 ,13 ), +RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ), +RCAR_GP_PIN (8 ,9 ),RCAR_GP_PIN (8 ,10 ), +RCAR_GP_PIN (8 ,11 ),RCAR_GP_PIN (8 ,12 ), + }, +}; +static const union vin_data vin2_data_mux = { + .data16 = { +VI2_D0_C0_MARK ,VI2_D1_C1_MARK , +VI2_D2_C2_MARK ,VI2_D3_C3_MARK , +VI2_D4_C4_MARK ,VI2_D5_C5_MARK , +VI2_D6_C6_MARK ,VI2_D7_C7_MARK , +VI2_D8_Y0_MARK ,VI2_D9_Y1_MARK , +VI2_D10_Y2_MARK ,VI2_D11_Y3_MARK , +VI2_D12_Y4_MARK ,VI2_D13_Y5_MARK , +VI2_D14_Y6_MARK ,VI2_D15_Y7_MARK , + }, +}; +static const unsigned int vin2_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (6 ,2 ),RCAR_GP_PIN (6 ,3 ), +}; +static const unsigned int vin2_sync_mux[] = { +VI2_HSYNC_N_MARK ,VI2_VSYNC_N_MARK , +}; +static const unsigned int vin2_field_pins[] = { +RCAR_GP_PIN (6 ,16 ), +}; +static const unsigned int vin2_field_mux[] = { +VI2_FIELD_MARK , +}; +static const unsigned int vin2_clkenb_pins[] = { +RCAR_GP_PIN (6 ,1 ), +}; +static const unsigned int vin2_clkenb_mux[] = { +VI2_CLKENB_MARK , +}; +static const unsigned int vin2_clk_pins[] = { +RCAR_GP_PIN (6 ,0 ), +}; +static const unsigned int vin2_clk_mux[] = { +VI2_CLK_MARK , +}; +/* - VIN3 ------------------------------------------------------------------- */ +static const union vin_data vin3_data_pins = { + .data16 = { +RCAR_GP_PIN (7 ,4 ),RCAR_GP_PIN (7 ,5 ), +RCAR_GP_PIN (7 ,6 ),RCAR_GP_PIN (7 ,7 ), +RCAR_GP_PIN (7 ,8 ),RCAR_GP_PIN (7 ,9 ), +RCAR_GP_PIN (7 ,10 ),RCAR_GP_PIN (7 ,11 ), +RCAR_GP_PIN (7 ,12 ),RCAR_GP_PIN (7 ,13 ), +RCAR_GP_PIN (7 ,14 ),RCAR_GP_PIN (7 ,15 ), +RCAR_GP_PIN (8 ,13 ),RCAR_GP_PIN (8 ,14 ), +RCAR_GP_PIN (8 ,15 ),RCAR_GP_PIN (8 ,16 ), + }, +}; +static const union vin_data vin3_data_mux = { + .data16 = { +VI3_D0_C0_MARK ,VI3_D1_C1_MARK , +VI3_D2_C2_MARK ,VI3_D3_C3_MARK , +VI3_D4_C4_MARK ,VI3_D5_C5_MARK , +VI3_D6_C6_MARK ,VI3_D7_C7_MARK , +VI3_D8_Y0_MARK ,VI3_D9_Y1_MARK , +VI3_D10_Y2_MARK ,VI3_D11_Y3_MARK , +VI3_D12_Y4_MARK ,VI3_D13_Y5_MARK , +VI3_D14_Y6_MARK ,VI3_D15_Y7_MARK , + }, +}; +static const unsigned int vin3_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (7 ,2 ),RCAR_GP_PIN (7 ,3 ), +}; +static const unsigned int vin3_sync_mux[] = { +VI3_HSYNC_N_MARK ,VI3_VSYNC_N_MARK , +}; +static const unsigned int vin3_field_pins[] = { +RCAR_GP_PIN (7 ,16 ), +}; +static const unsigned int vin3_field_mux[] = { +VI3_FIELD_MARK , +}; +static const unsigned int vin3_clkenb_pins[] = { +RCAR_GP_PIN (7 ,1 ), +}; +static const unsigned int vin3_clkenb_mux[] = { +VI3_CLKENB_MARK , +}; +static const unsigned int vin3_clk_pins[] = { +RCAR_GP_PIN (7 ,0 ), +}; +static const unsigned int vin3_clk_mux[] = { +VI3_CLK_MARK , +}; +/* - VIN4 ------------------------------------------------------------------- */ +static const union vin_data vin4_data_pins = { + .data12 = { +RCAR_GP_PIN (8 ,4 ),RCAR_GP_PIN (8 ,5 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ), +RCAR_GP_PIN (8 ,8 ),RCAR_GP_PIN (8 ,9 ), +RCAR_GP_PIN (8 ,10 ),RCAR_GP_PIN (8 ,11 ), +RCAR_GP_PIN (8 ,12 ),RCAR_GP_PIN (8 ,13 ), +RCAR_GP_PIN (8 ,14 ),RCAR_GP_PIN (8 ,15 ), + }, +}; +static const union vin_data vin4_data_mux = { + .data12 = { +VI4_D0_C0_MARK ,VI4_D1_C1_MARK , +VI4_D2_C2_MARK ,VI4_D3_C3_MARK , +VI4_D4_C4_MARK ,VI4_D5_C5_MARK , +VI4_D6_C6_MARK ,VI4_D7_C7_MARK , +VI4_D8_Y0_MARK ,VI4_D9_Y1_MARK , +VI4_D10_Y2_MARK ,VI4_D11_Y3_MARK , + }, +}; +static const unsigned int vin4_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (8 ,2 ),RCAR_GP_PIN (8 ,3 ), +}; +static const unsigned int vin4_sync_mux[] = { +VI4_HSYNC_N_MARK ,VI4_VSYNC_N_MARK , +}; +static const unsigned int vin4_field_pins[] = { +RCAR_GP_PIN (8 ,16 ), +}; +static const unsigned int vin4_field_mux[] = { +VI4_FIELD_MARK , +}; +static const unsigned int vin4_clkenb_pins[] = { +RCAR_GP_PIN (8 ,1 ), +}; +static const unsigned int vin4_clkenb_mux[] = { +VI4_CLKENB_MARK , +}; +static const unsigned int vin4_clk_pins[] = { +RCAR_GP_PIN (8 ,0 ), +}; +static const unsigned int vin4_clk_mux[] = { +VI4_CLK_MARK , +}; +/* - VIN5 ------------------------------------------------------------------- */ +static const union vin_data vin5_data_pins = { + .data12 = { +RCAR_GP_PIN (9 ,4 ),RCAR_GP_PIN (9 ,5 ), +RCAR_GP_PIN (9 ,6 ),RCAR_GP_PIN (9 ,7 ), +RCAR_GP_PIN (9 ,8 ),RCAR_GP_PIN (9 ,9 ), +RCAR_GP_PIN (9 ,10 ),RCAR_GP_PIN (9 ,11 ), +RCAR_GP_PIN (9 ,12 ),RCAR_GP_PIN (9 ,13 ), +RCAR_GP_PIN (9 ,14 ),RCAR_GP_PIN (9 ,15 ), + }, +}; +static const union vin_data vin5_data_mux = { + .data12 = { +VI5_D0_C0_MARK ,VI5_D1_C1_MARK , +VI5_D2_C2_MARK ,VI5_D3_C3_MARK , +VI5_D4_C4_MARK ,VI5_D5_C5_MARK , +VI5_D6_C6_MARK ,VI5_D7_C7_MARK , +VI5_D8_Y0_MARK ,VI5_D9_Y1_MARK , +VI5_D10_Y2_MARK ,VI5_D11_Y3_MARK , + }, +}; +static const unsigned int vin5_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (9 ,2 ),RCAR_GP_PIN (9 ,3 ), +}; +static const unsigned int vin5_sync_mux[] = { +VI5_HSYNC_N_MARK ,VI5_VSYNC_N_MARK , +}; +static const unsigned int vin5_field_pins[] = { +RCAR_GP_PIN (9 ,16 ), +}; +static const unsigned int vin5_field_mux[] = { +VI5_FIELD_MARK , +}; +static const unsigned int vin5_clkenb_pins[] = { +RCAR_GP_PIN (9 ,1 ), +}; +static const unsigned int vin5_clkenb_mux[] = { +VI5_CLKENB_MARK , +}; +static const unsigned int vin5_clk_pins[] = { +RCAR_GP_PIN (9 ,0 ), +}; +static const unsigned int vin5_clk_mux[] = { +VI5_CLK_MARK , +};static const struct sh_pfc_pin_group pinmux_groups[] = {SH_PFC_PIN_GROUP (avb_link),
@@ -1028,6 +1470,62 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (sdhi0_ctrl),SH_PFC_PIN_GROUP (sdhi0_cd),SH_PFC_PIN_GROUP (sdhi0_wp), +VIN_DATA_PIN_GROUP (vin0_data,24 ), +VIN_DATA_PIN_GROUP (vin0_data,20 ), +SH_PFC_PIN_GROUP (vin0_data18), +VIN_DATA_PIN_GROUP (vin0_data,16 ), +VIN_DATA_PIN_GROUP (vin0_data,12 ), +VIN_DATA_PIN_GROUP (vin0_data,10 ), +VIN_DATA_PIN_GROUP (vin0_data,8 ), +SH_PFC_PIN_GROUP (vin0_sync), +SH_PFC_PIN_GROUP (vin0_field), +SH_PFC_PIN_GROUP (vin0_clkenb), +SH_PFC_PIN_GROUP (vin0_clk), +VIN_DATA_PIN_GROUP (vin1_data,24 ), +VIN_DATA_PIN_GROUP (vin1_data,20 ), +SH_PFC_PIN_GROUP (vin1_data18), +VIN_DATA_PIN_GROUP (vin1_data,16 ), +VIN_DATA_PIN_GROUP (vin1_data,12 ), +VIN_DATA_PIN_GROUP (vin1_data,10 ), +VIN_DATA_PIN_GROUP (vin1_data,8 ), +VIN_DATA_PIN_GROUP (vin1_data_b,24 ), +VIN_DATA_PIN_GROUP (vin1_data_b,20 ), +SH_PFC_PIN_GROUP (vin1_data18_b), +VIN_DATA_PIN_GROUP (vin1_data_b,16 ), +SH_PFC_PIN_GROUP (vin1_sync), +SH_PFC_PIN_GROUP (vin1_field), +SH_PFC_PIN_GROUP (vin1_clkenb), +SH_PFC_PIN_GROUP (vin1_clk), +VIN_DATA_PIN_GROUP (vin2_data,16 ), +VIN_DATA_PIN_GROUP (vin2_data,12 ), +VIN_DATA_PIN_GROUP (vin2_data,10 ), +VIN_DATA_PIN_GROUP (vin2_data,8 ), +SH_PFC_PIN_GROUP (vin2_sync), +SH_PFC_PIN_GROUP (vin2_field), +SH_PFC_PIN_GROUP (vin2_clkenb), +SH_PFC_PIN_GROUP (vin2_clk), +VIN_DATA_PIN_GROUP (vin3_data,16 ), +VIN_DATA_PIN_GROUP (vin3_data,12 ), +VIN_DATA_PIN_GROUP (vin3_data,10 ), +VIN_DATA_PIN_GROUP (vin3_data,8 ), +SH_PFC_PIN_GROUP (vin3_sync), +SH_PFC_PIN_GROUP (vin3_field), +SH_PFC_PIN_GROUP (vin3_clkenb), +SH_PFC_PIN_GROUP (vin3_clk), +VIN_DATA_PIN_GROUP (vin4_data,12 ), +VIN_DATA_PIN_GROUP (vin4_data,10 ), +VIN_DATA_PIN_GROUP (vin4_data,8 ), +SH_PFC_PIN_GROUP (vin4_sync), +SH_PFC_PIN_GROUP (vin4_field), +SH_PFC_PIN_GROUP (vin4_clkenb), +SH_PFC_PIN_GROUP (vin4_clk), +VIN_DATA_PIN_GROUP (vin5_data,12 ), +VIN_DATA_PIN_GROUP (vin5_data,10 ), +VIN_DATA_PIN_GROUP (vin5_data,8 ), +SH_PFC_PIN_GROUP (vin5_sync), +SH_PFC_PIN_GROUP (vin5_field), +SH_PFC_PIN_GROUP (vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), }; static const char * const avb_groups[] = {
@@ -1087,6 +1585,79 @@ static const char * const sdhi0_groups[] "sdhi0_wp", }; +static const char *const vin0_groups[] = { +"vin0_data24" , +"vin0_data20" , +"vin0_data18" , +"vin0_data16" , +"vin0_data12" , +"vin0_data10" , +"vin0_data8" , +"vin0_sync" , +"vin0_field" , +"vin0_clkenb" , +"vin0_clk" , +}; + +static const char *const vin1_groups[] = { +"vin1_data24" , +"vin1_data20" , +"vin1_data18" , +"vin1_data16" , +"vin1_data12" , +"vin1_data10" , +"vin1_data8" , +"vin1_data24_b" , +"vin1_data20_b" , +"vin1_data16_b" , +"vin1_sync" , +"vin1_field" , +"vin1_clkenb" , +"vin1_clk" , +}; + +static const char *const vin2_groups[] = { +"vin2_data16" , +"vin2_data12" , +"vin2_data10" , +"vin2_data8" , +"vin2_sync" , +"vin2_field" , +"vin2_clkenb" , +"vin2_clk" , +}; + +static const char *const vin3_groups[] = { +"vin3_data16" , +"vin3_data12" , +"vin3_data10" , +"vin3_data8" , +"vin3_sync" , +"vin3_field" , +"vin3_clkenb" , +"vin3_clk" , +}; + +static const char *const vin4_groups[] = { +"vin4_data12" , +"vin4_data10" , +"vin4_data8" , +"vin4_sync" , +"vin4_field" , +"vin4_clkenb" , +"vin4_clk" , +}; + +static const char *const vin5_groups[] = { +"vin5_data12" , +"vin5_data10" , +"vin5_data8" , +"vin5_sync" , +"vin5_field" , +"vin5_clkenb" , +"vin5_clk" , +}; +static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (can0),
@@ -1096,6 +1667,12 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (scif0),SH_PFC_FUNCTION (scif3 ),SH_PFC_FUNCTION (sdhi0 ), +SH_PFC_FUNCTION (vin0 ), +SH_PFC_FUNCTION (vin1 ), +SH_PFC_FUNCTION (vin2 ), +SH_PFC_FUNCTION (vin3 ), +SH_PFC_FUNCTION (vin4 ), + SH_PFC_FUNCTION(vin5), };static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add VIN pin groups
Hello.
Quoted 1 line · Sergei Shtylyov
Add VIN[0-5] pin groups to the R8A7794 PFC driver.
Oops, R8A7792, of course. Geert, have you merged this one or not yet?
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>
[...]
MBR, Sergei
PATCH v2 1/1 pinctrl: sh-pfc: r8a7792: add VIN pin groups
In reply to Sergei ShtylyovAdd VIN[0-5] pin groups to the R8A7792 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 6 R8A7792 PFC patches posted before (those should be collected by Geert)...
Changes in version 2:
- fixed the SoC model in the changelog.
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 577 +++++++++++++++++++++++++++++++++++ 1 file changed, 577 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +577 -0
@@ -994,6 +994,448 @@ static const unsigned int sdhi0_wp_pins[static const unsigned int sdhi0_wp_mux[] = {SD0_WP_MARK , }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { +/* B */ +RCAR_GP_PIN (4 ,4 ),RCAR_GP_PIN (4 ,5 ), +RCAR_GP_PIN (4 ,6 ),RCAR_GP_PIN (4 ,7 ), +RCAR_GP_PIN (4 ,8 ),RCAR_GP_PIN (4 ,9 ), +RCAR_GP_PIN (4 ,10 ),RCAR_GP_PIN (4 ,11 ), +/* G */ +RCAR_GP_PIN (4 ,12 ),RCAR_GP_PIN (4 ,13 ), +RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,15 ), +RCAR_GP_PIN (8 ,1 ),RCAR_GP_PIN (8 ,2 ), +RCAR_GP_PIN (8 ,3 ),RCAR_GP_PIN (8 ,4 ), +/* R */ +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,7 ),RCAR_GP_PIN (8 ,8 ), +RCAR_GP_PIN (8 ,9 ),RCAR_GP_PIN (8 ,10 ), +RCAR_GP_PIN (8 ,11 ),RCAR_GP_PIN (8 ,12 ), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { +/* B */ +VI0_D0_B0_C0_MARK ,VI0_D1_B1_C1_MARK , +VI0_D2_B2_C2_MARK ,VI0_D3_B3_C3_MARK , +VI0_D4_B4_C4_MARK ,VI0_D5_B5_C5_MARK , +VI0_D6_B6_C6_MARK ,VI0_D7_B7_C7_MARK , +/* G */ +VI0_D8_G0_Y0_MARK ,VI0_D9_G1_Y1_MARK , +VI0_D10_G2_Y2_MARK ,VI0_D11_G3_Y3_MARK , +VI0_D12_G4_Y4_MARK ,VI0_D13_G5_Y5_MARK , +VI0_D14_G6_Y6_MARK ,VI0_D15_G7_Y7_MARK , +/* R */ +VI0_D16_R0_MARK ,VI0_D17_R1_MARK , +VI0_D18_R2_MARK ,VI0_D19_R3_MARK , +VI0_D20_R4_MARK ,VI0_D21_R5_MARK , +VI0_D22_R6_MARK ,VI0_D23_R7_MARK , + }, +}; +static const unsigned int vin0_data18_pins[] = { +/* B */ +RCAR_GP_PIN (4 ,6 ),RCAR_GP_PIN (4 ,7 ), +RCAR_GP_PIN (4 ,8 ),RCAR_GP_PIN (4 ,9 ), +RCAR_GP_PIN (4 ,10 ),RCAR_GP_PIN (4 ,11 ), +/* G */ +RCAR_GP_PIN (4 ,14 ),RCAR_GP_PIN (4 ,15 ), +RCAR_GP_PIN (8 ,1 ),RCAR_GP_PIN (8 ,2 ), +RCAR_GP_PIN (8 ,3 ),RCAR_GP_PIN (8 ,4 ), +/* R */ +RCAR_GP_PIN (8 ,7 ),RCAR_GP_PIN (8 ,8 ), +RCAR_GP_PIN (8 ,9 ),RCAR_GP_PIN (8 ,10 ), +RCAR_GP_PIN (8 ,11 ),RCAR_GP_PIN (8 ,12 ), +}; +static const unsigned int vin0_data18_mux[] = { +/* B */ +VI0_D2_B2_C2_MARK ,VI0_D3_B3_C3_MARK , +VI0_D4_B4_C4_MARK ,VI0_D5_B5_C5_MARK , +VI0_D6_B6_C6_MARK ,VI0_D7_B7_C7_MARK , +/* G */ +VI0_D10_G2_Y2_MARK ,VI0_D11_G3_Y3_MARK , +VI0_D12_G4_Y4_MARK ,VI0_D13_G5_Y5_MARK , +VI0_D14_G6_Y6_MARK ,VI0_D15_G7_Y7_MARK , +/* R */ +VI0_D18_R2_MARK ,VI0_D19_R3_MARK , +VI0_D20_R4_MARK ,VI0_D21_R5_MARK , +VI0_D22_R6_MARK ,VI0_D23_R7_MARK , +}; +static const unsigned int vin0_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (4 ,2 ),RCAR_GP_PIN (4 ,3 ), +}; +static const unsigned int vin0_sync_mux[] = { +VI0_HSYNC_N_MARK ,VI0_VSYNC_N_MARK , +}; +static const unsigned int vin0_field_pins[] = { +RCAR_GP_PIN (4 ,16 ), +}; +static const unsigned int vin0_field_mux[] = { +VI0_FIELD_MARK , +}; +static const unsigned int vin0_clkenb_pins[] = { +RCAR_GP_PIN (4 ,1 ), +}; +static const unsigned int vin0_clkenb_mux[] = { +VI0_CLKENB_MARK , +}; +static const unsigned int vin0_clk_pins[] = { +RCAR_GP_PIN (4 ,0 ), +}; +static const unsigned int vin0_clk_mux[] = { +VI0_CLK_MARK , +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data24 = { +/* B */ +RCAR_GP_PIN (5 ,4 ),RCAR_GP_PIN (5 ,5 ), +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,12 ),RCAR_GP_PIN (5 ,13 ), +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ), +/* R */ +RCAR_GP_PIN (9 ,5 ),RCAR_GP_PIN (9 ,6 ), +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), + }, +}; +static const union vin_data vin1_data_mux = { + .data24 = { +/* B */ +VI1_D0_B0_C0_MARK ,VI1_D1_B1_C1_MARK , +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D8_G0_Y0_MARK ,VI1_D9_G1_Y1_MARK , +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_MARK ,VI1_D13_G5_Y5_MARK , +VI1_D14_G6_Y6_MARK ,VI1_D15_G7_Y7_MARK , +/* R */ +VI1_D16_R0_MARK ,VI1_D17_R1_MARK , +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , + }, +}; +static const unsigned int vin1_data18_pins[] = { +/* B */ +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ), +/* R */ +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), +}; +static const unsigned int vin1_data18_mux[] = { +/* B */ +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_MARK ,VI1_D13_G5_Y5_MARK , +VI1_D14_G6_Y6_MARK ,VI1_D15_G7_Y7_MARK , +/* R */ +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , +}; +static const union vin_data vin1_data_b_pins = { + .data24 = { +/* B */ +RCAR_GP_PIN (5 ,4 ),RCAR_GP_PIN (5 ,5 ), +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,12 ),RCAR_GP_PIN (5 ,13 ), +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (9 ,1 ),RCAR_GP_PIN (9 ,2 ), +RCAR_GP_PIN (9 ,3 ),RCAR_GP_PIN (9 ,4 ), +/* R */ +RCAR_GP_PIN (9 ,5 ),RCAR_GP_PIN (9 ,6 ), +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), + }, +}; +static const union vin_data vin1_data_b_mux = { + .data24 = { +/* B */ +VI1_D0_B0_C0_MARK ,VI1_D1_B1_C1_MARK , +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D8_G0_Y0_MARK ,VI1_D9_G1_Y1_MARK , +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_B_MARK ,VI1_D13_G5_Y5_B_MARK , +VI1_D14_G6_Y6_B_MARK ,VI1_D15_G7_Y7_B_MARK , +/* R */ +VI1_D16_R0_MARK ,VI1_D17_R1_MARK , +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , + }, +}; +static const unsigned int vin1_data18_b_pins[] = { +/* B */ +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (9 ,1 ),RCAR_GP_PIN (9 ,2 ), +RCAR_GP_PIN (9 ,3 ),RCAR_GP_PIN (9 ,4 ), +/* R */ +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), +RCAR_GP_PIN (9 ,11 ),RCAR_GP_PIN (9 ,12 ), +}; +static const unsigned int vin1_data18_b_mux[] = { +/* B */ +VI1_D2_B2_C2_MARK ,VI1_D3_B3_C3_MARK , +VI1_D4_B4_C4_MARK ,VI1_D5_B5_C5_MARK , +VI1_D6_B6_C6_MARK ,VI1_D7_B7_C7_MARK , +/* G */ +VI1_D10_G2_Y2_MARK ,VI1_D11_G3_Y3_MARK , +VI1_D12_G4_Y4_B_MARK ,VI1_D13_G5_Y5_B_MARK , +VI1_D14_G6_Y6_B_MARK ,VI1_D15_G7_Y7_B_MARK , +/* R */ +VI1_D18_R2_MARK ,VI1_D19_R3_MARK , +VI1_D20_R4_MARK ,VI1_D21_R5_MARK , +VI1_D22_R6_MARK ,VI1_D23_R7_MARK , +}; +static const unsigned int vin1_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (5 ,2 ),RCAR_GP_PIN (5 ,3 ), +}; +static const unsigned int vin1_sync_mux[] = { +VI1_HSYNC_N_MARK ,VI1_VSYNC_N_MARK , +}; +static const unsigned int vin1_field_pins[] = { +RCAR_GP_PIN (5 ,16 ), +}; +static const unsigned int vin1_field_mux[] = { +VI1_FIELD_MARK , +}; +static const unsigned int vin1_clkenb_pins[] = { +RCAR_GP_PIN (5 ,1 ), +}; +static const unsigned int vin1_clkenb_mux[] = { +VI1_CLKENB_MARK , +}; +static const unsigned int vin1_clk_pins[] = { +RCAR_GP_PIN (5 ,0 ), +}; +static const unsigned int vin1_clk_mux[] = { +VI1_CLK_MARK , +}; +/* - VIN2 ------------------------------------------------------------------- */ +static const union vin_data vin2_data_pins = { + .data16 = { +RCAR_GP_PIN (6 ,4 ),RCAR_GP_PIN (6 ,5 ), +RCAR_GP_PIN (6 ,6 ),RCAR_GP_PIN (6 ,7 ), +RCAR_GP_PIN (6 ,8 ),RCAR_GP_PIN (6 ,9 ), +RCAR_GP_PIN (6 ,10 ),RCAR_GP_PIN (6 ,11 ), +RCAR_GP_PIN (6 ,12 ),RCAR_GP_PIN (6 ,13 ), +RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ), +RCAR_GP_PIN (8 ,9 ),RCAR_GP_PIN (8 ,10 ), +RCAR_GP_PIN (8 ,11 ),RCAR_GP_PIN (8 ,12 ), + }, +}; +static const union vin_data vin2_data_mux = { + .data16 = { +VI2_D0_C0_MARK ,VI2_D1_C1_MARK , +VI2_D2_C2_MARK ,VI2_D3_C3_MARK , +VI2_D4_C4_MARK ,VI2_D5_C5_MARK , +VI2_D6_C6_MARK ,VI2_D7_C7_MARK , +VI2_D8_Y0_MARK ,VI2_D9_Y1_MARK , +VI2_D10_Y2_MARK ,VI2_D11_Y3_MARK , +VI2_D12_Y4_MARK ,VI2_D13_Y5_MARK , +VI2_D14_Y6_MARK ,VI2_D15_Y7_MARK , + }, +}; +static const unsigned int vin2_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (6 ,2 ),RCAR_GP_PIN (6 ,3 ), +}; +static const unsigned int vin2_sync_mux[] = { +VI2_HSYNC_N_MARK ,VI2_VSYNC_N_MARK , +}; +static const unsigned int vin2_field_pins[] = { +RCAR_GP_PIN (6 ,16 ), +}; +static const unsigned int vin2_field_mux[] = { +VI2_FIELD_MARK , +}; +static const unsigned int vin2_clkenb_pins[] = { +RCAR_GP_PIN (6 ,1 ), +}; +static const unsigned int vin2_clkenb_mux[] = { +VI2_CLKENB_MARK , +}; +static const unsigned int vin2_clk_pins[] = { +RCAR_GP_PIN (6 ,0 ), +}; +static const unsigned int vin2_clk_mux[] = { +VI2_CLK_MARK , +}; +/* - VIN3 ------------------------------------------------------------------- */ +static const union vin_data vin3_data_pins = { + .data16 = { +RCAR_GP_PIN (7 ,4 ),RCAR_GP_PIN (7 ,5 ), +RCAR_GP_PIN (7 ,6 ),RCAR_GP_PIN (7 ,7 ), +RCAR_GP_PIN (7 ,8 ),RCAR_GP_PIN (7 ,9 ), +RCAR_GP_PIN (7 ,10 ),RCAR_GP_PIN (7 ,11 ), +RCAR_GP_PIN (7 ,12 ),RCAR_GP_PIN (7 ,13 ), +RCAR_GP_PIN (7 ,14 ),RCAR_GP_PIN (7 ,15 ), +RCAR_GP_PIN (8 ,13 ),RCAR_GP_PIN (8 ,14 ), +RCAR_GP_PIN (8 ,15 ),RCAR_GP_PIN (8 ,16 ), + }, +}; +static const union vin_data vin3_data_mux = { + .data16 = { +VI3_D0_C0_MARK ,VI3_D1_C1_MARK , +VI3_D2_C2_MARK ,VI3_D3_C3_MARK , +VI3_D4_C4_MARK ,VI3_D5_C5_MARK , +VI3_D6_C6_MARK ,VI3_D7_C7_MARK , +VI3_D8_Y0_MARK ,VI3_D9_Y1_MARK , +VI3_D10_Y2_MARK ,VI3_D11_Y3_MARK , +VI3_D12_Y4_MARK ,VI3_D13_Y5_MARK , +VI3_D14_Y6_MARK ,VI3_D15_Y7_MARK , + }, +}; +static const unsigned int vin3_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (7 ,2 ),RCAR_GP_PIN (7 ,3 ), +}; +static const unsigned int vin3_sync_mux[] = { +VI3_HSYNC_N_MARK ,VI3_VSYNC_N_MARK , +}; +static const unsigned int vin3_field_pins[] = { +RCAR_GP_PIN (7 ,16 ), +}; +static const unsigned int vin3_field_mux[] = { +VI3_FIELD_MARK , +}; +static const unsigned int vin3_clkenb_pins[] = { +RCAR_GP_PIN (7 ,1 ), +}; +static const unsigned int vin3_clkenb_mux[] = { +VI3_CLKENB_MARK , +}; +static const unsigned int vin3_clk_pins[] = { +RCAR_GP_PIN (7 ,0 ), +}; +static const unsigned int vin3_clk_mux[] = { +VI3_CLK_MARK , +}; +/* - VIN4 ------------------------------------------------------------------- */ +static const union vin_data vin4_data_pins = { + .data12 = { +RCAR_GP_PIN (8 ,4 ),RCAR_GP_PIN (8 ,5 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ), +RCAR_GP_PIN (8 ,8 ),RCAR_GP_PIN (8 ,9 ), +RCAR_GP_PIN (8 ,10 ),RCAR_GP_PIN (8 ,11 ), +RCAR_GP_PIN (8 ,12 ),RCAR_GP_PIN (8 ,13 ), +RCAR_GP_PIN (8 ,14 ),RCAR_GP_PIN (8 ,15 ), + }, +}; +static const union vin_data vin4_data_mux = { + .data12 = { +VI4_D0_C0_MARK ,VI4_D1_C1_MARK , +VI4_D2_C2_MARK ,VI4_D3_C3_MARK , +VI4_D4_C4_MARK ,VI4_D5_C5_MARK , +VI4_D6_C6_MARK ,VI4_D7_C7_MARK , +VI4_D8_Y0_MARK ,VI4_D9_Y1_MARK , +VI4_D10_Y2_MARK ,VI4_D11_Y3_MARK , + }, +}; +static const unsigned int vin4_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (8 ,2 ),RCAR_GP_PIN (8 ,3 ), +}; +static const unsigned int vin4_sync_mux[] = { +VI4_HSYNC_N_MARK ,VI4_VSYNC_N_MARK , +}; +static const unsigned int vin4_field_pins[] = { +RCAR_GP_PIN (8 ,16 ), +}; +static const unsigned int vin4_field_mux[] = { +VI4_FIELD_MARK , +}; +static const unsigned int vin4_clkenb_pins[] = { +RCAR_GP_PIN (8 ,1 ), +}; +static const unsigned int vin4_clkenb_mux[] = { +VI4_CLKENB_MARK , +}; +static const unsigned int vin4_clk_pins[] = { +RCAR_GP_PIN (8 ,0 ), +}; +static const unsigned int vin4_clk_mux[] = { +VI4_CLK_MARK , +}; +/* - VIN5 ------------------------------------------------------------------- */ +static const union vin_data vin5_data_pins = { + .data12 = { +RCAR_GP_PIN (9 ,4 ),RCAR_GP_PIN (9 ,5 ), +RCAR_GP_PIN (9 ,6 ),RCAR_GP_PIN (9 ,7 ), +RCAR_GP_PIN (9 ,8 ),RCAR_GP_PIN (9 ,9 ), +RCAR_GP_PIN (9 ,10 ),RCAR_GP_PIN (9 ,11 ), +RCAR_GP_PIN (9 ,12 ),RCAR_GP_PIN (9 ,13 ), +RCAR_GP_PIN (9 ,14 ),RCAR_GP_PIN (9 ,15 ), + }, +}; +static const union vin_data vin5_data_mux = { + .data12 = { +VI5_D0_C0_MARK ,VI5_D1_C1_MARK , +VI5_D2_C2_MARK ,VI5_D3_C3_MARK , +VI5_D4_C4_MARK ,VI5_D5_C5_MARK , +VI5_D6_C6_MARK ,VI5_D7_C7_MARK , +VI5_D8_Y0_MARK ,VI5_D9_Y1_MARK , +VI5_D10_Y2_MARK ,VI5_D11_Y3_MARK , + }, +}; +static const unsigned int vin5_sync_pins[] = { +/* HSYNC#, VSYNC# */ +RCAR_GP_PIN (9 ,2 ),RCAR_GP_PIN (9 ,3 ), +}; +static const unsigned int vin5_sync_mux[] = { +VI5_HSYNC_N_MARK ,VI5_VSYNC_N_MARK , +}; +static const unsigned int vin5_field_pins[] = { +RCAR_GP_PIN (9 ,16 ), +}; +static const unsigned int vin5_field_mux[] = { +VI5_FIELD_MARK , +}; +static const unsigned int vin5_clkenb_pins[] = { +RCAR_GP_PIN (9 ,1 ), +}; +static const unsigned int vin5_clkenb_mux[] = { +VI5_CLKENB_MARK , +}; +static const unsigned int vin5_clk_pins[] = { +RCAR_GP_PIN (9 ,0 ), +}; +static const unsigned int vin5_clk_mux[] = { +VI5_CLK_MARK , +};static const struct sh_pfc_pin_group pinmux_groups[] = {SH_PFC_PIN_GROUP (avb_link),
@@ -1028,6 +1470,62 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (sdhi0_ctrl),SH_PFC_PIN_GROUP (sdhi0_cd),SH_PFC_PIN_GROUP (sdhi0_wp), +VIN_DATA_PIN_GROUP (vin0_data,24 ), +VIN_DATA_PIN_GROUP (vin0_data,20 ), +SH_PFC_PIN_GROUP (vin0_data18), +VIN_DATA_PIN_GROUP (vin0_data,16 ), +VIN_DATA_PIN_GROUP (vin0_data,12 ), +VIN_DATA_PIN_GROUP (vin0_data,10 ), +VIN_DATA_PIN_GROUP (vin0_data,8 ), +SH_PFC_PIN_GROUP (vin0_sync), +SH_PFC_PIN_GROUP (vin0_field), +SH_PFC_PIN_GROUP (vin0_clkenb), +SH_PFC_PIN_GROUP (vin0_clk), +VIN_DATA_PIN_GROUP (vin1_data,24 ), +VIN_DATA_PIN_GROUP (vin1_data,20 ), +SH_PFC_PIN_GROUP (vin1_data18), +VIN_DATA_PIN_GROUP (vin1_data,16 ), +VIN_DATA_PIN_GROUP (vin1_data,12 ), +VIN_DATA_PIN_GROUP (vin1_data,10 ), +VIN_DATA_PIN_GROUP (vin1_data,8 ), +VIN_DATA_PIN_GROUP (vin1_data_b,24 ), +VIN_DATA_PIN_GROUP (vin1_data_b,20 ), +SH_PFC_PIN_GROUP (vin1_data18_b), +VIN_DATA_PIN_GROUP (vin1_data_b,16 ), +SH_PFC_PIN_GROUP (vin1_sync), +SH_PFC_PIN_GROUP (vin1_field), +SH_PFC_PIN_GROUP (vin1_clkenb), +SH_PFC_PIN_GROUP (vin1_clk), +VIN_DATA_PIN_GROUP (vin2_data,16 ), +VIN_DATA_PIN_GROUP (vin2_data,12 ), +VIN_DATA_PIN_GROUP (vin2_data,10 ), +VIN_DATA_PIN_GROUP (vin2_data,8 ), +SH_PFC_PIN_GROUP (vin2_sync), +SH_PFC_PIN_GROUP (vin2_field), +SH_PFC_PIN_GROUP (vin2_clkenb), +SH_PFC_PIN_GROUP (vin2_clk), +VIN_DATA_PIN_GROUP (vin3_data,16 ), +VIN_DATA_PIN_GROUP (vin3_data,12 ), +VIN_DATA_PIN_GROUP (vin3_data,10 ), +VIN_DATA_PIN_GROUP (vin3_data,8 ), +SH_PFC_PIN_GROUP (vin3_sync), +SH_PFC_PIN_GROUP (vin3_field), +SH_PFC_PIN_GROUP (vin3_clkenb), +SH_PFC_PIN_GROUP (vin3_clk), +VIN_DATA_PIN_GROUP (vin4_data,12 ), +VIN_DATA_PIN_GROUP (vin4_data,10 ), +VIN_DATA_PIN_GROUP (vin4_data,8 ), +SH_PFC_PIN_GROUP (vin4_sync), +SH_PFC_PIN_GROUP (vin4_field), +SH_PFC_PIN_GROUP (vin4_clkenb), +SH_PFC_PIN_GROUP (vin4_clk), +VIN_DATA_PIN_GROUP (vin5_data,12 ), +VIN_DATA_PIN_GROUP (vin5_data,10 ), +VIN_DATA_PIN_GROUP (vin5_data,8 ), +SH_PFC_PIN_GROUP (vin5_sync), +SH_PFC_PIN_GROUP (vin5_field), +SH_PFC_PIN_GROUP (vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), }; static const char * const avb_groups[] = {
@@ -1087,6 +1585,79 @@ static const char * const sdhi0_groups[] "sdhi0_wp", }; +static const char *const vin0_groups[] = { +"vin0_data24" , +"vin0_data20" , +"vin0_data18" , +"vin0_data16" , +"vin0_data12" , +"vin0_data10" , +"vin0_data8" , +"vin0_sync" , +"vin0_field" , +"vin0_clkenb" , +"vin0_clk" , +}; + +static const char *const vin1_groups[] = { +"vin1_data24" , +"vin1_data20" , +"vin1_data18" , +"vin1_data16" , +"vin1_data12" , +"vin1_data10" , +"vin1_data8" , +"vin1_data24_b" , +"vin1_data20_b" , +"vin1_data16_b" , +"vin1_sync" , +"vin1_field" , +"vin1_clkenb" , +"vin1_clk" , +}; + +static const char *const vin2_groups[] = { +"vin2_data16" , +"vin2_data12" , +"vin2_data10" , +"vin2_data8" , +"vin2_sync" , +"vin2_field" , +"vin2_clkenb" , +"vin2_clk" , +}; + +static const char *const vin3_groups[] = { +"vin3_data16" , +"vin3_data12" , +"vin3_data10" , +"vin3_data8" , +"vin3_sync" , +"vin3_field" , +"vin3_clkenb" , +"vin3_clk" , +}; + +static const char *const vin4_groups[] = { +"vin4_data12" , +"vin4_data10" , +"vin4_data8" , +"vin4_sync" , +"vin4_field" , +"vin4_clkenb" , +"vin4_clk" , +}; + +static const char *const vin5_groups[] = { +"vin5_data12" , +"vin5_data10" , +"vin5_data8" , +"vin5_sync" , +"vin5_field" , +"vin5_clkenb" , +"vin5_clk" , +}; +static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (can0),
@@ -1096,6 +1667,12 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (scif0),SH_PFC_FUNCTION (scif3 ),SH_PFC_FUNCTION (sdhi0 ), +SH_PFC_FUNCTION (vin0 ), +SH_PFC_FUNCTION (vin1 ), +SH_PFC_FUNCTION (vin2 ), +SH_PFC_FUNCTION (vin3 ), +SH_PFC_FUNCTION (vin4 ), + SH_PFC_FUNCTION(vin5), };static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Re: [PATCH v2] pinctrl: sh-pfc: r8a7792: add VIN pin groups
Hi Sergei,
Quoted 11 lines · Sergei Shtylyov
Add VIN[0-5] pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 6 R8A7792 PFC patches posted before (those should be collected by Geert)...Changes in version 2:
- fixed the SoC model in the changelog.
Thanks!
Quoted 8 lines
Index:
linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
===================================================================drivers/pinctrl/sh-pfc/pfc-r8a7792.c +3
-0+/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data24 = {
drivers/pinctrl/sh-pfc/pfc-r8a7792.c static const unsigned int sdhi0_wp_pins[ · line 1101
Quoted 10 lines
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +10
-0+/* B */ +RCAR_GP_PIN (5 ,4 ),RCAR_GP_PIN (5 ,5 ), +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,12 ),RCAR_GP_PIN (5 ,13 ), +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
Quoted 7 lines
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +7
-0+/* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), + }, +};
drivers/pinctrl/sh-pfc/pfc-r8a7792.c static const unsigned int sdhi0_wp_pins[ · line 1136
Quoted 10 lines
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +9
-0+static const unsigned int vin1_data18_pins[] = { +/* B */ +RCAR_GP_PIN (5 ,6 ),RCAR_GP_PIN (5 ,7 ), +RCAR_GP_PIN (5 ,8 ),RCAR_GP_PIN (5 ,9 ), +RCAR_GP_PIN (5 ,10 ),RCAR_GP_PIN (5 ,11 ), +/* G */ +RCAR_GP_PIN (5 ,14 ),RCAR_GP_PIN (5 ,15 ), +RCAR_GP_PIN (8 ,5 ),RCAR_GP_PIN (8 ,6 ), +RCAR_GP_PIN (8 ,6 ),RCAR_GP_PIN (8 ,7 ),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
drivers/pinctrl/sh-pfc/pfc-r8a7792.c static const unsigned int sdhi0_wp_pins[ · line 1108
Quoted 5 lines
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +5
-0+/* R */ +RCAR_GP_PIN (9 ,7 ),RCAR_GP_PIN (9 ,8 ), +RCAR_GP_PIN (9 ,9 ),RCAR_GP_PIN (9 ,10 ), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), +};
There's no need to resend. I'll fix it up when queuing in sh-pfc-for-v4.9.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add DU pin groups
In reply to Sergei ShtylyovAdd DU pin groups to the R8A7792 PFC driver.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus my 7 R8A7792 PFC patches posted before (those should be collected by Geert)...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 144 +++++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +144 -0
@@ -834,6 +834,120 @@ static const unsigned int can_clk_pins[]static const unsigned int can_clk_mux[] = {CAN_CLK_MARK , }; +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { +/* R[7:2], G[7:2], B[7:2] */ +RCAR_GP_PIN (0 ,7 ),RCAR_GP_PIN (0 ,6 ),RCAR_GP_PIN (0 ,5 ), +RCAR_GP_PIN (0 ,4 ),RCAR_GP_PIN (0 ,3 ),RCAR_GP_PIN (0 ,2 ), +RCAR_GP_PIN (0 ,15 ),RCAR_GP_PIN (0 ,14 ),RCAR_GP_PIN (0 ,13 ), +RCAR_GP_PIN (0 ,12 ),RCAR_GP_PIN (0 ,11 ),RCAR_GP_PIN (0 ,10 ), +RCAR_GP_PIN (0 ,23 ),RCAR_GP_PIN (0 ,22 ),RCAR_GP_PIN (0 ,21 ), +RCAR_GP_PIN (0 ,20 ),RCAR_GP_PIN (0 ,19 ),RCAR_GP_PIN (0 ,18 ), +}; +static const unsigned int du0_rgb666_mux[] = { +DU0_DR7_Y9_DATA7_MARK ,DU0_DR6_Y8_DATA6_MARK ,DU0_DR5_Y7_DATA5_MARK , +DU0_DR4_Y6_DATA4_MARK ,DU0_DR3_Y5_DATA3_MARK ,DU0_DR2_Y4_DATA2_MARK , +DU0_DG7_Y3_DATA15_MARK ,DU0_DG6_Y2_DATA14_MARK ,DU0_DG5_Y1_DATA13_MARK , +DU0_DG4_Y0_DATA12_MARK ,DU0_DG3_C7_DATA11_MARK ,DU0_DG2_C6_DATA10_MARK , +DU0_DB7_C5_MARK ,DU0_DB6_C4_MARK ,DU0_DB5_C3_MARK , +DU0_DB4_C2_MARK ,DU0_DB3_C1_MARK ,DU0_DB2_C0_MARK , +}; +static const unsigned int du0_rgb888_pins[] = { +/* R[7:0], G[7:0], B[7:0] */ +RCAR_GP_PIN (0 ,7 ),RCAR_GP_PIN (0 ,6 ),RCAR_GP_PIN (0 ,5 ), +RCAR_GP_PIN (0 ,4 ),RCAR_GP_PIN (0 ,3 ),RCAR_GP_PIN (0 ,2 ), +RCAR_GP_PIN (0 ,1 ),RCAR_GP_PIN (0 ,0 ), +RCAR_GP_PIN (0 ,15 ),RCAR_GP_PIN (0 ,14 ),RCAR_GP_PIN (0 ,13 ), +RCAR_GP_PIN (0 ,12 ),RCAR_GP_PIN (0 ,11 ),RCAR_GP_PIN (0 ,10 ), +RCAR_GP_PIN (0 ,9 ),RCAR_GP_PIN (0 ,8 ), +RCAR_GP_PIN (0 ,23 ),RCAR_GP_PIN (0 ,22 ),RCAR_GP_PIN (0 ,21 ), +RCAR_GP_PIN (0 ,20 ),RCAR_GP_PIN (0 ,19 ),RCAR_GP_PIN (0 ,18 ), +RCAR_GP_PIN (0 ,17 ),RCAR_GP_PIN (0 ,16 ), +}; +static const unsigned int du0_rgb888_mux[] = { +DU0_DR7_Y9_DATA7_MARK ,DU0_DR6_Y8_DATA6_MARK ,DU0_DR5_Y7_DATA5_MARK , +DU0_DR4_Y6_DATA4_MARK ,DU0_DR3_Y5_DATA3_MARK ,DU0_DR2_Y4_DATA2_MARK , +DU0_DR1_DATA1_MARK ,DU0_DR0_DATA0_MARK , +DU0_DG7_Y3_DATA15_MARK ,DU0_DG6_Y2_DATA14_MARK ,DU0_DG5_Y1_DATA13_MARK , +DU0_DG4_Y0_DATA12_MARK ,DU0_DG3_C7_DATA11_MARK ,DU0_DG2_C6_DATA10_MARK , +DU0_DG1_DATA9_MARK ,DU0_DG0_DATA8_MARK , +DU0_DB7_C5_MARK ,DU0_DB6_C4_MARK ,DU0_DB5_C3_MARK , +DU0_DB4_C2_MARK ,DU0_DB3_C1_MARK ,DU0_DB2_C0_MARK , +DU0_DB1_MARK ,DU0_DB0_MARK , +}; +static const unsigned int du0_sync_pins[] = { +/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ +RCAR_GP_PIN (0 ,25 ),RCAR_GP_PIN (0 ,24 ), +}; +static const unsigned int du0_sync_mux[] = { +DU0_EXVSYNC_DU0_VSYNC_MARK ,DU0_EXHSYNC_DU0_HSYNC_MARK , +}; +static const unsigned int du0_oddf_pins[] = { +/* EXODDF/ODDF/DISP/CDE */ +RCAR_GP_PIN (0 ,26 ), +}; +static const unsigned int du0_oddf_mux[] = { +DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK +}; +static const unsigned int du0_disp_pins[] = { +/* DISP */ +RCAR_GP_PIN (0 ,27 ), +}; +static const unsigned int du0_disp_mux[] = { +DU0_DISP_MARK , +}; +static const unsigned int du0_cde_pins[] = { +/* CDE */ +RCAR_GP_PIN (0 ,28 ), +}; +static const unsigned int du0_cde_mux[] = { +DU0_CDE_MARK , +}; +static const unsigned int du1_rgb666_pins[] = { +/* R[7:2], G[7:2], B[7:2] */ +RCAR_GP_PIN (1 ,5 ),RCAR_GP_PIN (1 ,4 ),RCAR_GP_PIN (1 ,3 ), +RCAR_GP_PIN (1 ,2 ),RCAR_GP_PIN (1 ,1 ),RCAR_GP_PIN (1 ,0 ), +RCAR_GP_PIN (1 ,11 ),RCAR_GP_PIN (1 ,10 ),RCAR_GP_PIN (1 ,9 ), +RCAR_GP_PIN (1 ,8 ),RCAR_GP_PIN (1 ,7 ),RCAR_GP_PIN (1 ,6 ), +RCAR_GP_PIN (1 ,17 ),RCAR_GP_PIN (1 ,16 ),RCAR_GP_PIN (1 ,15 ), +RCAR_GP_PIN (1 ,14 ),RCAR_GP_PIN (1 ,13 ),RCAR_GP_PIN (1 ,12 ), +}; +static const unsigned int du1_rgb666_mux[] = { +DU1_DR7_DATA5_MARK ,DU1_DR6_DATA4_MARK ,DU1_DR5_Y7_DATA3_MARK , +DU1_DR4_Y6_DATA2_MARK ,DU1_DR3_Y5_DATA1_MARK ,DU1_DR2_Y4_DATA0_MARK , +DU1_DG7_Y3_DATA11_MARK ,DU1_DG6_Y2_DATA10_MARK ,DU1_DG5_Y1_DATA9_MARK , +DU1_DG4_Y0_DATA8_MARK ,DU1_DG3_C7_DATA7_MARK ,DU1_DG2_C6_DATA6_MARK , +DU1_DB7_C5_MARK ,DU1_DB6_C4_MARK ,DU1_DB5_C3_DATA15_MARK , +DU1_DB4_C2_DATA14_MARK ,DU1_DB3_C1_DATA13_MARK ,DU1_DB2_C0_DATA12_MARK , +}; +static const unsigned int du1_sync_pins[] = { +/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ +RCAR_GP_PIN (1 ,19 ),RCAR_GP_PIN (1 ,18 ), +}; +static const unsigned int du1_sync_mux[] = { +DU1_EXVSYNC_DU1_VSYNC_MARK ,DU1_EXHSYNC_DU1_HSYNC_MARK , +}; +static const unsigned int du1_oddf_pins[] = { +/* EXODDF/ODDF/DISP/CDE */ +RCAR_GP_PIN (1 ,20 ), +}; +static const unsigned int du1_oddf_mux[] = { +DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK +}; +static const unsigned int du1_disp_pins[] = { +/* DISP */ +RCAR_GP_PIN (1 ,21 ), +}; +static const unsigned int du1_disp_mux[] = { +DU1_DISP_MARK , +}; +static const unsigned int du1_cde_pins[] = { +/* CDE */ +RCAR_GP_PIN (1 ,22 ), +}; +static const unsigned int du1_cde_mux[] = { +DU1_CDE_MARK , +};/* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = {/* IRQ0 */
@@ -1448,6 +1562,17 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (can0_data),SH_PFC_PIN_GROUP (can1_data),SH_PFC_PIN_GROUP (can_clk), +SH_PFC_PIN_GROUP (du0_rgb666), +SH_PFC_PIN_GROUP (du0_rgb888), +SH_PFC_PIN_GROUP (du0_sync), +SH_PFC_PIN_GROUP (du0_oddf), +SH_PFC_PIN_GROUP (du0_disp), +SH_PFC_PIN_GROUP (du0_cde), +SH_PFC_PIN_GROUP (du1_rgb666), +SH_PFC_PIN_GROUP (du1_sync), +SH_PFC_PIN_GROUP (du1_oddf), +SH_PFC_PIN_GROUP (du1_disp), +SH_PFC_PIN_GROUP (du1_cde),SH_PFC_PIN_GROUP (intc_irq0),SH_PFC_PIN_GROUP (intc_irq1), SH_PFC_PIN_GROUP(intc_irq2),
@@ -1548,6 +1673,23 @@ static const char * const can1_groups[] "can_clk", }; +static const char *const du0_groups[] = { +"du0_rgb666" , +"du0_rgb888" , +"du0_sync" , +"du0_oddf" , +"du0_disp" , +"du0_cde" , +}; + +static const char *const du1_groups[] = { +"du1_rgb666" , +"du1_sync" , +"du1_oddf" , +"du1_disp" , +"du1_cde" , +}; +static const char *const intc_groups[] = {"intc_irq0" ,"intc_irq1" ,
@@ -1662,6 +1804,8 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (avb),SH_PFC_FUNCTION (can0),SH_PFC_FUNCTION (can1), +SH_PFC_FUNCTION (du0), +SH_PFC_FUNCTION (du1),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc), SH_PFC_FUNCTION(scif0),
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add DU pin groups
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Add DU pin groups to the R8A7792 PFC driver.
Signed-off-by Sergei Shtylyov <[email protected]>
Thanks!
Will queue in sh-pfc-for-v4.9.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add DU pin groups
In reply to Sergei ShtylyovAdd QSPI pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov <[email protected]>.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +33 -0
@@ -1034,6 +1034,29 @@ static const unsigned int lbsc_ex_cs5_pistatic const unsigned int lbsc_ex_cs5_mux[] = {EX_CS5_N_MARK , }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { +/* SPCLK, SSL */ +RCAR_GP_PIN (3 ,25 ),RCAR_GP_PIN (3 ,26 ), +}; +static const unsigned int qspi_ctrl_mux[] = { +SPCLK_MARK ,SSL_MARK , +}; +static const unsigned int qspi_data2_pins[] = { +/* MOSI_IO0, MISO_IO1 */ +RCAR_GP_PIN (3 ,4 ),RCAR_GP_PIN (3 ,5 ), +}; +static const unsigned int qspi_data2_mux[] = { +MOSI_IO0_MARK ,MISO_IO1_MARK , +}; +static const unsigned int qspi_data4_pins[] = { +/* MOSI_IO0, MISO_IO1, IO2, IO3 */ +RCAR_GP_PIN (3 ,4 ),RCAR_GP_PIN (3 ,5 ),RCAR_GP_PIN (3 ,23 ), +RCAR_GP_PIN (3 ,24 ), +}; +static const unsigned int qspi_data4_mux[] = { +MOSI_IO0_MARK ,MISO_IO1_MARK ,IO2_MARK ,IO3_MARK , +};/* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = {/* RX, TX */
@@ -1585,6 +1608,9 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (lbsc_ex_cs3),SH_PFC_PIN_GROUP (lbsc_ex_cs4),SH_PFC_PIN_GROUP (lbsc_ex_cs5), +SH_PFC_PIN_GROUP (qspi_ctrl), +SH_PFC_PIN_GROUP (qspi_data2), +SH_PFC_PIN_GROUP (qspi_data4),SH_PFC_PIN_GROUP (scif0_data),SH_PFC_PIN_GROUP (scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1708,6 +1734,12 @@ static const char * const lbsc_groups[] "lbsc_ex_cs5", }; +static const char *const qspi_groups[] = { +"qspi_ctrl" , +"qspi_data2" , +"qspi_data4" , +}; +static const char *const scif0_groups[] = {"scif0_data" ,"scif0_clk" ,
@@ -1808,6 +1840,7 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (du1),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc), +SH_PFC_FUNCTION (qspi),SH_PFC_FUNCTION (scif0),SH_PFC_FUNCTION (scif3), SH_PFC_FUNCTION(sdhi0),
PATCH RESEND 1/1 pinctrl: sh-pfc: r8a7792: add QSPI pin groups
In reply to Sergei ShtylyovAdd QSPI pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov <[email protected]>.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo...
Disregard the patch just posted with the stale subject please.
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +33 -0
@@ -1034,6 +1034,29 @@ static const unsigned int lbsc_ex_cs5_pistatic const unsigned int lbsc_ex_cs5_mux[] = {EX_CS5_N_MARK , }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { +/* SPCLK, SSL */ +RCAR_GP_PIN (3 ,25 ),RCAR_GP_PIN (3 ,26 ), +}; +static const unsigned int qspi_ctrl_mux[] = { +SPCLK_MARK ,SSL_MARK , +}; +static const unsigned int qspi_data2_pins[] = { +/* MOSI_IO0, MISO_IO1 */ +RCAR_GP_PIN (3 ,4 ),RCAR_GP_PIN (3 ,5 ), +}; +static const unsigned int qspi_data2_mux[] = { +MOSI_IO0_MARK ,MISO_IO1_MARK , +}; +static const unsigned int qspi_data4_pins[] = { +/* MOSI_IO0, MISO_IO1, IO2, IO3 */ +RCAR_GP_PIN (3 ,4 ),RCAR_GP_PIN (3 ,5 ),RCAR_GP_PIN (3 ,23 ), +RCAR_GP_PIN (3 ,24 ), +}; +static const unsigned int qspi_data4_mux[] = { +MOSI_IO0_MARK ,MISO_IO1_MARK ,IO2_MARK ,IO3_MARK , +};/* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = {/* RX, TX */
@@ -1585,6 +1608,9 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (lbsc_ex_cs3),SH_PFC_PIN_GROUP (lbsc_ex_cs4),SH_PFC_PIN_GROUP (lbsc_ex_cs5), +SH_PFC_PIN_GROUP (qspi_ctrl), +SH_PFC_PIN_GROUP (qspi_data2), +SH_PFC_PIN_GROUP (qspi_data4),SH_PFC_PIN_GROUP (scif0_data),SH_PFC_PIN_GROUP (scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1708,6 +1734,12 @@ static const char * const lbsc_groups[] "lbsc_ex_cs5", }; +static const char *const qspi_groups[] = { +"qspi_ctrl" , +"qspi_data2" , +"qspi_data4" , +}; +static const char *const scif0_groups[] = {"scif0_data" ,"scif0_clk" ,
@@ -1808,6 +1840,7 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (du1),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc), +SH_PFC_FUNCTION (qspi),SH_PFC_FUNCTION (scif0),SH_PFC_FUNCTION (scif3), SH_PFC_FUNCTION(sdhi0),
Re: [PATCH resend] pinctrl: sh-pfc: r8a7792: add QSPI pin groups
Quoted 6 lines · Sergei Shtylyov
Add QSPI pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH resend] pinctrl: sh-pfc: r8a7792: add QSPI pin groups
In reply to Sergei ShtylyovQuoted 6 lines · Sergei Shtylyov
Add QSPI pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Expecting Geert to queue it.
Yours,
Linus Walleij
PATCH 1/1 pinctrl: sh-pfc: r8a7792: add MSIOF pin groups
In reply to Sergei ShtylyovAdd MSIOF0/1 pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov <[email protected]>.
---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus the QSPI patch last week...
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 82 +++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7792.c +82 -0
@@ -1034,6 +1034,64 @@ static const unsigned int lbsc_ex_cs5_pistatic const unsigned int lbsc_ex_cs5_mux[] = {EX_CS5_N_MARK , }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { +/* SCK */ +RCAR_GP_PIN (10 ,0 ), +}; +static const unsigned int msiof0_clk_mux[] = { +MSIOF0_SCK_MARK , +}; +static const unsigned int msiof0_sync_pins[] = { +/* SYNC */ +RCAR_GP_PIN (10 ,1 ), +}; +static const unsigned int msiof0_sync_mux[] = { +MSIOF0_SYNC_MARK , +}; +static const unsigned int msiof0_rx_pins[] = { +/* RXD */ +RCAR_GP_PIN (10 ,4 ), +}; +static const unsigned int msiof0_rx_mux[] = { +MSIOF0_RXD_MARK , +}; +static const unsigned int msiof0_tx_pins[] = { +/* TXD */ +RCAR_GP_PIN (10 ,3 ), +}; +static const unsigned int msiof0_tx_mux[] = { +MSIOF0_TXD_MARK , +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { +/* SCK */ +RCAR_GP_PIN (10 ,5 ), +}; +static const unsigned int msiof1_clk_mux[] = { +MSIOF1_SCK_MARK , +}; +static const unsigned int msiof1_sync_pins[] = { +/* SYNC */ +RCAR_GP_PIN (10 ,6 ), +}; +static const unsigned int msiof1_sync_mux[] = { +MSIOF1_SYNC_MARK , +}; +static const unsigned int msiof1_rx_pins[] = { +/* RXD */ +RCAR_GP_PIN (10 ,9 ), +}; +static const unsigned int msiof1_rx_mux[] = { +MSIOF1_RXD_MARK , +}; +static const unsigned int msiof1_tx_pins[] = { +/* TXD */ +RCAR_GP_PIN (10 ,8 ), +}; +static const unsigned int msiof1_tx_mux[] = { +MSIOF1_TXD_MARK , +};/* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = {/* SPCLK, SSL */
@@ -1608,6 +1666,14 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (lbsc_ex_cs3),SH_PFC_PIN_GROUP (lbsc_ex_cs4),SH_PFC_PIN_GROUP (lbsc_ex_cs5), +SH_PFC_PIN_GROUP (msiof0_clk), +SH_PFC_PIN_GROUP (msiof0_sync), +SH_PFC_PIN_GROUP (msiof0_rx), +SH_PFC_PIN_GROUP (msiof0_tx), +SH_PFC_PIN_GROUP (msiof1_clk), +SH_PFC_PIN_GROUP (msiof1_sync), +SH_PFC_PIN_GROUP (msiof1_rx), +SH_PFC_PIN_GROUP (msiof1_tx),SH_PFC_PIN_GROUP (qspi_ctrl),SH_PFC_PIN_GROUP (qspi_data2), SH_PFC_PIN_GROUP(qspi_data4),
@@ -1734,6 +1800,20 @@ static const char * const lbsc_groups[] "lbsc_ex_cs5", }; +static const char *const msiof0_groups[] = { +"msiof0_clk" , +"msiof0_sync" , +"msiof0_rx" , +"msiof0_tx" , +}; + +static const char *const msiof1_groups[] = { +"msiof1_clk" , +"msiof1_sync" , +"msiof1_rx" , +"msiof1_tx" , +}; +static const char *const qspi_groups[] = {"qspi_ctrl" ,"qspi_data2" ,
@@ -1840,6 +1920,8 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (du1),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (lbsc), +SH_PFC_FUNCTION (msiof0), +SH_PFC_FUNCTION (msiof1),SH_PFC_FUNCTION (qspi),SH_PFC_FUNCTION (scif0), SH_PFC_FUNCTION(scif3),
Re: [PATCH] pinctrl: sh-pfc: r8a7792: add MSIOF pin groups
Quoted 6 lines · Sergei Shtylyov
Add MSIOF0/1 pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds