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powerpc perf events: Fix priority of MSR HV vs PR bits

PATCH New Michael Neuling 1 participant 2 messages Oct 15, 2009

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Michael Neuling

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#0 lore raw

PATCH 1/1 powerpc perf events: Fix priority of MSR HV vs PR bits

The architecture defines that if MSR PR is set we are in problem state irrespective of the HV bit. This fixes perf events to reflect this.

Signed-off-by Michael Neuling <[email protected]>
CC [email protected]

---
Tested on PHYP and BML.

This could go back into 31 too with s/event/counters/g. It only effects bare metal on server chips, so no biggy if it doesn't.

 arch/powerpc/kernel/perf_event.c |   17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)
arch/powerpc/kernel/perf_event.c +10 -7
Index: linux-2.6-ozlabs/arch/powerpc/kernel/perf_event.c
===================================================================
@@ -116,20 +116,23 @@ static inline void perf_get_data_addr(st
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
 	unsigned long mmcra = regs->dsisr;
+	unsigned long sihv = MMCRA_SIHV;
+	unsigned long sipr = MMCRA_SIPR;
 
 	if (TRAP(regs) != 0xf00)
 		return 0;	/* not a PMU interrupt */
 
 	if (ppmu->flags & PPMU_ALT_SIPR) {
-		if (mmcra & POWER6_MMCRA_SIHV)
-			return PERF_RECORD_MISC_HYPERVISOR;
-		return (mmcra & POWER6_MMCRA_SIPR) ?
-			PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL;
+		sihv = POWER6_MMCRA_SIHV;
+		sipr = POWER6_MMCRA_SIPR;
 	}
-	if (mmcra & MMCRA_SIHV)
+
+	/* PR has priority over HV, so order below is important */
+	if (mmcra & sipr)
+		return PERF_RECORD_MISC_USER;
+	if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
 		return PERF_RECORD_MISC_HYPERVISOR;
-	return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER :
-		PERF_RECORD_MISC_KERNEL;
+	return PERF_RECORD_MISC_KERNEL;
 }
 
 /*
author
#1 lore raw

PATCH 1/1 powerpc perf events: Fix priority of MSR HV vs PR bits

The architecture defines that if MSR PR is set we are in problem state irrespective of the HV bit. This fixes perf events to reflect this.

Also, on bare metal systems, samples taken in Linux will now be reported as kernel rather than hypervisor.

Signed-off-by Michael Neuling <[email protected]>
CC [email protected]

---
Paulus suggested that the comment needed updating to reflect the additional functionality that I've changed.

 arch/powerpc/kernel/perf_event.c |   17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)
arch/powerpc/kernel/perf_event.c +10 -7
Index: linux-2.6-ozlabs/arch/powerpc/kernel/perf_event.c
===================================================================
@@ -116,20 +116,23 @@ static inline void perf_get_data_addr(st
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
 	unsigned long mmcra = regs->dsisr;
+	unsigned long sihv = MMCRA_SIHV;
+	unsigned long sipr = MMCRA_SIPR;
 
 	if (TRAP(regs) != 0xf00)
 		return 0;	/* not a PMU interrupt */
 
 	if (ppmu->flags & PPMU_ALT_SIPR) {
-		if (mmcra & POWER6_MMCRA_SIHV)
-			return PERF_RECORD_MISC_HYPERVISOR;
-		return (mmcra & POWER6_MMCRA_SIPR) ?
-			PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL;
+		sihv = POWER6_MMCRA_SIHV;
+		sipr = POWER6_MMCRA_SIPR;
 	}
-	if (mmcra & MMCRA_SIHV)
+
+	/* PR has priority over HV, so order below is important */
+	if (mmcra & sipr)
+		return PERF_RECORD_MISC_USER;
+	if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
 		return PERF_RECORD_MISC_HYPERVISOR;
-	return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER :
-		PERF_RECORD_MISC_KERNEL;
+	return PERF_RECORD_MISC_KERNEL;
 }
 
 /*