440spe MQ initialization

PATCH New Yuri Tikhonov 5 participants 16 messages Sep 23, 2008 – Oct 17, 2008

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Yuri Tikhonov

author

2008-09-23 08:37 UTC #0 lore raw

PATCH 1/1 440spe MQ initialization

Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results.

Signed-off-by Yuri Tikhonov <[email protected]>

---
 cpu/ppc4xx/44x_spd_ddr2.c      |   10 ++++++----
 include/asm-ppc/ppc4xx-sdram.h |    5 +++++
 2 files changed, 11 insertions(+), 4 deletions(-)

cpu/ppc4xx/44x_spd_ddr2.c +6 -4

index f1d7684..995d5fe 100644
@@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	/*
 	 * Set optimal value for Memory Queue HB/LL Configuration registers
 	 */
-	mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
-	      SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
-	mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
-	      SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+	      SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+	      SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+	mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+	      SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+	      SDRAM_CONF1LL_RPLM);
 	mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
 #endif
 }

include/asm-ppc/ppc4xx-sdram.h +5 -0

index 8efa557..98faced 100644
@@ -272,8 +272,11 @@
 #define SDRAM_CONF1HB_PRPD	0x00080000	/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1HB_PWPD	0x00040000	/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1HB_PRW	0x00020000	/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM	0x00001000	/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1HB_RPEN	0x00000800	/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1HB_RFTE	0x00000400	/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL	0x00000080	/* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK	0x0000F380	/* RPLM & WRCL mask */
 
 #define SDRAM_ERRSTATHB		(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
 #define SDRAM_ERRADDUHB		(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */

@@ -284,8 +287,10 @@
 #define SDRAM_CONF1LL_PRPD	0x00080000		/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1LL_PWPD	0x00040000		/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1LL_PRW	0x00020000		/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM	0x00001000		/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1LL_RPEN	0x00000800		/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1LL_RFTE	0x00000400		/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK	0x0000F000		/* RPLM mask */
 
 #define SDRAM_ERRSTATLL		(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
 #define SDRAM_ERRADDULL		(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */

Signature · 6 lines

1.5.6.1

 Regards, Yuri
-- 
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Stefan Roese

2008-09-23 09:22 UTC #1 lore raw

PATCH 1/1 440spe MQ initialization

Hi Yuri,

Quoted 9 lines · Yuri Tikhonov

Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results.

AMCC just recently updated the 440SP(e) MQ initialization with this patch:

commit 079589bcfb24ba11068460276a3cc9549ab5346f

Author: Prodyut  Hazarika <[email protected]>
Date:   Wed Aug 20 09:38:51 2008 -0700

ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by Prodyut Hazarika <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

I have a bad feeling changing this "optimized" settings without AMCC's specific ACK.

Prodyut, are you ok with Yuri's change?

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

Yuri Tikhonov

author

2008-09-23 09:36 UTC #2 lore raw

PATCH 1/1 440spe MQ initialization

Hello,

BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:

---
Dear Yuri,

here is some additional (and hopefully helpful) information from AMCC regarding the observed hangs on the katmai board:

Quoted 6 lines

If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:

Quoted 8 lines

PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering

Best regards,

Wolfgang Denk
---

Quoted 41 lines · On Tuesday, September 23, 2008 you wrote:

Hi Yuri,
Quoted 9 lines · Yuri Tikhonov
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results.
AMCC just recently updated the 440SP(e) MQ initialization with this patch:
commit 079589bcfb24ba11068460276a3cc9549ab5346f
Author: Prodyut  Hazarika <[email protected]>
Date:   Wed Aug 20 09:38:51 2008 -0700
ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX
- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors
- Add register bit definitions for Memory Queue Configuration registers
Signed-off-by Prodyut Hazarika <[email protected]>
Signed-off-by Stefan Roese <[email protected]>
I have a bad feeling changing this "optimized" settings without AMCC's specific ACK.
Prodyut, are you ok with Yuri's change?
Thanks.

Quoted 8 lines

Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

Regards, Yuri

--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Stefan Roese

2008-09-23 09:43 UTC #3 lore raw

PATCH 1/1 440spe MQ initialization

Quoted 4 lines · Yuri Tikhonov

BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:

Quoted 20 lines

---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering

Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.

Best regards,
Stefan

Olga Buchonina

2008-09-23 13:31 UTC #4 lore raw

PATCH 1/1 440spe MQ initialization

Yuriy/Stefan-

This is AMCC confirmation about configuration.

Regards,

Olga Buchonina
AMCC PowerPC Applications Engineering

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Tuesday, September 23, 2008 4:43 AM
To: Yuri Tikhonov
Cc: u-boot at lists.denx.de; Prodyut Hazarika; Olga Buchonina
Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization

Quoted 25 lines · Yuri Tikhonov

BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk
on Tue Mar 18 2008:
---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering

Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.

Best regards,
Stefan

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Prodyut Hazarika

2008-09-23 15:25 UTC #5 lore raw

PATCH 1/1 440spe MQ initialization

In reply to Stefan Roese

Hi Stefan/Yuri,
I looked at the changes.
I had already submitted the changes in an earlier patch. This code to set the PLB4 arbiter depth was moved to cpu_init_f function in cpu/ppc4xx/cpu_init.c since it is common across many processor families.

Please don't do the same thing again in the program_memory_queue function.

Thanks,
Prodyut

________________________________

From: Stefan Roese [mailto:sr at denx.de]
Sent: Tue 9/23/2008 2:43 AM
To: Yuri Tikhonov
Cc: u-boot at lists.denx.de; Prodyut Hazarika; Olga Buchonina
Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization

Quoted 4 lines · Yuri Tikhonov

BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:

Quoted 20 lines

---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering

Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.

Best regards,
Stefan

Yuri Tikhonov

author

2008-09-23 15:35 UTC #6 lore raw

PATCH 1/1 440spe MQ initialization

Hello Prodyut,

Quoted 7 lines · On Tuesday, September 23, 2008 you wrote:

Hi Stefan/Yuri,
I looked at the changes.
I had already submitted the changes in an earlier patch. This code to set the PLB4 arbiter depth was moved to cpu_init_f function in cpu/ppc4xx/cpu_init.c since it is common across many processor families.
Please don't do the same thing again in the program_memory_queue function.

Well, actually my patch doesn't have a deal with the PLB configuring,
but with MQ only. So, it's OK here.

But then another question arises: in Linux, in
ppc440spe_configure_raid_devices(), beside the other things we do the following:

/* Configure PLB as follows:
* PLB: 0xDF000000. This means
* - Priority level 00 fair priority,
* - Priority level 01 fair priority,
* - Priority level 11 fair priority,
* - High Bus Utilization enabled,
* - 4 Deep read pipe,
* - 2 Deep write pipe.
*/
mask = (1 << PLB_ACR_PPM0) | (1 << PLB_ACR_PPM1) | (1 << PLB_ACR_PPM3) |
(1 << PLB_ACR_HBU) | ((3 & PLB_ACR_RDP_MSK) << PLB_ACR_RDP) | (1 << PLB_ACR_WRP);
mtdcr(DCRN_PLB0_ACR, mask);
mtdcr(DCRN_PLB1_ACR, mask);

Is it OK, or should we remove these strings from the Linux driver,
assuming U-Boot has already done this ?

Thanks in advance,
Yuri

Quoted 35 lines

From: Stefan Roese [mailto:sr at denx.de]
Sent: Tue 9/23/2008 2:43 AM
To: Yuri Tikhonov
Cc: u-boot at lists.denx.de; Prodyut Hazarika; Olga Buchonina
Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization
Quoted 4 lines · Yuri Tikhonov
BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:
Quoted 20 lines
---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering
Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.

Quoted 8 lines

Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Prodyut Hazarika

2008-09-23 15:37 UTC #7 lore raw

PATCH 1/1 440spe MQ initialization

Hi Yuri,

Quoted 2 lines

Is it OK, or should we remove these strings from the Linux driver, assuming U-Boot has already done this ?

Please go ahead and remove these from the linux driver. And I think this driver has not been submitted to the powerpc tree, since I still don't see it in Josh's or Linus's tree.

Thanks,
Prodyut

Quoted 35 lines

From: Stefan Roese [mailto:sr at denx.de]
Sent: Tue 9/23/2008 2:43 AM
To: Yuri Tikhonov
Cc: u-boot at lists.denx.de; Prodyut Hazarika; Olga Buchonina
Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization
Quoted 4 lines · Yuri Tikhonov
BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:
Quoted 20 lines
---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering
Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.

Quoted 8 lines

Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Yuri Tikhonov

author

2008-09-23 15:45 UTC #8 lore raw

PATCH 1/1 440spe MQ initialization

Hi Prodyut,

Quoted 6 lines · On Tuesday, September 23, 2008 you wrote:

Hi Yuri,
Quoted 2 lines
Is it OK, or should we remove these strings from the Linux driver, assuming U-Boot has already done this ?
Please go ahead and remove these from the linux driver.

Thanks for confirmation, will do.

Quoted 2 lines

And I think this driver has not been submitted to the powerpc tree, since I
still don't see it in Josh's or Linus's tree.

Yep, for now it's present in the linux-2.6-denx tree only. We are
about to post this to MLs along with our RAID-6 related changes soon.

Quoted 45 lines

Quoted 35 lines
From: Stefan Roese [mailto:sr at denx.de]
Sent: Tue 9/23/2008 2:43 AM
To: Yuri Tikhonov
Cc: u-boot at lists.denx.de; Prodyut Hazarika; Olga Buchonina
Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization
Quoted 4 lines · Yuri Tikhonov
BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:
Quoted 20 lines
---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering
Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.
Quoted 8 lines
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

Quoted 3 lines

--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Regards, Yuri

--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Stefan Roese

2008-09-25 07:42 UTC #9 lore raw

PATCH 1/1 440spe MQ initialization

Quoted 6 lines · Yuri Tikhonov

Quoted 4 lines
Quoted 2 lines
Is it OK, or should we remove these strings from the Linux driver, assuming U-Boot has already done this ?
Please go ahead and remove these from the linux driver.
Thanks for confirmation, will do.

I have to admit that I am a little confused now. Are there now any patches that should be applied to U-Boot regarding the MQ and/or the PLB arbiter configuration? It seems to me that Yuri's configuration from the RAID driver (which will be dropped in the RAID driver soon) is not fully covered in the current U-Boot version.

So please let me know if Yuri's original MQ patch should be applied and if there is another PLB arbiter patch that should be applied too.

Thanks.

Best regards,
Stefan

Prodyut Hazarika

2008-09-25 13:17 UTC #10 lore raw

PATCH 1/1 440spe MQ initialization

Quoted 5 lines

I have to admit that I am a little confused now. Are there now any patches that should be applied to U-Boot regarding the MQ and/or the PLB arbiter configuration?

There is no patch that needs to be applied for PLB arbiter configuration. My earlier patch covered that.

Quoted 3 lines

It seems to me that Yuri's configuration from the RAID driver (which will be dropped in the RAID driver soon) is not fully covered in the current U-Boot version.

Yuri's configuration from RAID driver should be droppred coz changing MQ/PLB4 registers from Linux is not recommended

Quoted 2 lines

So please let me know if Yuri's original MQ patch should be applied and if there is another PLB arbiter patch that should be applied too.

Yuri's patch does the following
- set RLPM (read passing limit) bits in MQ register to 1,
- set WRCL (MCIF cycle limit) in MQ registers to 1.
In my testing, as far as I can remember, these values were set to 1 by default. I had tested with Canyonlands, Kilauea, Katmai and Glacier boards. So unless Yuri found that these values were not default values in some processor, Yuri's patch should be applied.

Thanks,
Prodyut

Prodyut Hazarika

2008-09-23 15:31 UTC #11 lore raw

PATCH 1/1 440spe MQ initialization

In reply to Stefan Roese

Hi Yuri/Stefan,
I remember duriing my testing that the default Read passing limit (RPML) and MCIF limit (WRCL) was 1. So there was no need to set these registers again to the same values.

Thanks,
Prodyut

: Tue 9/23/2008 2:43 AM
To: Yuri Tikhonov
Cc: u-boot at lists.denx.de; Prodyut Hazarika; Olga Buchonina
Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization

Quoted 4 lines · Yuri Tikhonov

BTW, when I said "recommended by AMCC" in the patch description I
referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:

Quoted 20 lines

---
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
Quoted 14 lines
If possible, can you please check if you still see the lock up when you program MQ as follows:
set value in HB and if you are using LL also as follows:
MQ0_CF1H = 0x80001C80
MQ0_CF1L = 0x80001C80
Additionally, make sure that your PLB settings are:
PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue.
I also would like to know how you are programming your DMA and how is the traffic is pipelined.
Regards,
Olga Buchonina
AMCC PowerPC Applications Engineering

Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.

Best regards,
Stefan

Wolfgang Denk

2008-10-16 23:10 UTC #12 lore raw

PATCH 1/1 440spe MQ initialization

In reply to Yuri Tikhonov

Dear Stefan,

Quoted 10 lines · In message <[email protected]> Yuri Tikhonov wrote:

Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results.

Quoted 5 lines

Signed-off-by Yuri Tikhonov <[email protected]>

---
 cpu/ppc4xx/44x_spd_ddr2.c      |   10 ++++++----
 include/asm-ppc/ppc4xx-sdram.h |    5 +++++
 2 files changed, 11 insertions(+), 4 deletions(-)

I must admit that I lost track in the discussion following this posting what the real state of affairs is now. Do we need to change anything in U-Boot, or not, and why not?

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The ideal situation is to have massive computing power right at home.
Something that dims the streetlights and shrinks the picture  on  the
neighbours' TVs when you boot it up.

Stefan Roese

2008-10-17 09:42 UTC #13 lore raw

PATCH 1/1 440spe MQ initialization

Hi Wolfgang,

Quoted 16 lines · Wolfgang Denk

Quoted 10 lines
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results.
Quoted 5 lines
Signed-off-by Yuri Tikhonov <[email protected]>
---
 cpu/ppc4xx/44x_spd_ddr2.c      |   10 ++++++----
 include/asm-ppc/ppc4xx-sdram.h |    5 +++++
 2 files changed, 11 insertions(+), 4 deletions(-)

Quoted 3 lines

I must admit that I lost track in the discussion following this posting what the real state of affairs is now. Do we need to change anything in U-Boot, or not, and why not?

I also lost track of whats really needed, I'm afraid. That's why I asked about this a few weeks ago. Here an extract from the last mail:

Quoted 10 lines · Prodyut Hazarika

Quoted 2 lines
So please let me know if Yuri's original MQ patch should be applied and if there is another PLB arbiter patch that should be applied too.
Yuri's patch does the following
- set RLPM (read passing limit) bits in MQ register to 1,
- set WRCL (MCIF cycle limit) in MQ registers to 1.
In my testing, as far as I can remember, these values were set to 1 by default. I had tested with Canyonlands, Kilauea, Katmai and Glacier boards. So unless Yuri found that these values were not default values in some processor, Yuri's patch should be applied.

So it seems that the current code relies on some already preset (default) values in those registers. I don't really like this. I'll try to provide a patch that configures those registers completely in a short while.

It would be great if Yuri could test this on a target to see if we are still missing something.

Best regards,
Stefan

Wolfgang Denk

2008-10-17 10:15 UTC #14 lore raw

PATCH 1/1 440spe MQ initialization

Dear Stefan Roese,

Quoted 4 lines · In message <[email protected]> you wrote:

So it seems that the current code relies on some already preset (default) values in those registers. I don't really like this. I'll try to provide a patch that configures those registers completely in a short while.

"In a short while" means very few hours? If Yuri is sopposed to test this, we have little time left. The release is scheduled for tomorrow.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When the bosses talk about improving  productivity,  they  are  never
talking about themselves.

Stefan Roese

2008-10-17 10:47 UTC #15 lore raw

PATCH 1/1 440spe MQ initialization

Hi Wolfgang,

Quoted 5 lines · Wolfgang Denk

Quoted 3 lines
So it seems that the current code relies on some already preset (default) values in those registers. I don't really like this. I'll try to provide a patch that configures those registers completely in a short while.
"In a short while" means very few hours?

Yes. I already tested with Yuri's patch and it doesn't change the resulting register values. So the current code already sets the correct values, it just doesn't set all bits explicitly. I'll provide another patch in a few minutes to set these bits explicitly, since this makes it clearer which bits are really configured.

Quoted 3 lines

If Yuri is sopposed to test
this, we have little time left. The release is scheduled for tomorrow.

Understood. He can test with the current U-Boot version without setting the MQ registers in the DMA/RAID Linux driver.

Best regards,
Stefan