Add R8A7743/SK-RZG1M board support
Subsystems (6)
v2 cover Add R8A7743/SK-RZG1M board support
Hello.
Here's the set of 12 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20160926-v4.8-rc8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. This version includes the Ether, so the board should boot with NFS root now. I tried to address all the comments to the version 1 (except the need to use the new CPG/MSSR drivers -- this one will be addressed RSN). The DMAC/SCIF/IRQC bindings patches posted recently are needed for scripts/checkpatch.pl to be happy. :-)
[1/12] ARM: shmobile: r8a7743: add clock index macros [2/12] ARM: shmobile: r8a7743: add power domain index macros [3/12] soc: renesas: rcar-sysc: add R8A7743 support [4/12] ARM: shmobile: r8a7743: basic SoC support [5/12] ARM: dts: r8a7743: initial SoC device tree [6/12] ARM: dts: r8a7743: add SYS-DMAC support [7/12] ARM: dts: r8a7743: add [H]SCIF[AB] support [8/12] ARM: dts: r8a7743: add Ether support
[9/12] ARM: dts: r8a7743: add IRQC support
[10/12] DT: arm: shmobile: document SK-RZG1M board [11/12] ARM: dts: sk-rzg1m: initial device tree [12/12] ARM: dts: sk-rzg1m: add Ether support
WBR, Sergei
RFC PATCH v2 1/12 ARM: shmobile: r8a7743: add clock index macros
Add macros usable by the device tree sources to reference the R8A7743 clocks by index.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- fixed the file copyright.
include/dt-bindings/clock/r8a7743-clock.h | 157 ++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+)
include/dt-bindings/clock/r8a7743-clock.h new file +157 -0
@@ -0,0 +1,157 @@ +/* +* Copyright (C) 2016 Cogent Embedded Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#ifndef __DT_BINDINGS_CLOCK_R8A7743_H__ +#define __DT_BINDINGS_CLOCK_R8A7743_H__ + +/* CPG */ +#define R8A7743_CLK_MAIN 0 +#define R8A7743_CLK_PLL0 1 +#define R8A7743_CLK_PLL1 2 +#define R8A7743_CLK_PLL3 3 +#define R8A7743_CLK_LB 4 +#define R8A7743_CLK_QSPI 5 +#define R8A7743_CLK_SDH 6 +#define R8A7743_CLK_SD0 7 +#define R8A7743_CLK_Z 8 +#define R8A7743_CLK_RCAN 9 + +/* MSTP0 */ +#define R8A7743_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7743_CLK_VCP0 1 +#define R8A7743_CLK_VPC0 3 +#define R8A7743_CLK_TMU1 11 +#define R8A7743_CLK_3DG 12 +#define R8A7743_CLK_2DDMAC 15 +#define R8A7743_CLK_FDP1_1 18 +#define R8A7743_CLK_FDP1_0 19 +#define R8A7743_CLK_TMU3 21 +#define R8A7743_CLK_TMU2 22 +#define R8A7743_CLK_CMT0 24 +#define R8A7743_CLK_TMU0 25 +#define R8A7743_CLK_VSP1_DU1 27 +#define R8A7743_CLK_VSP1_DU0 28 +#define R8A7743_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7743_CLK_SCIFA2 2 +#define R8A7743_CLK_SCIFA1 3 +#define R8A7743_CLK_SCIFA0 4 +#define R8A7743_CLK_MSIOF2 5 +#define R8A7743_CLK_SCIFB0 6 +#define R8A7743_CLK_SCIFB1 7 +#define R8A7743_CLK_MSIOF1 8 +#define R8A7743_CLK_SCIFB2 16 +#define R8A7743_CLK_SYS_DMAC1 18 +#define R8A7743_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7743_CLK_TPU0 4 +#define R8A7743_CLK_SDHI2 11 +#define R8A7743_CLK_SDHI1 12 +#define R8A7743_CLK_SDHI0 14 +#define R8A7743_CLK_MMCIF0 15 +#define R8A7743_CLK_IIC0 18 +#define R8A7743_CLK_PCIEC 19 +#define R8A7743_CLK_IIC1 23 +#define R8A7743_CLK_SSUSB 28 +#define R8A7743_CLK_CMT1 29 +#define R8A7743_CLK_USBDMAC0 30 +#define R8A7743_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7743_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7743_CLK_AUDIO_DMAC1 1 +#define R8A7743_CLK_AUDIO_DMAC0 2 +#define R8A7743_CLK_THERMAL 22 +#define R8A7743_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7743_CLK_EHCI 3 +#define R8A7743_CLK_HSUSB 4 +#define R8A7743_CLK_HSCIF2 13 +#define R8A7743_CLK_SCIF5 14 +#define R8A7743_CLK_SCIF4 15 +#define R8A7743_CLK_HSCIF1 16 +#define R8A7743_CLK_HSCIF0 17 +#define R8A7743_CLK_SCIF3 18 +#define R8A7743_CLK_SCIF2 19 +#define R8A7743_CLK_SCIF1 20 +#define R8A7743_CLK_SCIF0 21 +#define R8A7743_CLK_DU1 23 +#define R8A7743_CLK_DU0 24 +#define R8A7743_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7743_CLK_IPMMU_SGX 0 +#define R8A7743_CLK_VIN2 9 +#define R8A7743_CLK_VIN1 10 +#define R8A7743_CLK_VIN0 11 +#define R8A7743_CLK_ETHER 13 +#define R8A7743_CLK_SATA1 14 +#define R8A7743_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7743_CLK_GPIO7 4 +#define R8A7743_CLK_GPIO6 5 +#define R8A7743_CLK_GPIO5 7 +#define R8A7743_CLK_GPIO4 8 +#define R8A7743_CLK_GPIO3 9 +#define R8A7743_CLK_GPIO2 10 +#define R8A7743_CLK_GPIO1 11 +#define R8A7743_CLK_GPIO0 12 +#define R8A7743_CLK_RCAN1 15 +#define R8A7743_CLK_RCAN0 16 +#define R8A7743_CLK_QSPI_MOD 17 +#define R8A7743_CLK_I2C5 25 +#define R8A7743_CLK_IICDVFS 26 +#define R8A7743_CLK_I2C4 27 +#define R8A7743_CLK_I2C3 28 +#define R8A7743_CLK_I2C2 29 +#define R8A7743_CLK_I2C1 30 +#define R8A7743_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7743_CLK_SSI_ALL 5 +#define R8A7743_CLK_SSI9 6 +#define R8A7743_CLK_SSI8 7 +#define R8A7743_CLK_SSI7 8 +#define R8A7743_CLK_SSI6 9 +#define R8A7743_CLK_SSI5 10 +#define R8A7743_CLK_SSI4 11 +#define R8A7743_CLK_SSI3 12 +#define R8A7743_CLK_SSI2 13 +#define R8A7743_CLK_SSI1 14 +#define R8A7743_CLK_SSI0 15 +#define R8A7743_CLK_SCU_ALL 17 +#define R8A7743_CLK_SCU_DVC1 18 +#define R8A7743_CLK_SCU_DVC0 19 +#define R8A7743_CLK_SCU_CTU1_MIX1 20 +#define R8A7743_CLK_SCU_CTU0_MIX0 21 +#define R8A7743_CLK_SCU_SRC9 22 +#define R8A7743_CLK_SCU_SRC8 23 +#define R8A7743_CLK_SCU_SRC7 24 +#define R8A7743_CLK_SCU_SRC6 25 +#define R8A7743_CLK_SCU_SRC5 26 +#define R8A7743_CLK_SCU_SRC4 27 +#define R8A7743_CLK_SCU_SRC3 28 +#define R8A7743_CLK_SCU_SRC2 29 +#define R8A7743_CLK_SCU_SRC1 30 +#define R8A7743_CLK_SCU_SRC0 31 + +/* MSTP11 */ +#define R8A7743_CLK_SCIFA3 6 +#define R8A7743_CLK_SCIFA4 7 +#define R8A7743_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7743_H__ */
A message that is not in the archive (sent off-list or not yet received): 1987532.PE2ex6PrJ5-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org
RFC PATCH v2 2/12 ARM: shmobile: r8a7743: add power domain index macros
Add macros usable by the device tree sources to reference R8A7743 SYSC power domains by index.
Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin-M4DtvfQ/[email protected]>.
---
Changes in version 2:
- added Geert's tag.
include/dt-bindings/power/r8a7743-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
include/dt-bindings/power/r8a7743-sysc.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2016 Cogent Embedded Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ +#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ + +/* +* These power domain indices match the numbers of the interrupt bits +* representing the power areas in the various Interrupt Registers +* (e.g. SYSCISR, Interrupt Status Register) +*/ + +#define R8A7743_PD_CA15_CPU0 0 +#define R8A7743_PD_CA15_CPU1 1 +#define R8A7743_PD_CA15_SCU 12 +#define R8A7743_PD_SGX 20 + +/* Always-on power area */ +#define R8A7743_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */
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RFC PATCH v2 10/12 DT: arm: shmobile: document SK-RZG1M board
In reply to a message not in the archiveDocument the SK-RZG1M device tree bindings, listing it as a supported board.
This allows to use checkpatch.pl to validate .dts files referring to the SK-RZG1M board.
---
Changes in version 2:
- new patch.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/arm/shmobile.txt +2 -0
@@ -75,5 +75,7 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" + - SK-RZG1M (YR8A77430S000BE) + compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Wheat compatible = "renesas,wheat", "renesas,r8a7792"
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Re: [PATCH RFC v2 10/12] DT: arm: shmobile: document SK-RZG1M board
Quoted 6 lines · Sergei Shtylyov
Document the SK-RZG1M device tree bindings, listing it as a supported board.
This allows to use checkpatch.pl to validate .dts files referring to the SK-RZG1M board.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RFC PATCH v2 3/12 soc: renesas: rcar-sysc: add R8A7743 support
In reply to Sergei ShtylyovAdd support for RZ/G1M (R8A7743) SoC power areas to the R-Car SYSC driver.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- documented the R8A7743 SYSC device tree binding;
- added "R-Car" to the patch description;
- added Geert's tag.
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 7 +- drivers/soc/renesas/Makefile | 1 drivers/soc/renesas/r8a7743-sysc.c | 32 ++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 drivers/soc/renesas/rcar-sysc.h | 1 5 files changed, 41 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +4 -3
@@ -1,12 +1,13 @@ -DT bindings for the Renesas R-Car System Controller +DT bindings for the Renesas R-Car (RZ/G) System Controller == System Controller Node == -The R-Car System Controller provides power management for the CPU cores and -various coprocessors. +The R-Car (RZ/G) System Controller provides power management for the CPU cores +and various coprocessors. Required properties: - compatible: Must contain exactly one of the following: + - "renesas,r8a7743-sysc" (RZ/G1M) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) - "renesas,r8a7791-sysc" (R-Car M2-W)
drivers/soc/renesas/Makefile +1 -0
@@ -1,3 +1,4 @@ +obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o
drivers/soc/renesas/r8a7743-sysc.c new file +32 -0
@@ -0,0 +1,32 @@ +/* +* Renesas RZ/G1M System Controller +* +* Copyright (C) 2016 Cogent Embedded Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation; of the License. +*/ + +#include <linux/bug.h> +#include <linux/kernel.h> + +#include <dt-bindings/power/r8a7743-sysc.h> + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a7743_areas[]__initconst = { + {"always-on" ,0 ,0 ,R8A7743_PD_ALWAYS_ON ,-1 ,PD_ALWAYS_ON }, + {"ca15-scu" ,0x180 ,0 ,R8A7743_PD_CA15_SCU ,R8A7743_PD_ALWAYS_ON , +PD_SCU }, + {"ca15-cpu0" ,0x40 ,0 ,R8A7743_PD_CA15_CPU0 ,R8A7743_PD_CA15_SCU , +PD_CPU_NOCR }, + {"ca15-cpu1" ,0x40 ,1 ,R8A7743_PD_CA15_CPU1 ,R8A7743_PD_CA15_SCU , +PD_CPU_NOCR }, + {"sgx" ,0xc0 ,0 ,R8A7743_PD_SGX ,R8A7743_PD_ALWAYS_ON }, +}; + +const struct rcar_sysc_info r8a7743_sysc_info__initconst = { + .areas = r8a7743_areas, + .num_areas =ARRAY_SIZE (r8a7743_areas), +};
drivers/soc/renesas/rcar-sysc.c +3 -0
@@ -275,6 +275,9 @@ finalize: }static const struct of_device_id rcar_sysc_matches[] = { +#ifdef CONFIG_ARCH_R8A7743 + { .compatible ="renesas,r8a7743-sysc" , .data = &r8a7743_sysc_info }, +#endif #ifdef CONFIG_ARCH_R8A7779 { .compatible ="renesas,r8a7779-sysc" , .data = &r8a7779_sysc_info }, #endif
drivers/soc/renesas/rcar-sysc.h +1 -0
@@ -50,6 +50,7 @@ struct rcar_sysc_info {unsigned int num_areas; }; +extern const struct rcar_sysc_info r8a7743_sysc_info;extern const struct rcar_sysc_info r8a7779_sysc_info;extern const struct rcar_sysc_info r8a7790_sysc_info;extern const struct rcar_sysc_info r8a7791_sysc_info;
RFC PATCH v2 4/12 ARM: shmobile: r8a7743: basic SoC support
In reply to Sergei ShtylyovAdd minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- removed "select I2C" from the R8A7743 Kconfig entry;
- documented the R8A7743 device tree binding;
- added Geert's tag.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 + arch/arm/mach-shmobile/Kconfig | 4 ++ arch/arm/mach-shmobile/Makefile | 1 arch/arm/mach-shmobile/setup-r8a7743.c | 34 +++++++++++++++++++++ 4 files changed, 41 insertions(+)
Documentation/devicetree/bindings/arm/shmobile.txt +2 -0
@@ -13,6 +13,8 @@ SoCs: compatible = "renesas,r8a73a4" - R-Mobile A1 (R8A77400) compatible = "renesas,r8a7740" + - RZ/G1M (R8A77430) + compatible = "renesas,r8a7743" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790)
arch/arm/mach-shmobile/Kconfig +4 -0
@@ -68,6 +68,10 @@ config ARCH_R8A7740 select ARCH_RMOBILE select RENESAS_INTC_IRQPIN +config ARCH_R8A7743 + bool "RZ/G1M (R8A77430)" + select ARCH_RCAR_GEN2 + config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1
arch/arm/mach-shmobile/Makefile +1 -0
@@ -9,6 +9,7 @@ obj-y := timer.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o +obj-$(CONFIG_ARCH_R8A7743) += setup-r8a7743.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
arch/arm/mach-shmobile/setup-r8a7743.c new file +34 -0
@@ -0,0 +1,34 @@ +/* +* r8a7743 processor support +* +* Copyright (C) 2016 Cogent Embedded, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation; of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/init.h> + +#include <asm/mach/arch.h> + +#include "common.h" +#include "rcar-gen2.h" + +static const char *const r8a7743_boards_compat_dt[]__initconst = { +"renesas,r8a7743" , +NULL , +}; + +DT_MACHINE_START (R8A7743_DT ,"Generic R8A7743 (Flattened Device Tree)" ) + .init_early = shmobile_init_delay, + .init_time = rcar_gen2_timer_init, + .init_late = shmobile_init_late, + .reserve = rcar_gen2_reserve, + .dt_compat = r8a7743_boards_compat_dt, +MACHINE_END
RFC PATCH v2 4/12 ARM: shmobile: r8a7743: basic SoC support
Hi Sergei,
Thank you for the patch.
Quoted 14 lines · On Friday 30 Sep 2016 01:23:52 Sergei Shtylyov wrote:
Add minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>---
Changes in version 2:
- removed "select I2C" from the R8A7743Kconfigentry;
- documented the R8A7743 device tree binding;
- added Geert's tag.
Quoted 4 lines
Documentation/devicetree/bindings/arm/shmobile.txt | 2 + arch/arm/mach-shmobile/Kconfig | 4 ++ arch/arm/mach-shmobile/Makefile | 1 arch/arm/mach-shmobile/setup-r8a7743.c | 34 +++++++++++++++++
We should work towards removing files from arch/arm/mach-shmobile/, not adding new ones :-) I've just sent a patch to do so ("[PATCH] ARM: shmobile:
Consolidate R8A779[234] machine definitions'") and CC'ed you.
Quoted 81 lines
4 files changed, 41 insertions(+)Index:
renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===================================================================Documentation/devicetree/bindings/arm/shmobile.txt +2
-0@@ -13,6 +13,8 @@ SoCs: compatible = "renesas,r8a73a4" - R-Mobile A1 (R8A77400) compatible = "renesas,r8a7740" + - RZ/G1M (R8A77430) + compatible = "renesas,r8a7743" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790)Index: renesas/arch/arm/mach-shmobile/Kconfig
===================================================================arch/arm/mach-shmobile/Kconfig +4
-0@@ -68,6 +68,10 @@ config ARCH_R8A7740 select ARCH_RMOBILE select RENESAS_INTC_IRQPIN +config ARCH_R8A7743 + bool "RZ/G1M (R8A77430)" + select ARCH_RCAR_GEN2 + config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1Index: renesas/arch/arm/mach-shmobile/Makefile
===================================================================arch/arm/mach-shmobile/Makefile +1
-0@@ -9,6 +9,7 @@ obj-y := timer.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o +obj-$(CONFIG_ARCH_R8A7743) += setup-r8a7743.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.oIndex:
renesas/arch/arm/mach-shmobile/setup-r8a7743.c
===================================================================arch/arm/mach-shmobile/setup-r8a7743.c new file +34
-0@@ -0,0 +1,34 @@ +/* +* r8a7743 processor support +* +* Copyright (C) 2016 Cogent Embedded, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation; of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/init.h> + +#include <asm/mach/arch.h> + +#include "common.h" +#include "rcar-gen2.h" + +static const char *const r8a7743_boards_compat_dt[]__initconst = { +"renesas,r8a7743" , +NULL , +}; + +DT_MACHINE_START (R8A7743_DT ,"Generic R8A7743 (Flattened Device Tree)" ) + .init_early = shmobile_init_delay, + .init_time = rcar_gen2_timer_init, + .init_late = shmobile_init_late, + .reserve = rcar_gen2_reserve, + .dt_compat = r8a7743_boards_compat_dt, +MACHINE_END
Signature · 3 lines
Regards, Laurent Pinchart
RFC PATCH v2 5/12 ARM: dts: r8a7743: initial SoC device tree
In reply to Sergei ShtylyovThe initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- added the IRQC and Ether clocks.
arch/arm/boot/dts/r8a7743.dtsi | 235 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 235 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi new file +235 -0
@@ -0,0 +1,235 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a7743-clock.h> +#include <dt-bindings/power/r8a7743-sysc.h> + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg_clocks R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller at f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + sysc: system-controller at e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks at e6150000 { + compatible = "renesas,r8a7743-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk &usb_extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z", + "rcan"; + #power-domain-cells = <0>; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + zs_clk: zs { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + p_clk: p { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + }; + mp_clk: mp { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks at e6150138 { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7743_CLK_SCIFA2 R8A7743_CLK_SCIFA1 + R8A7743_CLK_SCIFA0 R8A7743_CLK_SCIFB0 + R8A7743_CLK_SCIFB1 R8A7743_CLK_SCIFB2 + R8A7743_CLK_SYS_DMAC1 R8A7743_CLK_SYS_DMAC0 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", + "scifb0", "scifb1", "scifb2", + "sys-dmac1", "sys-dmac0"; + }; + mstp4_clks: mstp4_clks at e6150140 { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = <R8A7743_CLK_IRQC>; + clock-output-names = "irqc"; + }; + mstp7_clks: mstp7_clks at e615014c { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7743_CLK_HSCIF2 R8A7743_CLK_SCIF5 + R8A7743_CLK_SCIF4 R8A7743_CLK_HSCIF1 + R8A7743_CLK_HSCIF0 R8A7743_CLK_SCIF3 + R8A7743_CLK_SCIF2 R8A7743_CLK_SCIF1 + R8A7743_CLK_SCIF0 + >; + clock-output-names = + "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "scif3", "scif2", "scif1", "scif0"; + }; + mstp8_clks: mstp8_clks at e6150990 { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + clock-indices = <R8A7743_CLK_ETHER>; + clock-output-names = "ether"; + }; + mstp11_clks: mstp11_clks at e615099c { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7743_CLK_SCIFA3 R8A7743_CLK_SCIFA4 + R8A7743_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +};
RFC PATCH v2 6/12 ARM: dts: r8a7743: add SYS-DMAC support
In reply to Sergei ShtylyovDescribe SYS-DMAC0/1 in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7743.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +64 -0
@@ -90,6 +90,70 @@ #power-domain-cells = <1>; }; + dmac0: dma-controller at e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller at e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks at e6150000 { compatible = "renesas,r8a7743-cpg-clocks",
RFC PATCH v2 7/12 ARM: dts: r8a7743: add [H]SCIF[AB] support
In reply to Sergei ShtylyovDescribe [H]SCIF[AB] ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- used the new RZ/G family "compatible" prop values, reformatting where needed;
- fixed the size cells of the SCIFB device nodes' "reg" properties;
- changed the size cells of the "reg" properties to hexadecimal;
- indented the SCIFA1 device node's closing brace correctly
- adjusted the patch description, renamed the patch.
arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +261 -0
@@ -154,6 +154,267 @@ dma-channels = <15>; }; + scifa0: serial at e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA0>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial at e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA1>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial at e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA2>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial at e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA3>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial at e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA4>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial at e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA5>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial at e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFB0>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial at e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFB1>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial at e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFB2>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial at e6e60000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial at e6e68000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial at e6e58000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial at e6ea8000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF3>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial at e6ee0000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF4>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial at e6ee8000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF5>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial at e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_HSCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial at e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_HSCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial at e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_HSCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks at e6150000 { compatible = "renesas,r8a7743-cpg-clocks",
RFC PATCH v2 8/12 ARM: dts: r8a7743: add Ether support
In reply to Sergei ShtylyovDefine the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +12 -0
@@ -415,6 +415,18 @@ status = "disabled"; }; + ether: ethernet at ee700000 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7743_CLK_ETHER>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks at e6150000 { compatible = "renesas,r8a7743-cpg-clocks",
RFC PATCH v2 9/12 ARM: dts: r8a7743: add IRQC support
In reply to Sergei ShtylyovDescribe the IRQC interrupt controller in the R8A7743 device tree.
---
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +19 -0
@@ -72,6 +72,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller at e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7743_CLK_IRQC>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
RFC PATCH v2 11/12 ARM: dts: sk-rzg1m: initial device tree
In reply to Sergei ShtylyovAdd the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
--- arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)
arch/arm/boot/dts/Makefile +1 -0
@@ -654,6 +654,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts new file +44 -0
44 lines not on this page · raw message
RFC PATCH v2 11/12 ARM: dts: sk-rzg1m: initial device tree
Quoted 8 lines · Sergei Shtylyov
Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RFC PATCH v2 12/12 ARM: dts: sk-rzg1m: add Ether support
In reply to Sergei ShtylyovDefine the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +14 -1
@@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; };
@@ -42,3 +42,16 @@ &scif0 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy at 1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +};
v2 cover Add R8A7743/SK-RZG1M board support
In reply to Sergei ShtylyovHi Sergei,
Quoted 7 lines · Sergei Shtylyov
Here's the set of 12 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20160926-v4.8-rc8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. This version includes the Ether, so the board should boot with NFS root now. I tried to address all the comments to the version 1 (except the need to use the new CPG/MSSR drivers -- this one will be addressed RSN). The DMAC/SCIF/IRQC bindings patches posted recently are
There's an (old) version of an r8a7791 CPG/MSSR driver at
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/cpg-mssr-v4
To handle it cleanly, this is going to need "[PATCH/RFC v3 00/22] soc:
renesas: Add R-Car RST driver for obtaining mode pin state"...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds