qcom/sc7280: Enable various hardware blocks on SC7280 SoC
Subsystems (6)
cover qcom/sc7280: Enable various hardware blocks on SC7280 SoC
This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
[1] https://lore.kernel.org/patchwork/cover/1379842/
Sai Prakash Ranjan (9):
dt-bindings: arm: msm: Add LLCC for SC7280
soc: qcom: llcc: Add configuration data for SC7280
arm64: dts: qcom: sc7280: Add device tree node for LLCC
dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
dt-bindings: soc: qcom: aoss: Add SC7280 compatible
soc: qcom: aoss: Add AOSS QMP support for SC7280
arm64: dts: qcom: sc7280: Add AOSS QMP node
arm64: dts: qcom: sc7280: Add Coresight support
.../bindings/arm/msm/qcom,llcc.yaml | 1 + .../bindings/mailbox/qcom-ipcc.yaml | 1 + .../bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 520 ++++++++++++++++++ drivers/soc/qcom/llcc-qcom.c | 19 + drivers/soc/qcom/qcom_aoss.c | 1 + 6 files changed, 543 insertions(+)
base-commit: d79b47c59576a51d8e288a6b98b75ccf4afb8acd
prerequisite-patch-id: d8babdd3c8a9923360af342f3d8d9876820272e5
prerequisite-patch-id: 5757e07e4336d773d402769d09106924962ce31b
prerequisite-patch-id: 9b21eb51aa86619f5695a511c65c9236e3bc0f2b
prerequisite-patch-id: 2f834cc892f7f9109cbf32a87d504ba27b64a5df
prerequisite-patch-id: 14b1185357703d750c3411a16e97675489ca7dde
prerequisite-patch-id: 55c143f21b646c18da921a62bbd2801a5df38c8f
prerequisite-patch-id: 66f4c58aff2f1a7283b0103590ff82384907bae3
prerequisite-patch-id: 75e73e6b13ab91ed5e3a96b59957aa5e867d65ea
prerequisite-patch-id: eb46845b4f9eb3706a26911042c2865a58577198
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH 1/9 dt-bindings: arm: msm: Add LLCC for SC7280
Add LLCC compatible for SC7280 SoC.
--- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +1 -0
@@ -22,6 +22,7 @@ properties: compatible: enum: - qcom,sc7180-llcc + - qcom,sc7280-llcc - qcom,sdm845-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 1/9] dt-bindings: arm: msm: Add LLCC for SC7280
Quoting Sai Prakash Ranjan (2021-02-25 01:30:17)
Quoted 4 lines
Add LLCC compatible for SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 1/9] dt-bindings: arm: msm: Add LLCC for SC7280
In reply to Sai Prakash RanjanQuoted 7 lines · Sai Prakash Ranjan
Add LLCC compatible for SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+)
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 2/9 soc: qcom: llcc: Add configuration data for SC7280
In reply to Sai Prakash RanjanAdd LLCC configuration data for SC7280 SoC.
--- drivers/soc/qcom/llcc-qcom.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
drivers/soc/qcom/llcc-qcom.c +19 -0
@@ -109,6 +109,18 @@ static const struct llcc_slice_config sc7180_data[] = { { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, }; +static const struct llcc_slice_config sc7280_data[] = { + {LLCC_CPUSS ,1 ,768 ,1 ,0 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,1 ,0 }, + {LLCC_MDMHPGRW ,7 ,512 ,2 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, + {LLCC_CMPT ,10 ,768 ,1 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, + {LLCC_GPUHTW ,11 ,256 ,1 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, + {LLCC_GPU ,12 ,512 ,1 ,0 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, + {LLCC_MMUHWT ,13 ,256 ,1 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,1 ,0 }, + {LLCC_MDMPNG ,21 ,768 ,0 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, + {LLCC_WLHW ,24 ,256 ,1 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, + {LLCC_MODPE ,29 ,64 ,1 ,1 ,0x3f ,0x0 ,0 ,0 ,0 ,1 ,0 ,0 }, +}; +static const struct llcc_slice_config sdm845_data[] = { {LLCC_CPUSS ,1 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,1 }, { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
@@ -179,6 +191,12 @@ static const struct qcom_llcc_config sc7180_cfg = { .need_llcc_cfg = true, }; +static const struct qcom_llcc_config sc7280_cfg = { + .sct_data = sc7280_data, + .size =ARRAY_SIZE (sc7280_data), + .need_llcc_cfg = true, +}; +static const struct qcom_llcc_config sdm845_cfg = { .sct_data = sdm845_data, .size =ARRAY_SIZE (sdm845_data),
@@ -606,6 +624,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)static const struct of_device_id qcom_llcc_of_match[] = { { .compatible ="qcom,sc7180-llcc" , .data = &sc7180_cfg }, + { .compatible ="qcom,sc7280-llcc" , .data = &sc7280_cfg }, { .compatible ="qcom,sdm845-llcc" , .data = &sdm845_cfg }, { .compatible ="qcom,sm8150-llcc" , .data = &sm8150_cfg }, { .compatible ="qcom,sm8250-llcc" , .data = &sm8250_cfg },
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH 3/9 arm64: dts: qcom: sc7280: Add device tree node for LLCC
In reply to Sai Prakash RanjanAdd a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC.
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +7 -0
@@ -338,6 +338,13 @@ uart5: serial@994000 { }; }; + system-cache-controller@9200000 { + compatible = "qcom,sc7280-llcc"; + reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0xb220000 0 0x30000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Quoted 6 lines
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
Should add system-cache-controller to the devicetree spec. Or just use cache-controller for the node name.
Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC
Quoted 5 lines · Stephen Boyd
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Quoted 4 lines
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC.
Quoted 7 lines
Quoted 2 lines
Signed-off-by Sai Prakash Ranjan <[email protected]>---
Reviewed-by Stephen Boyd <[email protected]>Should add system-cache-controller to the devicetree spec. Or just use cache-controller for the node name.
This was as per discussion in [1][2] where dt-schema throws an error since it expects cache-level to be associated with cache-controller.
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
Quoted 9 lines · Stephen Boyd
Quoted 8 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Quoted 6 lines
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
Quoted 8 lines
Quoted 4 lines
Reviewed-by Stephen Boyd <[email protected]>Should add system-cache-controller to the devicetree spec. Or just use cache-controller for the node name.
This was as per discussion in [1][2] where dt-schema throws an error since it expects cache-level to be associated with cache-controller.
Ah right. Can you add system-cache-controller to the dt spec?
Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC
Quoted 12 lines · Stephen Boyd
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
Quoted 11 lines · Stephen Boyd
Quoted 10 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Quoted 6 lines
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
Reviewed-by Stephen Boyd <[email protected]>
Quoted 8 lines
Quoted 6 lines
Quoted 2 lines
Should add system-cache-controller to the devicetree spec. Or just use cache-controller for the node name.
This was as per discussion in [1][2] where dt-schema throws an error since it expects cache-level to be associated with cache-controller.
Ah right. Can you add system-cache-controller to the dt spec?
Sure, I'll add it. Hopefully that won't have to block this change? Because I might need some time to get permissions to add it there.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC
Quoting Sai Prakash Ranjan (2021-02-27 05:58:25)
Quoted 16 lines · Stephen Boyd
Quoted 15 lines
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
Quoted 14 lines · Stephen Boyd
Quoted 12 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Quoted 6 lines
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
Reviewed-by Stephen Boyd <[email protected]>Should add system-cache-controller to the devicetree spec. Or just use cache-controller for the node name.
Quoted 9 lines
Quoted 5 lines
Quoted 3 lines
This was as per discussion in [1][2] where dt-schema throws an error since it expects cache-level to be associated with cache-controller.
Ah right. Can you add system-cache-controller to the dt spec?
Sure, I'll add it. Hopefully that won't have to block this change? Because I might need some time to get permissions to add it there.
Doesn't block it for me.
PATCH 4/9 dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
In reply to Sai Prakash RanjanAdd IPCC compatible for SC7280 SoC.
--- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +1 -0
@@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,sc7280-ipcc - qcom,sm8250-ipcc - const: qcom,ipcc
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 4/9] dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
Quoted 4 lines · Sai Prakash Ranjan
Add IPCC compatible for SC7280 SoC.
Cc Manivannan Sadhasivam <[email protected]>Signed-off-by Sai Prakash Ranjan <[email protected]>
Thanks,
Mani
Quoted 20 lines
--- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +1
-0@@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,sc7280-ipcc - qcom,sm8250-ipcc - const: qcom,ipccSignature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 4/9] dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
In reply to Sai Prakash RanjanQuoting Sai Prakash Ranjan (2021-02-25 01:30:20)
Quoted 5 lines
Add IPCC compatible for SC7280 SoC.
Cc Manivannan Sadhasivam <[email protected]>Signed-off-by Sai Prakash Ranjan <[email protected]>---
PATCH 5/9 arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
In reply to Sai Prakash RanjanAdd the IPCC DT node which is used to send and receive IPC signals with remoteprocs for SC7280 SoC.
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +10 -0
@@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {
@@ -315,6 +316,15 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/9] arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
Quoted 5 lines · Sai Prakash Ranjan
Add the IPCC DT node which is used to send and receive IPC signals with remoteprocs for SC7280 SoC.
Cc Manivannan Sadhasivam <[email protected]>Signed-off-by Sai Prakash Ranjan <[email protected]>
Thanks,
Mani
Quoted 36 lines
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0@@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {@@ -315,6 +316,15 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>;Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/9] arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
In reply to Sai Prakash RanjanQuoting Sai Prakash Ranjan (2021-02-25 01:30:21)
Quoted 6 lines
Add the IPCC DT node which is used to send and receive IPC signals with remoteprocs for SC7280 SoC.
Cc Manivannan Sadhasivam <[email protected]>Signed-off-by Sai Prakash Ranjan <[email protected]>---
PATCH 6/9 dt-bindings: soc: qcom: aoss: Add SC7280 compatible
In reply to Sai Prakash RanjanAdd SC7280 AOSS QMP compatible to the list of possible bindings.
--- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt +1 -0
@@ -17,6 +17,7 @@ power-domains. Value type: <string> Definition: must be one of: "qcom,sc7180-aoss-qmp" + "qcom,sc7280-aoss-qmp" "qcom,sdm845-aoss-qmp" "qcom,sm8150-aoss-qmp" "qcom,sm8250-aoss-qmp"
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 6/9] dt-bindings: soc: qcom: aoss: Add SC7280 compatible
Quoting Sai Prakash Ranjan (2021-02-25 01:30:22)
Quoted 4 lines
Add SC7280 AOSS QMP compatible to the list of possible bindings.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
Re: [PATCH 6/9] dt-bindings: soc: qcom: aoss: Add SC7280 compatible
In reply to Sai Prakash RanjanQuoted 7 lines · Sai Prakash Ranjan
Add SC7280 AOSS QMP compatible to the list of possible bindings.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + 1 file changed, 1 insertion(+)
PATCH 7/9 soc: qcom: aoss: Add AOSS QMP support for SC7280
In reply to Sai Prakash RanjanAdd AOSS QMP support for SC7280 SoC.
--- drivers/soc/qcom/qcom_aoss.c | 1 + 1 file changed, 1 insertion(+)
drivers/soc/qcom/qcom_aoss.c +1 -0
@@ -597,6 +597,7 @@ static int qmp_remove(struct platform_device *pdev)static const struct of_device_id qmp_dt_match[] = { { .compatible ="qcom,sc7180-aoss-qmp" , }, + { .compatible ="qcom,sc7280-aoss-qmp" , }, { .compatible ="qcom,sdm845-aoss-qmp" , }, { .compatible ="qcom,sm8150-aoss-qmp" , }, { .compatible ="qcom,sm8250-aoss-qmp" , },
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 7/9] soc: qcom: aoss: Add AOSS QMP support for SC7280
Quoting Sai Prakash Ranjan (2021-02-25 01:30:23)
Quoted 4 lines
Add AOSS QMP support for SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>---
PATCH 8/9 arm64: dts: qcom: sc7280: Add AOSS QMP node
In reply to Sai Prakash RanjanAdd a DT node for the AOSS QMP on SC7280 SoC.
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +14 -0
@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {
@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sc7280-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 20 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 {
power-domain-controller@c300000? power-controller@c300000?
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 385
Quoted 13 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +12
-0+ compatible = "qcom,sc7280-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: qcom,spmi@c440000 {
Ick, should be spmi@
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 387
Quoted 2 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoted 19 lines · Stephen Boyd
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 18 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0/ {@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 {power-domain-controller@c300000? power-controller@c300000?
Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed?
Quoted 9 lines
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +4
-0+ compatible = "qcom,sc7280-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP +
IPCC_MPROC_SIGNAL_GLINK_QMP
+IRQ_TYPE_EDGE_RISING>;arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0+ mboxes = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>;
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 385
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: qcom,spmi@c440000 {Ick, should be spmi@
Not introduced by this patch but I'll pass on the comment.
Quoted 2 lines
Quoted 2 lines
compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
Quoted 26 lines · Stephen Boyd
Quoted 25 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 24 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; };
Quoted 8 lines
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 1 line
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0+ aoss_qmp: qmp@c300000 {power-domain-controller@c300000? power-controller@c300000?
Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed?
Node name should be generic while still being meaningful. Nobody knows what qmp is, but power-controller makes sense. Can you fix this and the others to be power-controller?
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoted 32 lines · Stephen Boyd
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
Quoted 31 lines · Stephen Boyd
Quoted 29 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 21 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 {power-domain-controller@c300000? power-controller@c300000?
Quoted 8 lines
Quoted 3 lines
Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed?
Node name should be generic while still being meaningful. Nobody knows what qmp is, but power-controller makes sense. Can you fix this and the others to be power-controller?
Ok makes sense, I will post changing others as well and see if we get any comments there.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoted 33 lines · Sai Prakash Ranjan
Quoted 32 lines · Stephen Boyd
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
Quoted 31 lines · Stephen Boyd
Quoted 29 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 21 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / {arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 {power-domain-controller@c300000? power-controller@c300000?
Quoted 8 lines
Quoted 8 lines
Quoted 3 lines
Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed?
Node name should be generic while still being meaningful. Nobody knows what qmp is, but power-controller makes sense. Can you fix this and the others to be power-controller?
we probably would be changing them back
to qmp or something more generic soon
since the consensus was qmp wasn't a
power-controller. So not sure if its
worth the effort here.
Quoted 6 lines
Ok makes sense, I will post changing others as well and see if we get any comments there.
Thanks,
Sai
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoting Sibi Sankar (2021-03-08 21:58:21)
Quoted 44 lines · Sai Prakash Ranjan
Quoted 37 lines · Stephen Boyd
Quoted 36 lines
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
Quoted 34 lines · Stephen Boyd
Quoted 20 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 19 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0/ {@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 {power-domain-controller@c300000? power-controller@c300000?
Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed?
Quoted 5 lines
Quoted 5 lines
Node name should be generic while still being meaningful. Nobody knows what qmp is, but power-controller makes sense. Can you fix this and the
others to be power-controller?
Quoted 6 lines
we probably would be changing them back to qmp or something more generic soon since the consensus was qmp wasn't a power-controller. So not sure if its worth the effort here.
Hmm alright. Maybe mailbox? qmp is not generic. What does it stand for? qualcomm messaging protocol?
Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node
Quoted 52 lines · Stephen Boyd
Quoting Sibi Sankar (2021-03-08 21:58:21)
Quoted 44 lines · Sai Prakash Ranjan
Quoted 37 lines · Stephen Boyd
Quoted 36 lines
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
Quoted 34 lines · Stephen Boyd
Quoted 20 lines
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Quoted 19 lines
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0@@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi pdc: interrupt-controller@b220000 { · line 372
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-0/ {@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: qmp@c300000 {power-domain-controller@c300000? power-controller@c300000?
Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed?
Quoted 5 lines
Quoted 5 lines
Node name should be generic while still being meaningful. Nobody knows what qmp is, but power-controller makes sense. Can you fix this and the
others to be power-controller?Quoted 6 lines
we probably would be changing them back to qmp or something more generic soon since the consensus was qmp wasn't a power-controller. So not sure if its worth the effort here.
Quoted 2 lines
Hmm alright. Maybe mailbox? qmp is not generic. What does it stand for? qualcomm messaging protocol?
It's documented as ^^ in the git log
but I guess it should be called qualcomm
mailbox protocol instead. I don't think
it can be called mailbox since it doesn't
have mbox cells in its bindings.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH 9/9 arm64: dts: qcom: sc7280: Add Coresight support
In reply to Sai Prakash RanjanAdd coresight components found on SC7280 SoC.
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 489 +++++++++++++++++++++++++++ 1 file changed, 489 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +489 -0
@@ -349,6 +349,495 @@ uart5: serial@994000 { }; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&swao_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&swao_replicator_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + iommus = <&apps_smmu 0x04c0 0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@6b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06b04000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + swao_funnel_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + }; + + etf@6b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b05000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&swao_replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&swao_funnel_out>; + }; + }; + }; + }; + + replicator@6b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06b06000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,replicator-loses-context; + + out-ports { + port { + swao_replicator_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + port { + swao_replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = <&funnel1_in4>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quoted 5 lines · Sai Prakash Ranjan
This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
I've picked some of these patches...
It would be helpful if you split series like this based on how they will be picked up my various maintainers. E.g. I think it's quite likely Jassi won't find and pick up the mailbox binding patch.
PS. I sent a patch to Jassi adding the mailbox binding directory to MAINTAINERS.
Regards,
Bjorn
Quoted 36 lines
[1] https://lore.kernel.org/patchwork/cover/1379842/
Sai Prakash Ranjan (9):
dt-bindings: arm: msm: Add LLCC for SC7280
soc: qcom: llcc: Add configuration data for SC7280
arm64: dts: qcom: sc7280: Add device tree node for LLCC
dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
dt-bindings: soc: qcom: aoss: Add SC7280 compatible
soc: qcom: aoss: Add AOSS QMP support for SC7280
arm64: dts: qcom: sc7280: Add AOSS QMP node
arm64: dts: qcom: sc7280: Add Coresight support.../bindings/arm/msm/qcom,llcc.yaml | 1 + .../bindings/mailbox/qcom-ipcc.yaml | 1 + .../bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 520 ++++++++++++++++++ drivers/soc/qcom/llcc-qcom.c | 19 + drivers/soc/qcom/qcom_aoss.c | 1 + 6 files changed, 543 insertions(+)base-commit:
d79b47c59576a51d8e288a6b98b75ccf4afb8acd
prerequisite-patch-id:d8babdd3c8a9923360af342f3d8d9876820272e5
prerequisite-patch-id:5757e07e4336d773d402769d09106924962ce31b
prerequisite-patch-id:9b21eb51aa86619f5695a511c65c9236e3bc0f2b
prerequisite-patch-id:2f834cc892f7f9109cbf32a87d504ba27b64a5df
prerequisite-patch-id:14b1185357703d750c3411a16e97675489ca7dde
prerequisite-patch-id:55c143f21b646c18da921a62bbd2801a5df38c8f
prerequisite-patch-id:66f4c58aff2f1a7283b0103590ff82384907bae3
prerequisite-patch-id:75e73e6b13ab91ed5e3a96b59957aa5e867d65ea
prerequisite-patch-id:eb46845b4f9eb3706a26911042c2865a58577198Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quoted 11 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan
This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
I've picked some of these patches...
Quoted 8 lines
It would be helpful if you split series like this based on how they will be picked up my various maintainers. E.g. I think it's quite likely Jassi won't find and pick up the mailbox binding patch.
PS. I sent a patch to Jassi adding the mailbox binding directory to
MAINTAINERS.
Sure I will group patches(mainly dt-bindings for other subsystems) accordingly.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation