ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

PATCH Superseded Heiko Stübner 6 participants 16 messages Dec 10, 2013 – Jan 10, 2014

Subsystems (6)

Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +2 more subsystems

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Heiko Stübner

author

2013-12-10 15:14 UTC #0 lore raw

v4 cover ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

Next try, this time with less time between submissions.

Tested on both non-dt and dt s3c2416.

Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs Changes since v2
- address comments from Tomasz Figa
- use new pll registration mechanism
- use fixed-rate clocks for xti etc

Heiko Stuebner (7):
clk: samsung: add pll_6552 variant for s3c2416
clk: samsung: add plls used by the s3c2443
dt-bindings: add binding for clock-controller of s3c2443 and following
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
ARM: dt: add clock data for s3c2416
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

 .../bindings/clock/samsung,s3c2443-clock.txt       |   56 ++
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |   13 +
 arch/arm/boot/dts/s3c2416.dtsi                     |   42 ++
 arch/arm/mach-s3c24xx/Kconfig                      |   18 +-
 arch/arm/mach-s3c24xx/Makefile                     |    5 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |  171 -----
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |  212 ------
 arch/arm/mach-s3c24xx/common-s3c2443.c             |  675 --------------------
 arch/arm/mach-s3c24xx/common.c                     |   18 +-
 arch/arm/mach-s3c24xx/common.h                     |    6 +
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c            |   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |    9 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-pll.c                      |   84 ++-
 drivers/clk/samsung/clk-pll.h                      |    3 +
 drivers/clk/samsung/clk-s3c2443.c                  |  417 ++++++++++++
 include/dt-bindings/clock/samsung,s3c2443-clock.h  |   92 +++
 18 files changed, 756 insertions(+), 1114 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-10 15:15 UTC #1 lore raw

PATCH v4 1/7 clk: samsung: add pll_6552 variant for s3c2416

According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553 and while the pll_6553 matches exactly the one already implemented the pll_6552 differs to the one from the s3c64xx series.

The change is solely in the bit locations of the mdiv and pdiv values. All calculations are the same for both implementatons and even the proposed divider-values for specific frequencies in the manuals are the same.

Therefore implement a variant that simply uses the changed bit locations if necessary.

Signed-off-by Heiko Stuebner <[email protected]>

Acked-by Tomasz Figa <[email protected]>

---
 drivers/clk/samsung/clk-pll.c |   12 ++++++++++--
 drivers/clk/samsung/clk-pll.h |    1 +
 2 files changed, 11 insertions(+), 2 deletions(-)

drivers/clk/samsung/clk-pll.c +10 -2

index 529e11d..c37d033 100644
@@ -564,7 +564,9 @@ static const struct clk_ops samsung_pll46xx_clk_min_ops = {
 #define PLL6552_PDIV_MASK	0x3f
 #define PLL6552_SDIV_MASK	0x7
 #define PLL6552_MDIV_SHIFT	16
+#define PLL6552_MDIV_SHIFT_2416	14
 #define PLL6552_PDIV_SHIFT	8
+#define PLL6552_PDIV_SHIFT_2416	5
 #define PLL6552_SDIV_SHIFT	0
 
 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,

@@ -575,8 +577,13 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
 	u64 fvco = parent_rate;
 
 	pll_con = __raw_readl(pll->con_reg);
-	mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
-	pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
+	if (pll->type == pll_6552_s3c2416) {
+		mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
+		pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
+	} else {
+		mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
+		pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
+	}
 	sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
 
 	fvco *= mdiv;

@@ -773,6 +780,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 			init.ops = &samsung_pll36xx_clk_ops;
 		break;
 	case pll_6552:
+	case pll_6552_s3c2416:
 		init.ops = &samsung_pll6552_clk_ops;
 		break;
 	case pll_6553:

drivers/clk/samsung/clk-pll.h +1 -0

index 6c39030..ddf9029 100644
@@ -24,6 +24,7 @@ enum samsung_pll_type {
 	pll_4650,
 	pll_4650c,
 	pll_6552,
+	pll_6552_s3c2416,
 	pll_6553,
 };

Signature · 1 line

1.7.10.4

Mike Turquette

2013-12-23 20:07 UTC #2 lore raw

PATCH v4 1/7 clk: samsung: add pll_6552 variant for s3c2416

Quoting Heiko St?bner (2013-12-10 07:15:10)

Quoted 9 lines

According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553 and while the pll_6553 matches exactly the one already implemented the pll_6552 differs to the one from the s3c64xx series.
The change is solely in the bit locations of the mdiv and pdiv values. All calculations are the same for both implementatons and even the proposed divider-values for specific frequencies in the manuals are the same.

Quoted 5 lines

Therefore implement a variant that simply uses the changed bit locations if necessary.
Signed-off-by Heiko Stuebner <[email protected]>
Acked-by Tomasz Figa <[email protected]>

Acked-by Mike Turquette <[email protected]>

Quoted 58 lines

---
 drivers/clk/samsung/clk-pll.c |   12 ++++++++++--
 drivers/clk/samsung/clk-pll.h |    1 +
 2 files changed, 11 insertions(+), 2 deletions(-)

drivers/clk/samsung/clk-pll.c +10 -2

index 529e11d..c37d033 100644
@@ -564,7 +564,9 @@ static const struct clk_ops samsung_pll46xx_clk_min_ops = {
 #define PLL6552_PDIV_MASK      0x3f
 #define PLL6552_SDIV_MASK      0x7
 #define PLL6552_MDIV_SHIFT     16
+#define PLL6552_MDIV_SHIFT_2416        14
 #define PLL6552_PDIV_SHIFT     8
+#define PLL6552_PDIV_SHIFT_2416        5
 #define PLL6552_SDIV_SHIFT     0
 
 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,

@@ -575,8 +577,13 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
        u64 fvco = parent_rate;
 
        pll_con = __raw_readl(pll->con_reg);
-       mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
-       pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
+       if (pll->type == pll_6552_s3c2416) {
+               mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
+               pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
+       } else {
+               mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
+               pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
+       }
        sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
 
        fvco *= mdiv;

@@ -773,6 +780,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
                        init.ops = &samsung_pll36xx_clk_ops;
                break;
        case pll_6552:
+       case pll_6552_s3c2416:
                init.ops = &samsung_pll6552_clk_ops;
                break;
        case pll_6553:

drivers/clk/samsung/clk-pll.h +1 -0

index 6c39030..ddf9029 100644
@@ -24,6 +24,7 @@ enum samsung_pll_type {
        pll_4650,
        pll_4650c,
        pll_6552,
+       pll_6552_s3c2416,
        pll_6553,
 };

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-10 15:15 UTC #3 lore raw

PATCH v4 2/7 clk: samsung: add plls used by the s3c2443

In reply to Heiko Stübner

The s3c2443 uses different plls that are not present yet. Therefore add the two needed types.

Signed-off-by Heiko Stuebner <[email protected]>

Acked-by Tomasz Figa <[email protected]>

---
 drivers/clk/samsung/clk-pll.c |   72 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-pll.h |    2 ++
 2 files changed, 74 insertions(+)

drivers/clk/samsung/clk-pll.c +72 -0

index c37d033..461a6bf 100644
@@ -59,6 +59,72 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
 }
 
 /*
+ * PLL2126 Clock Type
+ */
+
+#define PLL2126_MDIV_MASK	(0xff)
+#define PLL2126_PDIV_MASK	(0x3f)
+#define PLL2126_SDIV_MASK	(0x3)
+#define PLL2126_MDIV_SHIFT	(16)
+#define PLL2126_PDIV_SHIFT	(8)
+#define PLL2126_SDIV_SHIFT	(0)
+
+static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 pll_con, mdiv, pdiv, sdiv;
+	u64 fvco = parent_rate;
+
+	pll_con = __raw_readl(pll->con_reg);
+	mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
+	pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
+	sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
+
+	fvco *= (mdiv + 8);
+	do_div(fvco, (pdiv + 2) << sdiv);
+
+	return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126_clk_ops = {
+	.recalc_rate = samsung_pll2126_recalc_rate,
+};
+
+/*
+ * PLL3000 Clock Type
+ */
+
+#define PLL3000_MDIV_MASK	(0xff)
+#define PLL3000_PDIV_MASK	(0x3)
+#define PLL3000_SDIV_MASK	(0x3)
+#define PLL3000_MDIV_SHIFT	(16)
+#define PLL3000_PDIV_SHIFT	(8)
+#define PLL3000_SDIV_SHIFT	(0)
+
+static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 pll_con, mdiv, pdiv, sdiv;
+	u64 fvco = parent_rate;
+
+	pll_con = __raw_readl(pll->con_reg);
+	mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
+	pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
+	sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
+
+	fvco *= (2 * (mdiv + 8));
+	do_div(fvco, pdiv << sdiv);
+
+	return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000_clk_ops = {
+	.recalc_rate = samsung_pll3000_recalc_rate,
+};
+
+/*
  * PLL35xx Clock Type
  */
 /* Maximum lock time can be 270 * PDIV cycles */

@@ -753,6 +819,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 	}
 
 	switch (pll_clk->type) {
+	case pll_2126:
+		init.ops = &samsung_pll2126_clk_ops;
+		break;
+	case pll_3000:
+		init.ops = &samsung_pll3000_clk_ops;
+		break;
 	/* clk_ops for 35xx and 2550 are similar */
 	case pll_35xx:
 	case pll_2550:

drivers/clk/samsung/clk-pll.h +2 -0

index ddf9029..5b64bdb 100644
@@ -13,6 +13,8 @@
 #define __SAMSUNG_CLK_PLL_H
 
 enum samsung_pll_type {
+	pll_2126,
+	pll_3000,
 	pll_35xx,
 	pll_36xx,
 	pll_2550,

Signature · 1 line

1.7.10.4

Mike Turquette

2013-12-23 20:07 UTC #4 lore raw

PATCH v4 2/7 clk: samsung: add plls used by the s3c2443

Quoting Heiko St?bner (2013-12-10 07:15:38)

Quoted 5 lines

The s3c2443 uses different plls that are not present yet. Therefore add the two needed types.
Signed-off-by Heiko Stuebner <[email protected]>
Acked-by Tomasz Figa <[email protected]>

Acked-by Mike Turquette <[email protected]>

Quoted 111 lines

---
 drivers/clk/samsung/clk-pll.c |   72 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-pll.h |    2 ++
 2 files changed, 74 insertions(+)

drivers/clk/samsung/clk-pll.c +72 -0

index c37d033..461a6bf 100644
@@ -59,6 +59,72 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
 }
 
 /*
+ * PLL2126 Clock Type
+ */
+
+#define PLL2126_MDIV_MASK      (0xff)
+#define PLL2126_PDIV_MASK      (0x3f)
+#define PLL2126_SDIV_MASK      (0x3)
+#define PLL2126_MDIV_SHIFT     (16)
+#define PLL2126_PDIV_SHIFT     (8)
+#define PLL2126_SDIV_SHIFT     (0)
+
+static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
+                               unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 pll_con, mdiv, pdiv, sdiv;
+       u64 fvco = parent_rate;
+
+       pll_con = __raw_readl(pll->con_reg);
+       mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
+       pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
+       sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
+
+       fvco *= (mdiv + 8);
+       do_div(fvco, (pdiv + 2) << sdiv);
+
+       return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126_clk_ops = {
+       .recalc_rate = samsung_pll2126_recalc_rate,
+};
+
+/*
+ * PLL3000 Clock Type
+ */
+
+#define PLL3000_MDIV_MASK      (0xff)
+#define PLL3000_PDIV_MASK      (0x3)
+#define PLL3000_SDIV_MASK      (0x3)
+#define PLL3000_MDIV_SHIFT     (16)
+#define PLL3000_PDIV_SHIFT     (8)
+#define PLL3000_SDIV_SHIFT     (0)
+
+static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
+                               unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 pll_con, mdiv, pdiv, sdiv;
+       u64 fvco = parent_rate;
+
+       pll_con = __raw_readl(pll->con_reg);
+       mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
+       pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
+       sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
+
+       fvco *= (2 * (mdiv + 8));
+       do_div(fvco, pdiv << sdiv);
+
+       return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000_clk_ops = {
+       .recalc_rate = samsung_pll3000_recalc_rate,
+};
+
+/*
  * PLL35xx Clock Type
  */
 /* Maximum lock time can be 270 * PDIV cycles */

@@ -753,6 +819,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
        }
 
        switch (pll_clk->type) {
+       case pll_2126:
+               init.ops = &samsung_pll2126_clk_ops;
+               break;
+       case pll_3000:
+               init.ops = &samsung_pll3000_clk_ops;
+               break;
        /* clk_ops for 35xx and 2550 are similar */
        case pll_35xx:
        case pll_2550:

drivers/clk/samsung/clk-pll.h +2 -0

index ddf9029..5b64bdb 100644
@@ -13,6 +13,8 @@
 #define __SAMSUNG_CLK_PLL_H
 
 enum samsung_pll_type {
+       pll_2126,
+       pll_3000,
        pll_35xx,
        pll_36xx,
        pll_2550,

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-31 20:03 UTC #5 lore raw

PATCH v4 2/7 clk: samsung: add plls used by the s3c2443

Hi Mike,

Am Montag, 23. Dezember 2013, 12:07:55 schrieb Mike Turquette:

Quoted 9 lines

Quoting Heiko St?bner (2013-12-10 07:15:38)
Quoted 5 lines
The s3c2443 uses different plls that are not present yet. Therefore add the two needed types.
Signed-off-by Heiko Stuebner <[email protected]>
Acked-by Tomasz Figa <[email protected]>
Acked-by Mike Turquette <[email protected]>

did you also take a look at the real clock driver too in
"[4/7] clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450"

because it looks like didn't get any response so far from you (and I just saw you acking the later s3c2410 driver)

Thanks
Heiko

Quoted 128 lines

Quoted 120 lines

---

 drivers/clk/samsung/clk-pll.c |   72
 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h
 |    2 ++
 2 files changed, 74 insertions(+)

drivers/clk/samsung/clk-pll.c +66 -0

index c37d033..461a6bf 100644
@@ -59,6 +59,72 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
 
 }
 
 /*
 
+ * PLL2126 Clock Type
+ */
+
+#define PLL2126_MDIV_MASK      (0xff)
+#define PLL2126_PDIV_MASK      (0x3f)
+#define PLL2126_SDIV_MASK      (0x3)
+#define PLL2126_MDIV_SHIFT     (16)
+#define PLL2126_PDIV_SHIFT     (8)
+#define PLL2126_SDIV_SHIFT     (0)
+
+static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
+                               unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 pll_con, mdiv, pdiv, sdiv;
+       u64 fvco = parent_rate;
+
+       pll_con = __raw_readl(pll->con_reg);
+       mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
+       pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
+       sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
+
+       fvco *= (mdiv + 8);
+       do_div(fvco, (pdiv + 2) << sdiv);
+
+       return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126_clk_ops = {
+       .recalc_rate = samsung_pll2126_recalc_rate,
+};
+
+/*
+ * PLL3000 Clock Type
+ */
+
+#define PLL3000_MDIV_MASK      (0xff)
+#define PLL3000_PDIV_MASK      (0x3)
+#define PLL3000_SDIV_MASK      (0x3)
+#define PLL3000_MDIV_SHIFT     (16)
+#define PLL3000_PDIV_SHIFT     (8)
+#define PLL3000_SDIV_SHIFT     (0)
+
+static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
+                               unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 pll_con, mdiv, pdiv, sdiv;
+       u64 fvco = parent_rate;
+
+       pll_con = __raw_readl(pll->con_reg);
+       mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
+       pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
+       sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
+
+       fvco *= (2 * (mdiv + 8));
+       do_div(fvco, pdiv << sdiv);
+
+       return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000_clk_ops = {
+       .recalc_rate = samsung_pll3000_recalc_rate,
+};
+
+/*

* PLL35xx Clock Type
*/

/* Maximum lock time can be 270 * PDIV cycles */

drivers/clk/samsung/clk-pll.c +0 -0

@@ -753,6 +819,12 @@ static void __init _samsung_clk_register_pll(struct

samsung_pll_clock *pll_clk,>

        }
        
        switch (pll_clk->type) {

drivers/clk/samsung/clk-pll.c +6 -0

+       case pll_2126:
+               init.ops = &samsung_pll2126_clk_ops;
+               break;
+       case pll_3000:
+               init.ops = &samsung_pll3000_clk_ops;
+               break;
 
        /* clk_ops for 35xx and 2550 are similar */
        case pll_35xx:
 
        case pll_2550:

drivers/clk/samsung/clk-pll.h +2 -0

index ddf9029..5b64bdb 100644
@@ -13,6 +13,8 @@
 
 #define __SAMSUNG_CLK_PLL_H
 
 enum samsung_pll_type {
 
+       pll_2126,
+       pll_3000,

Quoted 3 lines

        pll_35xx,
        pll_36xx,
        pll_2550,

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Heiko Stübner

author

2013-12-10 15:17 UTC #6 lore raw

PATCH v4 3/7 dt-bindings: add binding for clock-controller of s3c2443 and following

In reply to Heiko Stübner

Starting with the s3c2443 the s3c24xx series got a new clock tree compared to the previous s3c24xx socs. This binding describes the clock controller found in the s3c2443, s3c2416 and s3c2450 socs.

Signed-off-by Heiko Stuebner <[email protected]>

Acked-by Tomasz Figa <[email protected]>

---
 .../bindings/clock/samsung,s3c2443-clock.txt       |   56 ++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt

Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt new file +56 -0

new file mode 100644
index 0000000..a2d94c9
@@ -0,0 +1,56 @@
+* Samsung S3C2443 Clock Controller
+
+The S3C2443 clock controller generates and supplies clock to various controllers
+within the SoC. The clock binding described here is applicable to all SoCs in
+the s3c24x family starting with the s3c2443.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
+  - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
+  - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Some of the clocks are available only
+on a particular SoC.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s3c2443-clock.h header and can be used in device
+tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xti" - crystal input - required,
+ - "ext" - external clock source - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_uart" - external uart clock - optional,
+
+Example: Clock controller node:
+
+	clocks: clock-controller at 4c000000 {
+		compatible = "samsung,s3c2416-clock";
+		reg = <0x4c000000 0x40>;
+		#clock-cells = <1>;
+	};
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller (refer to the standard clock bindings for information about
+  "clocks" and "clock-names" properties):
+
+	serial at 50004000 {
+		compatible = "samsung,s3c2440-uart";
+		reg = <0x50004000 0x4000>;
+		interrupts = <1 23 3 4>, <1 23 4 4>;
+		clock-names = "uart", "clk_uart_baud2",
+				"clk_uart_baud3";
+		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
+				<&clocks SCLK_UART>;
+		status = "disabled";
+	};

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-10 15:17 UTC #7 lore raw

PATCH v4 4/7 clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450

In reply to Heiko Stübner

The three SoCs share a common clock tree which only differs in the existence of some special clocks.

As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch.

The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver.

Signed-off-by Heiko Stuebner <[email protected]>

Acked-by Tomasz Figa <[email protected]>

---
 arch/arm/mach-s3c24xx/Kconfig                     |    6 +
 drivers/clk/samsung/Makefile                      |    1 +
 drivers/clk/samsung/clk-s3c2443.c                 |  417 +++++++++++++++++++++
 include/dt-bindings/clock/samsung,s3c2443-clock.h |   92 +++++
 4 files changed, 516 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h

arch/arm/mach-s3c24xx/Kconfig +6 -0

index 8f1d327..2eeeb55 100644
@@ -670,6 +670,12 @@ config S3C2443_COMMON
 	  Common code for the S3C2443 and similar processors, which includes
 	  the S3C2416 and S3C2450.
 
+config S3C2443_COMMON_CLK
+	bool
+	help
+	  Temporary symbol to build the clock driver based on the common clock
+	  framework.
+
 config S3C2443_DMA
 	bool
 	help

drivers/clk/samsung/Makefile +1 -0

index 8eb4799..4c892c6 100644
@@ -8,4 +8,5 @@ obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
+obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
 obj-$(CONFIG_ARCH_S3C64XX)	+= clk-s3c64xx.o

drivers/clk/samsung/clk-s3c2443.c new file +417 -0

417 lines not on this page · raw message

include/dt-bindings/clock/samsung,s3c2443-clock.h new file +92 -0

92 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-10 15:18 UTC #8 lore raw

PATCH v4 5/7 ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs

In reply to Heiko Stübner

As the conversion to the common-clock-framework is done in multiple steps, it is necessary to prevent conflicts between the different struct clk implementations.

For this include the s3c24xx_setup_clocks function only when SAMSUNG_CLOCK is selected and make the socs we don't convert this time explicitly depend on SAMSUNG_CLOCK, which gets only selected automatically if COMMON_CLK is not enabled.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/mach-s3c24xx/Kconfig  |    4 ++++
 arch/arm/mach-s3c24xx/common.c |    2 ++
 2 files changed, 6 insertions(+)

arch/arm/mach-s3c24xx/Kconfig +4 -0

index 2eeeb55..3f1547c 100644
@@ -25,6 +25,7 @@ comment "S3C24XX SoCs"
 config CPU_S3C2410
 	bool "SAMSUNG S3C2410"
 	default y
+	depends on SAMSUNG_CLOCK
 	select CPU_ARM920T
 	select CPU_LLSERIAL_S3C2410
 	select S3C2410_CLOCK

@@ -38,6 +39,7 @@ config CPU_S3C2410
 
 config CPU_S3C2412
 	bool "SAMSUNG S3C2412"
+	depends on SAMSUNG_CLOCK
 	select CPU_ARM926T
 	select CPU_LLSERIAL_S3C2440
 	select S3C2412_DMA if S3C24XX_DMA

@@ -58,6 +60,7 @@ config CPU_S3C2416
 
 config CPU_S3C2440
 	bool "SAMSUNG S3C2440"
+	depends on SAMSUNG_CLOCK
 	select CPU_ARM920T
 	select CPU_LLSERIAL_S3C2440
 	select S3C2410_CLOCK

@@ -68,6 +71,7 @@ config CPU_S3C2440
 
 config CPU_S3C2442
 	bool "SAMSUNG S3C2442"
+	depends on SAMSUNG_CLOCK
 	select CPU_ARM920T
 	select CPU_LLSERIAL_S3C2440
 	select S3C2410_CLOCK

arch/arm/mach-s3c24xx/common.c +2 -0

index 4adaa4b..46af4e5 100644
@@ -319,6 +319,7 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 
 /* initialise all the clocks */
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
 					   unsigned long hclk,
 					   unsigned long pclk)

@@ -331,6 +332,7 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
 	clk_p.rate = pclk;
 	clk_f.rate = fclk;
 }
+#endif
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
 	defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-10 15:19 UTC #9 lore raw

PATCH v4 6/7 ARM: dt: add clock data for s3c2416

In reply to Heiko Stübner

This adds the clock controller itself, the xti clock on the smdk2416 as well as the clock references in the individual device nodes.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/boot/dts/s3c2416-smdk2416.dts |   13 ++++++++++
 arch/arm/boot/dts/s3c2416.dtsi         |   42 ++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)

arch/arm/boot/dts/s3c2416-smdk2416.dts +13 -0

index 59594cf..ea92fd6 100644
@@ -19,6 +19,19 @@
 		reg =  <0x30000000 0x4000000>;
 	};
 
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xti: xti {
+			compatible = "fixed-clock";
+			clock-frequency = <12000000>;
+			clock-output-names = "xti";
+			#clock-cells = <0>;
+		};
+	};
+
 	serial at 50000000 {
 		status = "okay";
 		pinctrl-names = "default";

arch/arm/boot/dts/s3c2416.dtsi +42 -0

98 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Heiko Stübner

author

2013-12-10 15:20 UTC #10 lore raw

PATCH v4 7/7 ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

In reply to Heiko Stübner

This converts the mentioned platforms to use the newly introduced driver for the common clock framework for them.

With this the whole legacy clock structure can go away too.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/mach-s3c24xx/Kconfig           |   14 +-
 arch/arm/mach-s3c24xx/Makefile          |    5 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c   |  171 --------
 arch/arm/mach-s3c24xx/clock-s3c2443.c   |  212 ----------
 arch/arm/mach-s3c24xx/common-s3c2443.c  |  675 -------------------------------
 arch/arm/mach-s3c24xx/common.c          |   16 +-
 arch/arm/mach-s3c24xx/common.h          |    6 +
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c |   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c   |    9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c   |    9 +-
 10 files changed, 41 insertions(+), 1115 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c

arch/arm/mach-s3c24xx/Kconfig +4 ~~-10~~

index 3f1547c..397c440 100644
@@ -49,12 +49,12 @@ config CPU_S3C2412
 
 config CPU_S3C2416
 	bool "SAMSUNG S3C2416/S3C2450"
+	select COMMON_CLK
 	select CPU_ARM926T
 	select CPU_LLSERIAL_S3C2440
 	select S3C2416_PM if PM
-	select S3C2443_COMMON
+	select S3C2443_COMMON_CLK
 	select S3C2443_DMA if S3C24XX_DMA
-	select SAMSUNG_CLKSRC
 	help
 	  Support for the S3C2416 SoC from the S3C24XX line

@@ -87,11 +87,11 @@ config CPU_S3C244X
 
 config CPU_S3C2443
 	bool "SAMSUNG S3C2443"
+	select COMMON_CLK
 	select CPU_ARM920T
 	select CPU_LLSERIAL_S3C2440
-	select S3C2443_COMMON
+	select S3C2443_COMMON_CLK
 	select S3C2443_DMA if S3C24XX_DMA
-	select SAMSUNG_CLKSRC
 	help
 	  Support for the S3C2443 SoC from the S3C24XX line

@@ -668,12 +668,6 @@ endif	# CPU_S3C2442
 
 if CPU_S3C2443 || CPU_S3C2416
 
-config S3C2443_COMMON
-	bool
-	help
-	  Common code for the S3C2443 and similar processors, which includes
-	  the S3C2416 and S3C2450.
-
 config S3C2443_COMMON_CLK
 	bool
 	help

arch/arm/mach-s3c24xx/Makefile +2 -3

index 7f54e5b..ba0e547 100644
@@ -26,7 +26,7 @@ obj-$(CONFIG_S3C2412_DMA)	+= dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)	+= pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)	+= sleep-s3c2412.o
 
-obj-$(CONFIG_CPU_S3C2416)	+= s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)	+= s3c2416.o
 obj-$(CONFIG_S3C2416_PM)	+= pm-s3c2416.o
 
 obj-$(CONFIG_CPU_S3C2440)	+= s3c2440.o clock-s3c2440.o

@@ -36,7 +36,7 @@ obj-$(CONFIG_S3C2440_DMA)	+= dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
 
-obj-$(CONFIG_CPU_S3C2443)	+= s3c2443.o clock-s3c2443.o
+obj-$(CONFIG_CPU_S3C2443)	+= s3c2443.o
 
 # PM

@@ -53,7 +53,6 @@ obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
 obj-$(CONFIG_S3C2410_IOTIMING)	+= iotiming-s3c2410.o
 obj-$(CONFIG_S3C2412_IOTIMING)	+= iotiming-s3c2412.o
 
-obj-$(CONFIG_S3C2443_COMMON)	+= common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)	+= dma-s3c2443.o
 
 #

arch/arm/mach-s3c24xx/clock-s3c2416.c deleted +0 ~~-171~~

171 lines not on this page · raw message

arch/arm/mach-s3c24xx/clock-s3c2443.c deleted +0 ~~-212~~

212 lines not on this page · raw message

arch/arm/mach-s3c24xx/common-s3c2443.c deleted +0 ~~-675~~

675 lines not on this page · raw message

arch/arm/mach-s3c24xx/common.c +14 -2

index 46af4e5..015e6c0 100644
@@ -145,7 +145,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idcode		= 0x32450003,
 		.idmask		= 0xffffffff,
 		.map_io		= s3c2416_map_io,
-		.init_clocks	= s3c2416_init_clocks,
 		.init_uarts	= s3c2416_init_uarts,
 		.init		= s3c2416_init,
 		.name		= name_s3c2416,

@@ -154,7 +153,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idcode		= 0x32443001,
 		.idmask		= 0xffffffff,
 		.map_io		= s3c2443_map_io,
-		.init_clocks	= s3c2443_init_clocks,
 		.init_uarts	= s3c2443_init_uarts,
 		.init		= s3c2443_init,
 		.name		= name_s3c2443,

@@ -537,3 +535,17 @@ struct platform_device s3c2443_device_dma = {
 	},
 };
 #endif
+
+#ifdef CONFIG_CPU_S3C2416
+void __init s3c2416_init_clocks(int xtal)
+{
+	s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+void __init s3c2443_init_clocks(int xtal)
+{
+	s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+}
+#endif

arch/arm/mach-s3c24xx/common.h +6 -0

index e46c104..d7323f1 100644
@@ -114,4 +114,10 @@ extern struct platform_device s3c2412_device_dma;
 extern struct platform_device s3c2440_device_dma;
 extern struct platform_device s3c2443_device_dma;
 
+#ifdef CONFIG_S3C2443_COMMON_CLK
+void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
+				    int current_soc,
+				    void __iomem *reg_base);
+#endif
+
 #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */

arch/arm/mach-s3c24xx/mach-s3c2416-dt.c +1 ~~-38~~

index f50454a..0a86953 100644
@@ -18,59 +18,23 @@
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <linux/serial_core.h>
 
 #include <asm/mach/arch.h>
 #include <mach/map.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the S3C2416 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
-	OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
-				"s3c2440-uart.0", NULL),
-	OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
-				"s3c2440-uart.1", NULL),
-	OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
-				"s3c2440-uart.2", NULL),
-	OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
-				"s3c2440-uart.3", NULL),
-	OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
-				"s3c-sdhci.0", NULL),
-	OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
-				"s3c-sdhci.1", NULL),
-	OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
-				"s3c2440-i2c.0", NULL),
-	{},
-};
-
 static void __init s3c2416_dt_map_io(void)
 {
 	s3c24xx_init_io(NULL, 0);
-	s3c24xx_init_clocks(12000000);
 }
 
 static void __init s3c2416_dt_machine_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table,
-				s3c2416_auxdata_lookup, NULL);
-
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	s3c_pm_init();
 }

@@ -86,6 +50,5 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
 	.map_io		= s3c2416_dt_map_io,
 	.init_irq	= irqchip_init,
 	.init_machine	= s3c2416_dt_machine_init,
-	 .init_time	= clocksource_of_init,
 	.restart	= s3c2416_restart,
 MACHINE_END

arch/arm/mach-s3c24xx/mach-smdk2416.c +7 -2

index f88e672..3ec6d49 100644
@@ -218,10 +218,15 @@ static struct platform_device *smdk2416_devices[] __initdata = {
 	&s3c2443_device_dma,
 };
 
+static void __init smdk2416_init_time(void)
+{
+	s3c2416_init_clocks(12000000);
+	samsung_timer_init();
+}
+
 static void __init smdk2416_map_io(void)
 {
 	s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
-	s3c24xx_init_clocks(12000000);
 	s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
 	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }

@@ -256,6 +261,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
 	.init_irq	= s3c2416_init_irq,
 	.map_io		= smdk2416_map_io,
 	.init_machine	= smdk2416_machine_init,
-	.init_time	= samsung_timer_init,
+	.init_time	= smdk2416_init_time,
 	.restart	= s3c2416_restart,
 MACHINE_END

arch/arm/mach-s3c24xx/mach-smdk2443.c +7 -2

index d9933fc..58da97b 100644
@@ -121,11 +121,16 @@ static struct platform_device *smdk2443_devices[] __initdata = {
 static void __init smdk2443_map_io(void)
 {
 	s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
-	s3c24xx_init_clocks(12000000);
 	s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
 	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init smdk2443_init_time(void)
+{
+	s3c2443_init_clocks(12000000);
+	samsung_timer_init();
+}
+
 static void __init smdk2443_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);

@@ -145,6 +150,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
 	.init_irq	= s3c2443_init_irq,
 	.map_io		= smdk2443_map_io,
 	.init_machine	= smdk2443_machine_init,
-	.init_time	= samsung_timer_init,
+	.init_time	= smdk2443_init_time,
 	.restart	= s3c2443_restart,
 MACHINE_END

Signature · 1 line

1.7.10.4

Tomasz Figa

2013-12-10 15:27 UTC #11 lore raw

v4 cover ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

In reply to Heiko Stübner

Hi Heiko,

Quoted 38 lines · On Tuesday 10 of December 2013 16:14:29 Heiko St?bner wrote:

Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs Changes since v2
- address comments from Tomasz Figa
- use new pll registration mechanism
- use fixed-rate clocks for xti etc
Heiko Stuebner (7):
clk: samsung: add pll_6552 variant for s3c2416
clk: samsung: add plls used by the s3c2443
dt-bindings: add binding for clock-controller of s3c2443 and following
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
ARM: dt: add clock data for s3c2416
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
 .../bindings/clock/samsung,s3c2443-clock.txt       |   56 ++
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |   13 +
 arch/arm/boot/dts/s3c2416.dtsi                     |   42 ++
 arch/arm/mach-s3c24xx/Kconfig                      |   18 +-
 arch/arm/mach-s3c24xx/Makefile                     |    5 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |  171 -----
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |  212 ------
 arch/arm/mach-s3c24xx/common-s3c2443.c             |  675 --------------------
 arch/arm/mach-s3c24xx/common.c                     |   18 +-
 arch/arm/mach-s3c24xx/common.h                     |    6 +
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c            |   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |    9 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-pll.c                      |   84 ++-
 drivers/clk/samsung/clk-pll.h                      |    3 +
 drivers/clk/samsung/clk-s3c2443.c                  |  417 ++++++++++++

Quoted 8 lines

 include/dt-bindings/clock/samsung,s3c2443-clock.h  |   92 +++
 18 files changed, 756 insertions(+), 1114 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h

I have already acked clock patches, so for remaining ones:

Reviewed-by Tomasz Figa <[email protected]>

Best regards,
Tomasz

Heiko Stübner

author

2013-12-23 13:11 UTC #12 lore raw

v4 cover ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

In reply to Heiko Stübner

Hi Kukjin,

it seems you didn't have the time for this series during your 2nd round.

I'm not sure what your plans/time constraint are, but according to the -rc5 release mail from Linus [0], 3.13 will at least reach -rc8 so it seems as if there is still a bit of time to for 3.14 stuff.

This series would really be a nice base for not only the other ccf-conversions (the already submitted s3c2410 and the s3c2412 which I'm currently working on) but also for broadening the dt-support, with the auxdata gone from the dt- board file.

Thanks
Heiko

[0] https://lkml.org/lkml/2013/12/22/70

Am Dienstag, 10. Dezember 2013, 16:14:29 schrieb Heiko St?bner:

Quoted 48 lines

Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs Changes since v2
- address comments from Tomasz Figa
- use new pll registration mechanism
- use fixed-rate clocks for xti etc
Heiko Stuebner (7):
clk: samsung: add pll_6552 variant for s3c2416
clk: samsung: add plls used by the s3c2443
dt-bindings: add binding for clock-controller of s3c2443 and following
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
ARM: dt: add clock data for s3c2416
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
 .../bindings/clock/samsung,s3c2443-clock.txt       |   56 ++
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |   13 +
 arch/arm/boot/dts/s3c2416.dtsi                     |   42 ++
 arch/arm/mach-s3c24xx/Kconfig                      |   18 +-
 arch/arm/mach-s3c24xx/Makefile                     |    5 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |  171 -----
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |  212 ------
 arch/arm/mach-s3c24xx/common-s3c2443.c             |  675
-------------------- arch/arm/mach-s3c24xx/common.c                     | 
 18 +-
 arch/arm/mach-s3c24xx/common.h                     |    6 +
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c            |   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |    9 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-pll.c                      |   84 ++-
 drivers/clk/samsung/clk-pll.h                      |    3 +
 drivers/clk/samsung/clk-s3c2443.c                  |  417 ++++++++++++
 include/dt-bindings/clock/samsung,s3c2443-clock.h  |   92 +++
 18 files changed, 756 insertions(+), 1114 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt delete
mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h

Kukjin Kim

2013-12-24 01:37 UTC #13 lore raw

v4 cover ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

Quoted 3 lines · Heiko St?bner

Hi Kukjin,

Hi,

Quoted 8 lines

it seems you didn't have the time for this series during your 2nd round.
I'm not sure what your plans/time constraint are, but according to the - rc5
release mail from Linus [0], 3.13 will at least reach -rc8 so it seems as if
there is still a bit of time to for 3.14 stuff.

Good news to us :-)

Quoted 7 lines

This series would really be a nice base for not only the other ccf- conversions
(the already submitted s3c2410 and the s3c2412 which I'm currently working on)
but also for broadening the dt-support, with the auxdata gone from the dt- board file.

I agreed, let me try to send one more pull-request for 3.14 after finishing review of your patches.

Thanks and Merry Christmas,
Kukjin

Quoted 57 lines

Thanks
Heiko
[0] https://lkml.org/lkml/2013/12/22/70
Am Dienstag, 10. Dezember 2013, 16:14:29 schrieb Heiko St?bner:
Quoted 48 lines
Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs Changes since v2
- address comments from Tomasz Figa
- use new pll registration mechanism
- use fixed-rate clocks for xti etc
Heiko Stuebner (7):
clk: samsung: add pll_6552 variant for s3c2416
clk: samsung: add plls used by the s3c2443
dt-bindings: add binding for clock-controller of s3c2443 and following
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
ARM: dt: add clock data for s3c2416
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
 .../bindings/clock/samsung,s3c2443-clock.txt       |   56 ++
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |   13 +
 arch/arm/boot/dts/s3c2416.dtsi                     |   42 ++
 arch/arm/mach-s3c24xx/Kconfig                      |   18 +-
 arch/arm/mach-s3c24xx/Makefile                     |    5 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |  171 -----
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |  212 ------
 arch/arm/mach-s3c24xx/common-s3c2443.c             |  675
-------------------- arch/arm/mach-s3c24xx/common.c                     |
 18 +-
 arch/arm/mach-s3c24xx/common.h                     |    6 +
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c            |   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |    9 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-pll.c                      |   84 ++-
 drivers/clk/samsung/clk-pll.h                      |    3 +
 drivers/clk/samsung/clk-s3c2443.c                  |  417 ++++++++++++
 include/dt-bindings/clock/samsung,s3c2443-clock.h  |   92 +++
 18 files changed, 756 insertions(+), 1114 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt delete
mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h

Sachin Kamat

2013-12-24 10:20 UTC #14 lore raw

v4 cover ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

Hi Kukjin,

Quoted 16 lines · Kukjin Kim

Quoted 3 lines · Heiko St?bner
Hi Kukjin,
Hi,
Quoted 8 lines
it seems you didn't have the time for this series during your 2nd round.
I'm not sure what your plans/time constraint are, but according to the - rc5
release mail from Linus [0], 3.13 will at least reach -rc8 so it seems as if
there is still a bit of time to for 3.14 stuff.
Good news to us :-)

Quoted 8 lines

Quoted 7 lines
This series would really be a nice base for not only the other ccf- conversions
(the already submitted s3c2410 and the s3c2412 which I'm currently working on)
but also for broadening the dt-support, with the auxdata gone from the dt- board file.
I agreed, let me try to send one more pull-request for 3.14 after finishing review of your patches.

While at it please also try to send the remaining pending patches.

Signature · 2 lines

With warm regards,
Sachin

kgene at kernel.org

2014-01-10 08:30 UTC #15 lore raw

v4 cover ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework

In reply to Heiko Stübner

Quoted 50 lines · Heiko St?bner

Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs Changes since v2
- address comments from Tomasz Figa
- use new pll registration mechanism
- use fixed-rate clocks for xti etc
Heiko Stuebner (7):
clk: samsung: add pll_6552 variant for s3c2416
clk: samsung: add plls used by the s3c2443
dt-bindings: add binding for clock-controller of s3c2443 and following
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
ARM: dt: add clock data for s3c2416
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
 .../bindings/clock/samsung,s3c2443-clock.txt       |   56 ++
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |   13 +
 arch/arm/boot/dts/s3c2416.dtsi                     |   42 ++
 arch/arm/mach-s3c24xx/Kconfig                      |   18 +-
 arch/arm/mach-s3c24xx/Makefile                     |    5 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |  171 -----
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |  212 ------
 arch/arm/mach-s3c24xx/common-s3c2443.c             |  675 -------------------
-
 arch/arm/mach-s3c24xx/common.c                     |   18 +-
 arch/arm/mach-s3c24xx/common.h                     |    6 +
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c            |   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |    9 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-pll.c                      |   84 ++-
 drivers/clk/samsung/clk-pll.h                      |    3 +
 drivers/clk/samsung/clk-s3c2443.c                  |  417 ++++++++++++
 include/dt-bindings/clock/samsung,s3c2443-clock.h  |   92 +++
 18 files changed, 756 insertions(+), 1114 deletions(-)
 create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h

Quoted 2 lines

--
1.7.10.4

Heiko,
Looks nice to me and I'm going to send this series to clk tree for v3.14.

Mike,
This series got you and Tomasz's ack for 3.14. Since major change is for clk stuff and there is no dependency with samsung tree, I'd like to send pull-request for this series to you for v3.14 tonight. If any problems, please kindly let me know.

Thanks,
Kukjin